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Review

Recent Research for HZO-Based Ferroelectric Memory towards In-Memory Computing Applications

by
Jaewook Yoo
1,
Hyeonjun Song
1,
Hongseung Lee
1,
Seongbin Lim
1,
Soyeon Kim
1,
Keun Heo
2,*,† and
Hagyoul Bae
1,*,†
1
Department of Electronic Engineering, Jeonbuk National University, Jeonju 54896, Republic of Korea
2
Semiconductor Science and Technology, Jeonbuk National University, Jeonju 54896, Republic of Korea
*
Authors to whom correspondence should be addressed.
†
These authors contributed equally to this work.
Electronics 2023, 12(10), 2297; https://doi.org/10.3390/electronics12102297
Submission received: 3 April 2023 / Revised: 30 April 2023 / Accepted: 12 May 2023 / Published: 19 May 2023
(This article belongs to the Special Issue Advanced CMOS Devices and Applications)
Browse Figures
Versions Notes

Abstract

:
The AI and IoT era requires software and hardware capable of efficiently processing massive amounts data quickly and at a low cost. However, there are bottlenecks in existing Von Neumann structures, including the difference in the operating speed of current-generation DRAM and Flash memory systems, the large voltage required to erase the charge of nonvolatile memory cells, and the limitations of scaled-down systems. Ferroelectric materials are one exciting means of breaking away from this structure, as Hf-based ferroelectric materials have a low operating voltage, excellent data retention qualities, and show fast switching speed, and can be used as non-volatile memory (NVM) if polarization characteristics are utilized. Moreover, adjusting their conductance enables diverse computing architectures, such as neuromorphic computing with analog characteristics or ‘logic-in-memory’ computing with digital characteristics, through high integration. Several types of ferroelectric memories, including two-terminal-based FTJs, three-terminal-based FeFETs using electric field effect, and FeRAMs using ferroelectric materials as capacitors, are currently being studied. In this review paper, we include these devices, as well as a Fe-diode with high on/off ratio properties, which has a similar structure to the FTJs but operate with the Schottky barrier modulation. After reviewing the operating principles and features of each structure, we conclude with a summary of recent applications that have incorporated them.

1. Introduction

Software is being developed to develop learning algorithms for machine learning, deep learning, and artificial intelligence (AI). Hardware must also be developed that matches the performance of this software [1,2,3]. Structurally separated processing and memory devices have high energy costs and poor data bandwidth performance (Von Neumann bottlenecks) [4,5]. The human brain shows high accuracy and as it calculates and remembers in the analog domain [6,7]. Therefore, neuromorphic systems that imitate the human brain can be expected to overcome the Von Neumann bottleneck. Efforts are also underway to overcome the so-called “memory wall”, i.e., the speed gap between logic and memory in the current CMOS stage, which occurs when hundreds of processes are performed in parallel by a graphic processing unit or custom-designed processor [8,9,10,11,12]. Resistive random-access memory (RRAM), phase change material (PCM), and magnetic random-access memory (MRAM) have been proposed as new non-volatile forms of memory that reduce the physical distance between computing components and data for memory and processing to overcome the fundamental limitations of existing CMOS systems [13,14,15,16]. However, these candidates are too slow, possess only a limited data bandwidth, and offer no price advantage [14]. As an alternative, in-memory computing has been proposed as a means of breaking away from the Von Neumann structure itself. In-memory computing improves latency and energy by performing calculations without physical separation from the storage where the data are located. Ferroelectric-based non-volatile memory with independent switching mechanisms and high-power efficiency has recently been recognized for its potential in neuromorphic and in-memory computing [17,18,19,20,21,22].
Ferroelectric materials are those with spontaneous two-way remanent polarization even in the absence of an electric field applied from the outside. Perovskite, for example, is a well-known ferroelectric material [23,24,25,26]. Perovskite may possess polarization properties depending on the location of Ti or Zr cations. In general, a phase transition occurs to tetragonal systems with ferroelectricity at low temperatures. When an external electric field higher than the coercive field (Ec) is applied, the position of the positive ion in the material moves to the opposite position compared to the conventional one, and polarization is reversed [26,27,28]. Accordingly, even when an electric field is not applied, binary states of 0 and 1 can be obtained by using reversing polarization. For this reason, these materials have begun to attract attention as an NVM [29]. However, polarization is reduced by an irregular interface layer formed between the silicon and ferroelectric material, reducing ferroelectricity, and for that reason is not compatible with the CMOS process. Moreover, since the size of the metal atom is relatively large and has a three-dimensional structure, ferroelectric properties do not appear in thin films of 50~70 nm or less [30].
In 2011, it was reported that SiO2 doping performed on an HfO2 thin film resulted in the expression of ferroelectricity. Since then, doping attempts with Si, Zr, Al, Y, Gd, Sr, La, etc., have been made [31,32,33,34,35,36,37,38,39,40,41]. Among these, Zr has the advantage of having a lower heat treatment temperature than other dopants and a similar atomic radius and lattice parameter to Hf, so HZO (HF1−xZrxO2) doped with Zr in Hf is receiving a lot of attention. HZO shows ferroelectric characteristics as its crystal structure between an electrode and a ferroelectric thin film is changed by stress from a conventional monoclinic phase to an orthorhombic phase at a temperature of 400~600 °C. HZO shows the highest ferroelectricity when the composition ratio of Hf and Zr is 1:1, and since HZO is usually deposited through atomic layer deposition (ALD), the composition ratio can be controlled and thin films can be produced easily [42,43]. In addition, HZO has ferroelectric characteristics even in thin films, so it is easy to integrate into devices and is compatible with existing CMOS processes [44]. However, studies noted its insufficient endurance, sustainability, and reliability, as well as the difficulty associated with manufacturing the back-end-of-line (BEOL) process at high temperatures. Ferroelectric memory can be classified into four types: ferroelectric tunnel junction (FTJ), Fe-diode with diode operation, FeFET with field effects, and ferroelectric random-access memory (FeRAM) [23,24,44]. This review paper introduces the operation of these four types of memory devices and some of their applications.

2. Ferroelectric Memory Operation Category

2.1. Ferroelectric Tunneling Junction (FTJ)

A FTJ is based on tunneling current conversion between the upper and lower metal electrodes and ferroelectrics. FTJs were first proposed by Esaki et al. in 1971 and only began to attract attention as it became possible to manufacture a very thin high-quality ferroelectric thin film [27,45]. FTJs have a metal-ferroelectric-metal (MFM) structure in which electrodes are formed on both sides of a nanometer thick of ferroelectric thin film. The potential barrier of the energy band between the electrode and the ferroelectrics varies depending on the polarization direction of the ferroelectric, and the amount of tunneling current changes with the change in resistance (a phenomenon called tunneling electrical resistance (TER)) [30,46]. TER occurs through three mechanisms: “direct tunneling” (when electrons pass directly through the tunneling barrier), “Fowler-Nordheim tunneling” (when electron tunneling occurs in a relatively thick tunneling barrier), and “thermionic emission” (when carriers receive thermal energy and exceed potential barrier) [47].
The bistable resistance states for the two opposite polarities can be obtained, which means that they are eventually polarized to the low resistance (LRS) and high resistance states (HRS) as shown in energy band diagrams of Figure 1a,b. FTJs can be driven at low power because the program and erase occurs in nanoseconds and do not lose data thanks to a non-destructive read process. In principle, the on/off states of an FTJ follow linear or quasi-linear I-V relationships, so an additional selector device is required to reduce the skip current in the crossbar arrangement.
The FTJ using tunneling current causes problems from thin films compared to hafnium-based materials and other ferroelectric devices. When polarization is reversed due to a high Ec value (~1 MV/cm), a hafnium-based ferroelectric has a small voltage margin, causing failures and poor cycling endurance. In addition, a high tunneling current may occur that traps electrons during operation. Trapping affects the barrier via remanent polarization and lowers the LRS and HRS values. Moreover, when a very thin polycrystalline layer is used, the memory window (MW) is dramatically reduced as parasitic currents are generated due to unwanted conduction from the interface. To address this problem, a structural metal-insulator-ferroelectric-metal (MIFM) with additional tunneling barriers inserted into the dielectric membranes has been explored as an alternative [46,48,49]. Figure 1c,d show that direct tunneling and Fowler-Nordheim tunneling contribute to tunneling current, respectively. Although the current density is slightly reduced from the stack structure, it can be useful for neuromorphic computing using large-scale parrel arrays.
Hwang et al. examined an FTJ with an MIFM structure by inserting a TiO2 layer to increase the ferroelectricity of the HZO films. The insertion layer increased the TER ratio of the device (which had an asymmetric structure). Figure 2a shows that the TER was maintained up to 107 times when a 10 μs bipolar pulse was applied. In addition, the TER ratio of the device was measured for 28 h (Figure 2b), and their research confirmed that the ratio was maintained for more than 10 years through the fitting [49].

2.2. Ferroelectric Diode (Fe-Diode)

Fe-diodes use polarization inversion caused by Schottky barrier modulation at an interface between a metal electrode and a ferroelectric thin film. The molecular structure and energy band diagram of the TiN/HZO/TiN Fe-diode is exhibited in Figure 3a,b, respectively. In a conventional metal-semiconductor contact, a spatial charge region in the semiconductor is formed to align the Fermi level, and a charge exacts same and opposite exists on the interface of the metal. The interfacial charge of a single ferroelectric Schottky diode and the band diagram is therefore subject to continuous and sustainable variability by the application of an external electric field [50,51]. The positive and negative polarization charges result in the accumulation of electrons that, respectively reduce the barrier height and increase the band bending by the positively charged oxygen vacancy. The current-voltage characteristic has a bistable operation due to the polarization dependence of the Schottky barrier. In the ferroelectric, as the rigidity of the lattice increases, the dielectric constant decreases in inverse proportion to the increasing electric field [50]. After polarization inversion, the changed electric field of the ferroelectric, and the depletion width of the Schottky diode decrease linearly until the depletion region end is zero at the maximum value of the interface. Finally, the transmission characteristic of the ferroelectric Schottky diode is obtained from a bias exceeding the threshold voltage.
Figure 3c shows the I-V characteristics of an Fe-diode [52]. The blue and red lines refer to positive voltage sweep and negative voltage sweep. In the former, the current becomes high and changes to a positive forward diode, while in the latter case, the current remains high and changes to a negative forward diode.
Fe-diodes and FTJs are both two-terminal devices, but the Fe-diode differs in its unique nonlinearity, which is defined as the ratio of the read current in V r and V r /2 attributable to the Schottky barrier. This means that the leakage current may be effectively reduced at the intersection of the array. Therefore, each memory cell and an external selector device need not be additionally connected in series. Moreover, if the two-terminal device repeatedly switches ferroelectric polarization, an error occurs during the read operation. The generated error can be solved by restoring the initial polarization state using the existing read pulse and inversion pulse as inputs.

2.3. Ferroelectric Field Effect Transistor (FeFET)

A FeFET incorporates a ferroelectric material into a gate oxide and is a non-destructive method that induces a change in current in a channel according to the polarization switching of the ferroelectric material. For this reason, the electric field that reaches the channel can be reduced, and the switching speed of the polarization is brisk [44,47]. Fast read/write operations are possible that use less power than static random-access memory (SRAM) and dynamic random-access memory (DRAM). Even if the gate voltage applied from the outside is stopped, the remanent polarization of the ferroelectric remains and can be applied to nonvolatile memory, and the character appears as hysteresis in the transfer curve [53]. In short, FeFET employs the same driving method as an existing FET in which ferroelectricity in the insulator site of the existing FET structure is used to generate an inverse layer of the semiconductor channel. It differs, however, in that the polarization of the ferroelectric induced by the applied gate voltage changes the threshold voltage [54]. This difference in threshold voltage is defined as MW, which can be obtained by multiplying the Ec by the thickness of the ferroelectric material and then doubling the result.
A Hf-based ferroelectric material has a larger Ec value than other materials, so it is easy to scale down and implement a high MW, though the issue of write endurance and read-after-write delay due to retention and parasitic charge trapping remains. This can be addressed by using a MIFM structure that inserts an insulating layer or by adding a layer of oxide with good conductivity to the FeFET channel. Mo et al. used an ultrathin IGZO channel in FeFET, and when the P/E voltage is higher than 2V, Vth is effectively shifted to record high endurance and retention [55,56]. The former characteristics can be determined through drain current measurement over time in the absence of applied voltage, and the latter characteristics can be extracted in the number of cycles by repeatedly applying positive/negative voltage pulses. When the program and erase were operated 108 times, 2Pr = 15 μC/cm2 was recorded without wake-up and significant degradation. In addition, it has been confirmed that both the program and the erase state are maintained for at least 1 year. Hoffmann et al. achieved high write endurance by inserting SiNx layers to improve the parasitic charge trapping of FeFETs [57]. It has been confirmed that the retention degradation caused by the reverse conversion of ferroelectric domains in a large demarcation theater is capable of overcoming retention instability by controlling the gate work function. Gaddam et al. reported the use of HfO2 as a seed layer above and below HZO in a MFM structure composed of TiN-HZO-TiN (Figure 4a) [58]. Figure 4b shows that the thickness of the insert layer is inversely proportional to its ferroelectric characteristics, and a 1 nm seed layer in the HZO bottom layer of HZO yields a maximum (Pr) of 22.1 μC/cm2, while a 1 nm seed layer inserted into the upper layer of HZO yields a maximum (Pr) of 19.6 μC/cm2. Endurance and retention characteristics were measured and compared, which can be confirmed in Figure 4c,d. In both cases, the upper and lower layer show improved properties after the insert layer is added.

2.4. Ferroelectric RAM (FeRAM)

FeRAM is a memory with a 1T-1C structure that uses a ferroelectric as a capacitor-based material [59]. FeRAM is similar to DRAM in which the capacity layer has been replaced by a nonlinear dielectric, and the plate line of FeRAM, unlike DRAM, does not maintain a constant voltage because it requires pulses to switch the ferroelectric polarization direction [47]. The binary information is stored in the ferroelectric capacitor and the transistor allows random access for read/write operations. Because ferroelectricity is used, it has NVM characteristics, but the stored values have destructive characteristics because the polarization is detected by the read pulse as to whether it is inverted, and the cell needs to be recovered.
Unfortunately, FeRAM has the disadvantage of having a larger cell size than other memories because it requires a plate line. Accordingly, FeRAM footprints range from 15 to 20 F2, making them larger than other ferroelectric memory devices, including FeFETs (4–8 F2), FTJs (4 F2), and Fe-diodes (4 F2). Therefore, these are unlikely candidates for next-generation ferroelectric devices because integration is more difficult even if a scale-down is performed [44].

3. Ferroelectric Device Application

Recently, researchers have focused on implementing artificial neurons and synapses with memory devices using ferroelectric materials and using these in neuromorphic computing systems. [60,61,62,63,64,65]. The basic behavior of computing is based on the matrix product of the voltage generated in artificial spiking neurons and the variable resistance called synapses [66]. Conventional CMOS can also construct neurons and synapses, but it requires a great deal of unit devices, resulting in low energy efficiency and difficulty in device integration [67]. Hf-based ferroelectric materials have a bistable polarization state and thus can be used as a non-volatile memory that stores binary information via the regulation of electric field strength [68]. Hf-based ferroelectric devices are stochastically capable of unexpected switching and multi-value polarization control and have a larger band gap (5.0 to 5.5 eV) than perovskite-structured ferroelectric devices (3 to 4 eV). Their high stability against leakage current renders them suitable for high-speed and low-power storage applications even if the scale of the device is reduced in charge-based ferroelectric memory devices (three-terminal devices). Furthermore, two-terminal ferroelectric memory devices are available for high-performance, low-power, and large-scale parallel memory computing applications due to their excellent analog switching characteristics, high nonlinearity, and uniformity [69,70,71,72,73]. However, the two-terminal device has current density, sneak current, and retention characteristics, and the three-terminal device has endurance, and the number of states in the scaled-down device causes problems. This section highlights the benefits of ferroelectric devices as memory devices from an application perspective.

3.1. Two-Terminal Devices

3.1.1. FTJ

Neuromorphic applications perform many analog tasks such as addition, multiplication, etc., and require linear and symmetric conductance tuning, low current write-read operations, fast transition speed, and high endurance. [74,75]. In the MFM structure of a FTJ or MFIM structure with an added insertion layer, related studies are noted because the current density is low, and a crossbar arrangement structure is possible [76]. In general, when the crossbar arrangement structure is expanded through the linear I-V characteristics of FTJ, there is the problem of high current flow from high conductivity. However, research has been conducted to provide ultra-low conductivity and ultra-low current by developing nonlinear I-V characteristics [77]. In short, FTJ brings great advantages in terms of large-scale parallel computing and integration [78].
Reservoir computing (RC) refers to energy-consuming networks that compute time data. They have attracted attention for their low cost of learning-only weights among reading layers [79]. Currently, data processing power must be improved, and research is ongoing to develop a dynamic RC hardware system by combining it with an RRAM-based readout layer using nonlinear features based on FTJ devices. The RRAM used in one experiment showed stable Set/Reset operation from the I-V curve by measuring 1T-1R 100 times. When the dielectric effect is removed from the polarization current over time in the FTJ; four peak values from the beginning of the polarization current are used as RC computing nodes. This experiment confirmed the trend of the recognition accuracy of the RC hardware system simulation value and the measured value matched for digital signals.
Chen et al. have reported electron synapses for neuromorphic systems that use three-dimensional vertical HZO-based FTJs, which can be confirmed in Figure 5a [80]. Throughout the training, the FTJ synapse showed analog-like conductivity and low energy consumption characteristics when synapse weights were updated, as well as high integration performance. As shown in Figure 5b,c, implemented in hardware, the synapse was trained by applying boost/decrease pulses through a 1/2 bias to change conductivity. When the original state is maintained, caution is needed because both the word line and the cell related to the bit line can be selected if an appropriate bias is not applied. Subsequently, as shown in Figure 5d, recognition accuracy of 96% was confirmed through 50 test character patterns through a hardware neural network (HNN) application.
Ota et al. used an FTJ that enhanced the performance and reliability of in-memory reinforcement learning (RL) through structural and material engineering, which can be confirmed in Figure 6a [81]. Compared to conventional memristors, which are difficult to program for accurate conductive states, RL can achieve human-level performance on a variety of control or decision-making tasks [82]. As shown in Figure 6b, the simulation of the standard problem showed that the training speed could be optimized at the standard deviation value (σ) and at the same normalized conductance change by adjusting the pulse voltage. Even at an optimal pulse voltage, if the σ increased, the minimum convergence time also increased, which means that the smaller σ better maximizes RL performance in Figure 6c. It was confirmed that the endurance is improved as the voltage margin (Vm) increases. As shown in Figure 6d,e, to increase Vm, the thickness of HZO and the concentration of Zr should be reduced. In this case, it is advantageous to reduce the thickness of the HZO in order to secure the variability of the RL system. Vm fluctuation with respect to the scale of the device can be solved by voltage compensation.
In the crossbar array, the parasitic component between the sneak path current and the mutual is fatal to the FTJ’s operation pursuant to Kirchhoff’s current law, and as a result, the sum of the currents is difficult to determine by a subsequent amplifier [67,78,83]. Goh et al. implemented a crossbar array without a selector using TaN as the insertion layer to prevent sneak current and confirmed that this was possible up to 4 kbit [84]. With the addition of the insertion layer, stable intermediate states of 30 or more, linear potentiation and depression are possible, as is the possibility of synapse implementation with long-term reinforcement and suppression, spiking-timing-dependent plasticity (STDP), and low energy consumption. As a result, we looked at instances of neuromorphic computing and in-memory that used an HZO−based FTJ compatible with CMOS as a synaptic device. In addition, we identified the difficulties in implementing these in large crossbar array environments and briefly summarized the research that sought solutions to these problems.
Kim et al. implemented a physical unreachable function (PUF) by simulating a 4 × 4 FTJ array [85]. PUF uses unique variability as an electrical parameter, compared to storing sequential passwords in existing memory devices. It is attracting attention because it has advantages in terms of price and is strong against side-channeling attacks. To implement this PUF, RRAM was considered a promising structure, and thus research was initiated to use it as an encryption device using FTJ. This study was simulated with an FTJ array of three sizes. It has been confirmed that reliability due to deviation between devices has more influence than reliability due to the scale-down of devices. That being said, even if the FTJ is scaled down, a stable operation may be performed in the intersection array. Lim et al. proposed SR-FTJ (self-rectifying-FTJ) through simulation that allows content-addressable memory (CAM) and PUF to operate in two layers [86]. CAM is specialized in in-memory computing, specializing in high-speed search of cache controllers or routers. However, since it has a security problem, research has been conducted in giving it high area efficiency by vertically combining it with the PUF introduced above. A certain difference in the leakage current of SR-FTJ was used as CAM data, and the leakage current was used as a value of PUF. Although its performance is still low, such memory can reduce its area by 88.1 to 97.4% compared to the previous one.

3.1.2. Fe-Diode

A design of a Hf-based Fe-diode was published in 2020 by Luo et al. [52]. The current density and nonlinearity were very high compared to the widely examined perovskite. Relative to FTJ, a higher on/off ratio could be obtained using Schottky contact. The following year, a study conducted by Bae described a diode formed by stacking an HZO layer on an oxide IGZO layer [87]. When IGZO and a ferroelectric are combined, they have high mobility and ideal SS, and high retention and endurance characteristics [55,56]. Therefore, when IGZO is efficiently positive bias and the polarization of ferroelectricity is up-polar, and negative biases and polarization of the ferroelectricity is down-polar, the charges have a depletion state and an accumulation state, respectively. The single device had a high on/off ratio of 3 × 105 and can be used as a high-speed, low-power non-volatile memory operating at 800 ps and 0.8 fJ. To implement logic-in-memory, the Boolean logic ‘NOT’ was operated using two diodes, with a significant difference in input/output current of as much as 104. In addition, a Fe-diode that combines HZO and IGZO called TCAM (Ternary-Content-Addressable-Memory) was implemented using non-volatile and ambipolar characteristics. This was verified as a potential device for in-memory data processing and neuromorphic computing [88].
To implement logic-in-memory with an Fe-diode, researchers have sought to improve the retention performance through the insertion of a HfOx layer into the HZO layer [89]. Since the retention defect in the ferroelectric was caused by the leakage current and the resulting trapping effect, retention performance was improved by adding the HfOx insertion layer [90]. A logic ‘XOR’ operation was performed on these devices by three sequential cycles (write 1, write 2, and read). The logical variables p and q were used for 16 Boolean functions. For one fluorine function, for example, 0 and 1 were excluded when 0 and 1 are 0 V and +7.5 V in the write cycle, and 0 and 1 operate when each was −4 V and 4 V in the read cycle. The operation was confirmed with the pulse results, and the experiment confirmed that this can be used as a logic-in-memory device in an MFIM structure in which an insertion layer is added to the ferroelectric layer.

3.2. Three-Terminal Devices

3.2.1. FeFET

A FeFET has a similar driving method as MOSFET, therefore efforts have been made to improve memory performance using a structural approach. An HZO-based FinFET device was investigated by Bae et al. [91]. Space and energy distributions were extracted from the trap density of the ferroelectric layer and interface layer, which were stacked on the gate, through low-frequency noise measurement (a non-destructive analysis). In addition, degradation due to radiation damage was analyzed based on the interface trap and bulk trap. A 3D FeFET was developed by Florent et al. that connected three transistors in series in the vertical direction, confirming the potential for achieving CMOS process compatibility and high integration as an NVM. To significantly improve on the low endurance characteristics in the three-terminal device created by Liao et al., a 3D GAA nano-sheet was structurally introduced, and the corner dead zone of ferroelectric polarization was suppressed [92]. In Figure 7a, HZO is used as a double layer to enable multiple Ec, which can store 3 bits of data. Figure 7b shows that the relatively nonuniform vectors at the edge of the GAA offset each other for a single HZO film using TCAD, resulting in weak polarization. In Figure 7c,d, the high endurance of 1011 and the metal-HZO interface dead layer are improved by using HZO as a double layer. Using the ITO-IGZO heterojunction channel developed by Chen et al., one study showed that the top interface defects can be self-compensated in the top gate and dual gate structure to improve the ultra-low sub-pA leakage, disturb-free, and sneak-current-free read/write operations [93]. First, the defect self-compensation effect on the ITO-IGZO channel FeFET, as well as the FeFET using only the IGZO channel, was investigated as the top gate, and it was confirmed that the trapping/de-trapping of electrons in the IGZO channel device lost the hysteresis response. As a result, MW converged to 0, and Figure 8a shows that the deep-level trap density of the low IGZO channel device is 100 times higher than that of the ITO-IGZO channel device. XPS analysis suggests that oxygen vacancy in Figure 8b is less in ITO-IGZO devices than in IGZO devices because metals with high bond dissociation energy (BDE) suppress oxygen defects. Meanwhile, read-after-write delay tests were performed on devices with BEOL dual gate and IGZO channel devices, and delays of 200 ns and 10 s were observed (Figure 8c), respectively. As illustrated in the energy band diagram of Figure 8d, interface and bulk deep-level traps are effectively passivated by the self-compensation effect. Finally, BEOL, which was structurally and thermally disadvantageous, was developed as a BEOL top gate FeFET with a very low delay value of 200 ns and an ideal SS of 62 mV/dec using heterogeneous bonding channels.
Unlike a two-terminal device, an FET structure changes channel conductivity by the gate and determines the weight of the input/output. This system shows an advantage in online learning because the learning and option are easily separated [44,94,95]. TiN/HZO/TiN structures were created using a 10 nm HZO thin film, and remanent polarization was measured in three ways (Figure 9a–c) to investigate synaptic properties [96]. The best way for remanent polarization proved to be increasing the voltage amplitude while retaining the same pulse interval. In this way, 32 polarization states were generated and converted into channel current states by simulation, and the MNIST simulation showed a pattern recognition accuracy of 84.34%, as shown in Figure 9d,e. Storage computing systems operating based on the parallel computing of FeFETs examined have been shown by Nako et al. to be well-suited for large-scale in-memory computing, which is updated over time in real-world applications such as speech recognition via online learning [97]. Voice numbers from 0 to 9 are converted into 78 frequency channels and 48 time steps, and the voltage pulse of a single frequency channel can be used as input as the gate voltage of a single FeFET. A number is determined in one device through the drain current obtained from there, according to the majority vote of the finally determined FeFET connected in parallel. In this study, several measures were proposed to increase detection accuracy. The time step used to make virtual nodes was adjusted, the voltage conversion and frequency channel selection methods were optimized, and drain, source, and substrate currents were measured and applied in detection to improve accuracy.
Chung et al. fabricated FeFETs using a germanium (Ge) channel to study the time response to the HZO gate stack, as shown in Figure 10a [98]. In Figure 10b,c, experiments demonstrate that a single pulse of fewer than 10 ns and a pulse train of 100 ps are suitable for attempting polarization transitions in FeFET. Time response is an indicator of the working speed of FeFET, which means that it is possible to operate in the GHz region when responding in an ultra-high-speed region of less than 10 ns. This group also presents a study that updates the optimal weights for improving the linearity and asymmetry of the channel conductance using the same Ge-FeFET [69]. The weight update applies potentiation and depression pulses to the gate electrode to enter a new conductance value through partial polarization of the ferroelectric. Online networks are required for the effective operation of linear and symmetric conductance. Therefore, if it is not optimized for the voltage or width of the pulse, as the number of pulses increases, the size of the decreasing conductance has nonlinear and asymmetric characteristics, and the network becomes inefficient. Through experiments, the pulse was optimized, and it was proved that the better the linearity, the higher the accuracy, and the lower the accuracy of the nonlinearity pulse. Using these devices, MNIST images were trained with these devices and achieved high accuracy of up to 88%. This means that the results confirm that optimization for the pulse has a great influence on updating the conductance.
Noh et al. conducted a study to combine β-Ga2O3 and HZO, which operate well at high temperatures available in rough environments (desert, space, etc.) [18]. β-Ga2O3 is a wide bandgap of 4.8~4.9 eV and has recently succeeded in melt-grown growth about low-priced large bulk substrates, receiving attention as a next-generation power semiconductor [99,100]. In this letter, FeFET was manufactured using HZO and β-Ga2O3 channels on sapphire substrates. The SS and Ion/Ioff characteristics of FeFET were excellent, and MW for use as a synaptic device was also confirmed. Meanwhile, as the number of pulses increases, both the nonlinear formation and the maximum conductance increase, resulting in a trade-off relationship. On-chip learning allowed excellent learning of 94% accuracy in a wide temperature band (20–200 °C) for the MNIST data set. Therefore, ferroelectric materials combined with β-Ga2O3 and HZO can be used to create devices that can overcome high temperatures.
So far, this paper has only considered HZO-based ferroelectric memory devices, but a recent study of P(VDF-TrFE) ferroelectric material-based 2D FeFET is worth reviewing from a structural and application perspective. To realize in-memory computing, Luo et al. implemented the ‘logic-in-memory’ system, which means digital operation, and the ‘neuromorphic computing’, which means analog operation, in a single three-terminal device, blurring the boundaries between the two operations [101]. With dual-ferroelectric-coupling effects and 2D transition metal dichalcogenide (TMD) channels, MoS2 with unipolar characteristics was used as the upper electrode, and MoTe2 with ambipolar characteristics was used as the lower electrode. The digital operation was performed using two ferroelectric layers located at the upper and lower ends. These layers induced four conductance states, and the ‘OR’ and ‘AND’ were implemented through the upper electrode while the ‘XNOR’ logic was implemented through the lower electrode, as shown in Figure 11a–c. In addition, one layer was set to a fixed polarization to implement analog operations that perform synaptic behavior like a general FeFET through long-term focus (LTD) measurement and MNIST simulation. This study is considered one of the low-power and high-efficiency in-memory computing hardware technologies that simultaneously conducts logic and synaptic operations when the switching between double-gate and single-gate methods was free.

3.2.2. FeRAM

FeRAM, with its 1T-1C structure, has been studied due to its high endurance, low voltage operation, and disturbance-free operation, but it is large footprint and destructive read operation suggest that it is better suited for use as, a memory array than in any neuromorphic application [44,102,103].
FeRAM was developed by Francois et al. as a 1T-1C array with a 16 kbit capacity [102]. The capacitor is less than 300 nm in diameter, and it has been confirmed that it has an operating speed of 30 ns, that data are in a 125 °C environment, that it has endurance characteristics of 1011 or more, and that it is compatible with the BEOL process. A 64 kbit array with a larger capacity was demonstrated by Okuno et al. [104]. A high operating speed of 14 ns, an endurance of 1011 or higher, and data retention characteristics of 10 years or more were also investigated. Their research attempted to amplify a voltage that changes in accordance with the difference in capacitance obtained through the comparison of the reference capacitor and the ferroelectric capacitor by the sense amplifier. Simulation and experimental results confirmed that the two memory states were distinguished. The dependence on the read voltage margin on the MFM capacitor size was calculated, and it was found that it was possible through a 40 nm process based on a 3D cylinder capacitor. While working on a low-capacity FeRAM array, a high-capacity FeRAM with 8 GB density was demonstrated by Sung et al. [105]. While the existing FeRAM operated by maximizing 2Pr by adjusting the capacitor plate voltage, the demonstrated FeRAM showed potential as a low-power, high-speed memory by using a low fixed capacitor plate voltage that widened the difference in work functions of the upper and lower electrodes. However, the system remained disadvantageous in terms of density, and additional improvements will be needed to improve the 2Pr and speed switching through asymmetric operating voltage, upper/lower electrode development, and HZO composition.

4. Conclusions

We described four types of ferroelectric-based memory devices, focusing on their operational methods, features, and applications. FTJ operates according to the TER whose resistance changes depending on the polarization direction of the ferroelectric. Fe-diodes operate by causing polarization inversion through Schottky barrier modulation at the interface between the metal electrode and the ferroelectric thin film. These two structures are two-terminal devices, so high integration that enables large-scale parallel computing can be implemented. In addition, their analog switching characteristics and uniformity are excellent. FTJs which have a linear I-V and Fe-diode generally have nonlinear I-V characteristics, but FTJs with a nonlinear I-V are also being studied. This is the nonlinear I-V characteristic of the two-terminal device that is advantageous for synaptic devices in neuromorphic applications and low-current devices in large-scale parallel computing with resistance-based crossbar arrays [77,78]. To improve mobility, SS, endurance, and retention characteristics, an IGZO layer or several oxide layers (such as TiO2 and HfOx) can be used as insertion layers [58,87,89]. FeFET induces a change in the current of a channel according to polarization switching, and FeRAM uses a ferroelectric material in a capacitor having a 1T-1C structure to perform a destructive operation. FeFET has low leakage current due to the wide bandgap of the HZO and thus shows advantageous high-speed and low-power characteristics, even when the associated device scale is small. Since they operate like MOSFET, researchers have focused on developing memory performance through a structural approach [91,92,93]. Especially, inducing a channel current change by gate has proved that learning and operation can be separated and have advantages in online learning [97]. FeRAM is being actively researched for use as a memory array, in light of its high endurance characteristics and compatibility with the BEOL process [102,104]. Finally, studies of low fixed plate voltages, have yielded encouraging findings for the development of low-power high-speed memory [105]. In summary, while research has only just begun on the application of memory devices using ferroelectric doped with Zr on Hf, the potential is clearly enormous. If each structure’s unique strengths and weaknesses continue to be improved upon, many applications, such as in-memory computing and neuromorphic computing, will be developed.

Author Contributions

Conceptualization, J.Y. and H.B.; resources, H.S., H.L. and S.L.; visualization, H.L. and S.K.; writing—original draft, J.Y.; writing—review and editing, K.H. and H.B.; supervision, K.H. and H.B.; All authors have read and agreed to the published version of the manuscript.

Funding

The article publishing fee was funded by the Basic Science Research Program through the NRF of Korea funded by the Ministry of Education (2022R1F1A1071914).

Data Availability Statement

No new data were created or analyzed in this work. Data sharing is not applicable to this article.

Acknowledgments

This work was supported in part by the Basic Science Research Program through the NRF of Korea funded by the Ministry of Education (2022R1F1A1071914), in part by the Nano·Material Technology Development Program through the NRF of Korea funded by the Ministry of Science, ICT and Future Planning (2009-0082580), in part by the IC Design Education Center (IDEC), in part by the National Research Council of Science & Technology (NST) grant by the Korea government (MSIT) (No. CAP22031-110), in part by “Research Base Construction Fund Support Program” funded by Jeonbuk National University in 2022, and in part by Basic Science Research Program funded by the Ministry of Education (2022R1I1A307258211).

Conflicts of Interest

The authors declare no conflict of interest.

References

  1. Song, C.-M.; Kwon, H.-J. Ferroelectrics Based on HfO2 Film. Electronics 2021, 10, 2759. [Google Scholar] [CrossRef]
  2. Cappy, A. Neuro-Inspired Information Processing; John Wiley & Sons: Hoboken, NJ, USA, 2020. [Google Scholar]
  3. Keshavarzi, A.; Ni, K.; Van Den Hoek, W.; Datta, S.; Raychowdhury, A. FerroElectronics for Edge Intelligence. IEEE Micro 2020, 40, 33–48. [Google Scholar] [CrossRef]
  4. Wang, Z.; Wu, H.; Burr, G.W.; Hwang, C.S.; Wang, K.L.; Xia, Q.; Yang, J.J. Resistive switching materials for information processing. Nat. Rev. Mater. 2020, 5, 173–195. [Google Scholar] [CrossRef]
  5. Dai, S.; Zhao, Y.; Wang, Y.; Zhang, J.; Fang, L.; Jin, S.; Shao, Y.; Huang, J. Recent Advances in Transistor-Based Artificial Synapses. Adv. Funct. Mater. 2019, 29, 1903700. [Google Scholar] [CrossRef]
  6. Sun, B.; Guo, T.; Zhou, G.; Ranjan, S.; Jiao, Y.; Wei, L.; Zhou, Y.N.; Wu, Y.A. Synaptic devices based neuromorphic computing applications in artificial intelligence. Mater. Today Phys. 2021, 18, 100393. [Google Scholar] [CrossRef]
  7. Han, J.-K.; Yun, S.-Y.; Lee, S.-W.; Yu, J.-M.; Choi, Y.-K. A Review of Artificial Spiking Neuron Devices for Neural Processing and Sensing. Adv. Funct. Mater. 2022, 32, 2204102. [Google Scholar] [CrossRef]
  8. Banerjee, W. Challenges and Applications of Emerging Nonvolatile Memory Devices. Electronics 2020, 9, 1029. [Google Scholar] [CrossRef]
  9. Sebastian, A.; Le Gallo, M.; Khaddam-Aljameh, R.; Eleftheriou, E. Memory devices and applications for in-memory computing. Nat. Nanotechnol. 2020, 15, 529–544. [Google Scholar] [CrossRef]
  10. Jouppi, N.P.; Young, C.; Patil, N.; Patterson, D.; Agrawal, G.; Bajwa, R.; Bates, S.; Bhatia, S.; Boden, N.; Borchers, A.; et al. In-Datacenter Performance Analysis of a Tensor Processing Unit. In Proceedings of the 44th Annual International Symposium on Computer Architecture, New York, NY, USA, 24–28 June 2017. [Google Scholar]
  11. Sze, V.; Chen, Y.-H.; Yang, T.-J.; Emer, J.S. Efficient Processing of Deep Neural Networks: A Tutorial and Survey. Proc. IEEE 2017, 105, 2295–2329. [Google Scholar] [CrossRef]
  12. Yu, J.-M.; Lee, C.; Kim, D.-J.; Park, H.; Han, J.-K.; Hur, J.; Kim, J.-K.; Kim, M.-S.; Seo, M.; Im, S.G.; et al. All-Solid-State Ion Synaptic Transistor for Wafer-Scale Integration with Electrolyte of a Nanoscale Thickness. Adv. Funct. Mater. 2021, 31, 2010971. [Google Scholar] [CrossRef]
  13. Wang, W.; Gao, S.; Li, Y.; Yue, W.; Kan, H.; Zhang, C.; Lou, Z.; Wang, L.; Shen, G. Artificial Optoelectronic Synapses Based on TiNxO2–x/MoS2 Heterojunction for Neuromorphic Computing and Visual System. Adv. Funct. Mater. 2021, 31, 2101201. [Google Scholar] [CrossRef]
  14. Ielmini, D.; Wong, H.-S.P. In-memory computing with resistive switching devices. Nat. Electron. 2018, 1, 333–343. [Google Scholar] [CrossRef]
  15. Raoux, S.; Wełnic, W.; Ielmini, D. Phase Change Materials and Their Application to Nonvolatile Memories. Chem. Rev. 2010, 110, 240–267. [Google Scholar] [CrossRef] [PubMed]
  16. Kent, A.D.; Worledge, D.C. A new spin on magnetic memories. Nat. Nanotechnol. 2015, 10, 187–191. [Google Scholar] [CrossRef] [PubMed]
  17. Jan, A.; Rembert, T.; Taper, S.; Symonowicz, J.; Strkalj, N.; Moon, T.; Lee, Y.S.; Bae, H.; Lee, H.J.; Choe, D.-H.; et al. In Operando Optical Tracking of Oxygen Vacancy Migration and Phase Change in few Nanometers Ferroelectric HZO Memories. Adv. Funct. Mater. 2023, 2214970. [Google Scholar] [CrossRef]
  18. Noh, J.; Bae, H.; Li, J.; Luo, Y.; Qu, Y.; Park, T.J.; Si, M.; Chen, X.; Charnas, A.R.; Chung, W.; et al. First Experimental Demonstration of Robust HZO/β-Ga2O3 Ferroelectric Field-Effect Transistors as Synaptic Devices for Artificial Intelligence Applications in a High-Temperature Environment. IEEE Trans. Electron Devices 2021, 68, 2515–2521. [Google Scholar] [CrossRef]
  19. Choe, D.-H.; Kim, S.; Moon, T.; Jo, S.; Bae, H.; Nam, S.-G.; Lee, Y.S.; Heo, J. Unexpectedly low barrier of ferroelectric switching in HfO2 via topological domain walls. Mater. Today 2021, 50, 8–15. [Google Scholar] [CrossRef]
  20. Si, M.; Luo, Y.; Chung, W.; Bae, H.; Zheng, D.; Li, J.; Qin, J.; Qiu, G.; Yu, S.; Ye, P. A novel scalable energy-efficient synaptic device: Crossbar ferroelectric semiconductor junction. In Proceedings of the 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 7–11 December 2019. [Google Scholar]
  21. Kang, S.; Jang, W.-S.; Morozovska, A.N.; Kwon, O.; Jin, Y.; Kim, Y.-H.; Bae, H.; Wang, C.; Yang, S.-H.; Belianinov, A. Highly enhanced ferroelectricity in HfO2-based ferroelectric thin film by light ion bombardment. Science 2022, 376, 731–738. [Google Scholar] [CrossRef]
  22. Seo, M.; Kang, M.-H.; Jeon, S.-B.; Bae, H.; Hur, J.; Jang, B.C.; Yun, S.; Cho, S.; Kim, W.-K.; Kim, M.-S.; et al. First Demonstration of a Logic-Process Compatible Junctionless Ferroelectric FinFET Synapse for Neuromorphic Applications. IEEE Electron Device Lett. 2018, 39, 1445–1448. [Google Scholar] [CrossRef]
  23. Martin, L.W.; Rappe, A.M. Thin-film ferroelectric materials and their applications. Nat. Rev. Mater. 2016, 2, 16087. [Google Scholar] [CrossRef]
  24. Schroeder, U.; Park, M.H.; Mikolajick, T.; Hwang, C.S. The fundamentals and applications of ferroelectric HfO2. Nat. Rev. Mater. 2022, 7, 653–669. [Google Scholar] [CrossRef]
  25. Mulaosmanovic, H.; Breyer, E.T.; Dünkel, S.; Beyer, S.; Mikolajick, T.; Slesazeck, S. Ferroelectric field-effect transistors based on HfO2: A review. Nanotechnology 2021, 32, 502002. [Google Scholar] [CrossRef]
  26. Qi, L.; Ruan, S.; Zeng, Y.-J. Review on Recent Developments in 2D Ferroelectrics: Theories and Applications. Adv. Mater. 2021, 33, e2005098. [Google Scholar] [CrossRef]
  27. Kim, S.J.; Mohan, J.; Summerfelt, S.R.; Kim, J. Ferroelectric Hf0.5Zr0.5O2 Thin Films: A Review of Recent Advances. JOM 2018, 71, 246–255. [Google Scholar] [CrossRef]
  28. Kim, J.Y.; Choi, M.-J.; Jang, H.W. Ferroelectric field effect transistors: Progress and perspective. APL Mater. 2021, 9, 021102. [Google Scholar] [CrossRef]
  29. Park, H.W.; Lee, J.-G.; Hwang, C.S. Review of ferroelectric field-effect transistors for three-dimensional storage applications. Nano Sel. 2021, 2, 1187–1207. [Google Scholar] [CrossRef]
  30. Park, M.H.; Lee, Y.H.; Mikolajick, T.; Schroeder, U.; Hwang, C.S. Review and perspective on ferroelectric HfO2-based thin films for memory applications. Mrs Commun. 2018, 8, 795–808. [Google Scholar] [CrossRef]
  31. Böscke, T.S.; Müller, J.; Bräuhaus, D.; Schröder, U.; Böttger, U. Ferroelectricity in hafnium oxide thin films. Appl. Phys. Lett. 2011, 99, 102903. [Google Scholar] [CrossRef]
  32. Park, M.H.; Lee, Y.H.; Kim, H.J.; Kim, Y.J.; Moon, T.; Kim, K.D.; Muller, J.; Kersch, A.; Schroeder, U.; Mikolajick, T.; et al. Ferroelectricity and Antiferroelectricity of Doped Thin HfO2-Based Films. Adv. Mater. 2015, 27, 1811–1831. [Google Scholar] [CrossRef]
  33. Schroeder, U.; Yurchuk, E.; Müller, J.; Martin, D.; Schenk, T.; Polakowski, P.; Adelmann, C.; Popovici, M.I.; Kalinin, S.V.; Mikolajick, T. Impact of different dopants on the switching properties of ferroelectric hafniumoxide. Jpn. J. Appl. Phys. 2014, 53, 08LE02. [Google Scholar] [CrossRef]
  34. Zhou, D.; Müller, J.; Xu, J.; Knebel, S.; Bräuhaus, D.; Schröder, U. Insights into electrical characteristics of silicon doped hafnium oxide ferroelectric thin films. Appl. Phys. Lett. 2012, 100, 082905. [Google Scholar] [CrossRef]
  35. Park, M.H.; Kim, H.J.; Kim, Y.J.; Lee, W.; Moon, T.; Kim, K.D.; Hwang, C.S. Study on the degradation mechanism of the ferroelectric properties of thin Hf0.5Zr0.5O2 films on TiN and Ir electrodes. Appl. Phys. Lett. 2014, 105, 072902. [Google Scholar] [CrossRef]
  36. Kim, H.J.; Park, M.H.; Kim, Y.J.; Lee, Y.H.; Jeon, W.; Gwon, T.; Moon, T.; Kim, K.D.; Hwang, C.S. Grain size engineering for ferroelectric Hf0.5Zr0.5O2 films by an insertion of Al2O3 interlayer. Appl. Phys. Lett. 2014, 105, 192903. [Google Scholar] [CrossRef]
  37. Müller, J.; Schröder, U.; Böscke, T.S.; Müller, I.; Böttger, U.; Wilde, L.; Sundqvist, J.; Lemberger, M.; Kücher, P.; Mikolajick, T.; et al. Ferroelectricity in yttrium-doped hafnium oxide. J. Appl. Phys. 2011, 110, 114113. [Google Scholar] [CrossRef]
  38. Polakowski, P.; Riedel, S.; Weinreich, W.; Rudolf, M.; Sundqvist, J.; Seidel, K.; Muller, J. Ferroelectric deep trench capacitors based on Al:HfO2 for 3D nonvolatile memory applications. In Proceedings of the 2014 IEEE 6th International Memory Workshop (IMW), Taipei, Taiwan, 18–21 May 2014. [Google Scholar]
  39. Mueller, S.; Adelmann, C.; Singh, A.; Van Elshocht, S.; Schroeder, U.; Mikolajick, T. Ferroelectricity in Gd-Doped HfO2 Thin Films. ECS J. Solid State Sci. Technol. 2012, 1, N123–N126. [Google Scholar] [CrossRef]
  40. Schenk, T.; Schroeder, U.; Pesic, M.; Popovici, M.; Pershin, Y.V.; Mikolajick, T. Electric Field Cycling Behavior of Ferroelectric Hafnium Oxide. ACS Appl. Mater. Interfaces 2014, 6, 19744–19751. [Google Scholar] [CrossRef]
  41. Müller, J.; Böscke, T.; Müller, S.; Yurchuk, E.; Polakowski, P.; Paul, J.; Martin, D.; Schenk, T.; Khullar, K.; Kersch, A.; et al. Ferroelectric Hafnium Oxide: A CMOS-compatible and highly scalable approach to future ferroelectric memories. In Proceedings of the 2013 IEEE International Electron Devices Meeting, Washington, DC, USA, 9–11 December 2013. [Google Scholar]
  42. Muller, J.; Boscke, T.S.; Schroder, U.; Mueller, S.; Brauhaus, D.; Bottger, U.; Frey, L.; Mikolajick, T. Ferroelectricity in Simple Binary ZrO2 and HfO2. Nano Lett. 2012, 12, 4318–4323. [Google Scholar] [CrossRef]
  43. Jo, S.; Lee, H.; Choe, D.-H.; Kim, J.-H.; Lee, Y.S.; Kwon, O.; Nam, S.; Park, Y.; Kim, K.; Chae, B.G.; et al. Negative differential capacitance in ultrathin ferroelectric hafnia. Nat. Electron. 2023. [Google Scholar] [CrossRef]
  44. Park, J.Y.; Choe, D.-H.; Lee, D.H.; Yu, G.T.; Yang, K.; Kim, S.H.; Park, G.H.; Nam, S.-G.; Lee, H.J.; Jo, S.; et al. Revival of Ferroelectric Memories Based on Emerging Fluorite-Structured Ferroelectrics. Adv. Mater. 2022, e2204904. [Google Scholar] [CrossRef]
  45. Mikolajick, T.; Slesazeck, S.; Mulaosmanovic, H.; Park, M.H.; Fichtner, S.; Lomenzo, P.D.; Hoffmann, M.; Schroeder, U. Next generation ferroelectric materials for semiconductor process integration and their applications. J. Appl. Phys. 2021, 129, 100901. [Google Scholar] [CrossRef]
  46. Max, B.; Hoffmann, M.; Slesazeck, S.; Mikolajick, T. Ferroelectric Tunnel Junctions based on Ferroelectric-Dielectric Hf0.5Zr0.5O2/A12O3 Capacitor Stacks. In Proceedings of the 2018 48th European Solid-State Device Research Conference (ESSDERC), Dresden, Germany, 3–6 September 2018. [Google Scholar]
  47. Mikolajick, T.; Schroeder, U.; Slesazeck, S. The Past, the Present, and the Future of Ferroelectric Memories. IEEE Trans. Electron Devices 2020, 67, 1434–1443. [Google Scholar] [CrossRef]
  48. Fujii, S.; Kamimuta, Y.; Ino, T.; Nakasaki, Y.; Takaishi, R.; Saitoh, M. First demonstration and performance improvement of ferroelectric HfO2-based resistive switch with low operation current and intrinsic diode property. In Proceedings of the 2016 IEEE Symposium on VLSI Technology, Honolulu, HI, USA, 14–16 June 2016. [Google Scholar]
  49. Hwang, J.; Goh, Y.; Jeon, S. Effect of Insertion of Dielectric Layer on the Performance of Hafnia Ferroelectric Devices. IEEE Trans. Electron Devices 2021, 68, 841–845. [Google Scholar] [CrossRef]
  50. Blom, P.W.M.; Wolf, R.M.; Cillessen, J.F.M.; Krijn, M.P.C.M. Ferroelectric Schottky Diode. Phys. Rev. Lett. 1994, 73, 2107–2110. [Google Scholar] [CrossRef]
  51. Hsiang, K.-Y.; Liao, C.-Y.; Wang, J.-F.; Lou, Z.-F.; Lin, C.-Y.; Chiang, S.-H.; Liu, C.-W.; Hou, T.-H.; Lee, M.-H. Unipolar Parity of Ferroelectric-Antiferroelectric Characterized by Junction Current in Crystalline Phase Hf1−xZrxO2 Diodes. Nanomaterials 2021, 11, 2685. [Google Scholar] [CrossRef]
  52. Luo, Q.; Cheng, Y.; Yang, J.; Cao, R.; Ma, H.; Yang, Y.; Huang, R.; Wei, W.; Zheng, Y.; Gong, T.; et al. A highly CMOS compatible hafnia-based ferroelectric diode. Nat. Commun. 2020, 11, 1391. [Google Scholar] [CrossRef]
  53. Chen, A. A review of emerging non-volatile memory (NVM) technologies and applications. Solid-State Electron. 2016, 125, 25–38. [Google Scholar] [CrossRef]
  54. Hoffman, J.; Pan, X.; Reiner, J.W.; Walker, F.J.; Han, J.P.; Ahn, C.H.; Ma, T.P. Ferroelectric Field Effect Transistors for Memory Applications. Adv. Mater. 2010, 22, 2957–2961. [Google Scholar] [CrossRef]
  55. Mo, F.; Tagawa, Y.; Jin, C.; Ahn, M.; Saraya, T.; Hiramoto, T.; Kobayashi, M. Experimental Demonstration of Ferroelectric HfO2 FET with Ultrathin-body IGZO for High-Density and Low-Power Memory Application. In Proceedings of the 2019 Symposium on VLSI Technology, Kyoto, Japan, 9–14 June 2019. [Google Scholar]
  56. Mo, F.; Tagawa, Y.; Jin, C.; Ahn, M.; Saraya, T.; Hiramoto, T.; Kobayashi, M. Low-Voltage Operating Ferroelectric FET with Ultrathin IGZO Channel for High-Density Memory Application. IEEE J. Electron Devices Soc. 2020, 8, 717–723. [Google Scholar] [CrossRef]
  57. Hoffmann, M.; Tan, A.J.; Shanker, N.; Liao, Y.-H.; Wang, L.-C.; Bae, J.-H.; Hu, C.; Salahuddin, S. Fast Read-After-Write and Depolarization Fields in High Endurance n-Type Ferroelectric FETs. IEEE Electron Device Lett. 2022, 43, 717–720. [Google Scholar] [CrossRef]
  58. Gaddam, V.; Das, D.; Jeon, S. Insertion of HfO2 Seed/Dielectric Layer to the Ferroelectric HZO Films for Heightened Remanent Polarization in MFM Capacitors. IEEE Trans. Electron Devices 2020, 67, 745–750. [Google Scholar] [CrossRef]
  59. Okuno, J.; Kunihiro, T.; Konishi, K.; Materano, M.; Ali, T.; Kuehnel, K.; Seidel, K.; Mikolajick, T.; Schroeder, U.; Tsukamoto, M.; et al. 1T1C FeRAM Memory Array Based on Ferroelectric HZO With Capacitor Under Bitline. IEEE J. Electron Devices Soc. 2022, 10, 29–34. [Google Scholar] [CrossRef]
  60. Breyer, E.T.; Mulaosmanovic, H.; Mikolajick, T.; Slesazeck, S. Reconfigurable NAND/NOR logic gates in 28 nm HKMG and 22 nm FD-SOI FeFET technology. In Proceedings of the 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2–6 December 2017. [Google Scholar]
  61. Breyer, E.T.; Mulaosmanovic, H.; Mikolajick, T.; Slesazeck, S. Perspective on ferroelectric, hafnium oxide based transistors for digital beyond von-Neumann computing. Appl. Phys. Lett. 2021, 118, 050501. [Google Scholar] [CrossRef]
  62. Berdan, R.; Marukame, T.; Ota, K.; Yamaguchi, M.; Saitoh, M.; Fujii, S.; Deguchi, J.; Nishi, Y. Low-power linear computation using nonlinear ferroelectric tunnel junction memristors. Nat. Electron. 2020, 3, 259–266. [Google Scholar] [CrossRef]
  63. Jerry, M.; Chen, P.-Y.; Zhang, J.; Sharma, P.; Ni, K.; Yu, S.; Datta, S. Ferroelectric FET Analog Synapse for Acceleration of Deep Neural Network Training. In Proceedings of the 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2–6 December 2017. [Google Scholar]
  64. Wang, P.; Yu, S. Ferroelectric devices and circuits for neuro-inspired computing. MRS Commun. 2020, 10, 538–548. [Google Scholar] [CrossRef]
  65. Mulaosmanovic, H.; Ocker, J.; Müller, S.; Noack, M.; Müller, J.; Polakowski, P.; Mikolajick, T.; Slesazeck, S. Novel ferroelectric FET based synapse for neuromorphic systems. In Proceedings of the 2017 Symposium on VLSI Technology, Kyoto, Japan, 5–8 June 2017. [Google Scholar]
  66. Han, J.-K.; Yun, S.-Y.; Yu, J.-M.; Jeon, S.-B.; Choi, Y.-K. Artificial Multisensory Neuron with a Single Transistor for Multimodal Perception through Hybrid Visual and Thermal Sensing. ACS Appl. Mater. Interfaces 2023, 15, 5449–5455. [Google Scholar] [CrossRef]
  67. Lee, D.H.; Park, G.H.; Kim, S.H.; Park, J.Y.; Yang, K.; Slesazeck, S.; Mikolajick, T.; Park, M.H. Neuromorphic devices based on fluorite-structured ferroelectrics. InfoMat 2022, 4, e12380. [Google Scholar] [CrossRef]
  68. Fan, Z.; Chen, J.; Wang, J. Ferroelectric HfO2-based materials for next-generation ferroelectric memories. J. Adv. Dielectr. 2016, 6, 1630003. [Google Scholar] [CrossRef]
  69. Chung, W.; Si, M.; Ye, P.D. First Demonstration of Ge Ferroelectric Nanowire FET as Synaptic Device for Online Learning in Neural Network with High Number of Conductance State and Gmax/Gmin. In Proceedings of the 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 1–5 December 2018. [Google Scholar]
  70. Si, M.; Ye, P.D. The Critical Role of Charge Balance on the Memory Characteristics of Ferroelectric Field-Effect Transistors. IEEE Trans. Electron Devices 2021, 68, 5108–5113. [Google Scholar] [CrossRef]
  71. Saha, A.K.; Si, M.; Ni, K.; Datta, S.; Ye, P.D.; Gupta, S. Ferroelectric Thickness Dependent Domain Interactions in FEFETs for Memory and Logic: A phase-Field Model based Analysis. In Proceedings of the 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 12–18 December 2020. [Google Scholar]
  72. Lyu, X.; Si, M.; Sun, X.; Capano, M.A.; Wang, H.; Ye, P.D. Ferroelectric and Anti-Ferroelectric Hafnium Zirconium Oxide: Scaling Limit, Switching Speed and Record High Polarization Density. In Proceedings of the 2019 Symposium on VLSI Technology, Kyoto, Japan, 9–14 June 2019. [Google Scholar]
  73. Saitoh, M.; Ichihara, R.; Yamaguchi, M.; Suzuki, K.; Takano, K.; Akari, K.; Takahashi, K.; Kamiya, Y.; Matsuo, K.; Kamimuta, Y.; et al. HfO2-based FeFET and FTJ for Ferroelectric-Memory Centric 3D LSI towards Low-Power and High-Density Storage and AI Applications. In Proceedings of the 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 12–18 December 2020. [Google Scholar]
  74. Marinella, M.J.; Agarwal, S.; Hsia, A.; Richter, I.; Jacobs-Gedrim, R.; Niroula, J.; Plimpton, S.J.; Ipek, E.; James, C.D. Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator. IEEE J. Emerg. Sel. Top. Circuits Syst. 2018, 8, 86–101. [Google Scholar] [CrossRef]
  75. Yang, S.-T.; Li, X.-Y.; Yu, T.-L.; Wang, J.; Fang, H.; Nie, F.; He, B.; Zhao, L.; Lü, W.-M.; Yan, S.-S.; et al. High-Performance Neuromorphic Computing Based on Ferroelectric Synapses with Excellent Conductance Linearity and Symmetry. Adv. Funct. Mater. 2022, 32, 2202366. [Google Scholar] [CrossRef]
  76. Yu, S.; Chen, P.-Y. Emerging Memory Technologies: Recent Trends and Prospects. IEEE Solid-State Circuits Mag. 2016, 8, 43–56. [Google Scholar] [CrossRef]
  77. Yang, R. In-memory computing with ferroelectrics. Nat. Electron. 2020, 3, 237–238. [Google Scholar] [CrossRef]
  78. Fuller, E.J.; Keene, S.T.; Melianas, A.; Wang, Z.; Agarwal, S.; Li, Y.; Tuchman, Y.; James, C.D.; Marinella, M.J.; Yang, J.J. Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing. Science 2019, 364, 570–574. [Google Scholar] [CrossRef]
  79. Yu, J.; Li, Y.; Sun, W.; Zhang, W.; Gao, Z.; Dong, D.; Yu, Z.; Zhao, Y.; Lai, J.; Ding, Q. Energy efficient and robust reservoir computing system using ultrathin (3.5 nm) ferroelectric tunneling junctions for temporal data learning. In Proceedings of the 2021 Symposium on VLSI Technology, Kyoto, Japan, 13–19 June 2021. [Google Scholar]
  80. Chen, L.; Wang, T.-Y.; Dai, Y.-W.; Cha, M.-Y.; Zhu, H.; Sun, Q.-Q.; Ding, S.-J.; Zhou, P.; Chua, L.; Zhang, D.W. Ultra-low power Hf0.5Zr0.5O2 based ferroelectric tunnel junction synapses for hardware neural network applications. Nanoscale 2018, 10, 15826–15833. [Google Scholar] [CrossRef]
  81. Ota, K.; Yamaguchi, M.; Berdan, R.; Marukame, T.; Nishi, Y.; Matsuo, K.; Takahashi, K.; Kamiya, Y.; Miyano, S.; Deguchi, J.; et al. Performance Maximization of In-Memory Reinforcement Learning with Variability-Controlled Hf1−xZrxO2 Ferroelectric Tunnel Junctions. In Proceedings of the 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 7–11 December 2019. [Google Scholar]
  82. Berdan, R.; Marukame, T.; Kabuyanagi, S.; Ota, K.; Saitoh, M.; Fujii, S.; Deguchi, J.; Nishi, Y. In-memory Reinforcement Learning with Moderately-Stochastic Conductance Switching of Ferroelectric Tunnel Junctions. In Proceedings of the 2019 Symposium on VLSI Technology, Kyoto, Japan, 9–14 June 2019. [Google Scholar]
  83. Luo, Y.-C.; Hur, J.; Yu, S. Ferroelectric Tunnel Junction Based Crossbar Array Design for Neuro-Inspired Computing. IEEE Trans. Nanotechnol. 2021, 20, 243–247. [Google Scholar] [CrossRef]
  84. Goh, Y.; Hwang, J.; Kim, M.; Lee, Y.; Jung, M.; Jeon, S. Selector-less Ferroelectric Tunnel Junctions by Stress Engineering and an Imprinting Effect for High-Density Cross-Point Synapse Arrays. ACS Appl. Mater. Interfaces 2021, 13, 59422–59430. [Google Scholar] [CrossRef]
  85. Kim, S.; Lee, K.; Oh, M.-H.; Lee, J.-H.; Park, B.-G.; Kwon, D. Physical Unclonable Functions Using Ferroelectric Tunnel Junctions. IEEE Electron Device Lett. 2021, 42, 816–819. [Google Scholar] [CrossRef]
  86. Lim, S.; Goh, Y.; Lee, Y.K.; Ko, D.H.; Hwang, J.; Kim, M.; Jeong, Y.; Shin, H.; Jeon, S.; Jung, S.-O. A Highly Integrated Crosspoint Array Using Self-rectifying FTJ for Dual-mode Operations: CAM and PUF. In Proceedings of the ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), Milan, Italy, 19–22 September 2022. [Google Scholar]
  87. Bae, H.; Moon, T.; Nam, S.G.; Lee, K.-H.; Kim, S.; Hong, S.; Choe, D.-H.; Jo, S.; Lee, Y.; Heo, J. Ferroelectric Diodes with Sub-ns and Sub-fJ Switching and Its Programmable Network for Logic-in-Memory Applications. In Proceedings of the 2021 Symposium on VLSI Technology, Kyoto, Japan, 13–19 June 2021. [Google Scholar]
  88. Zhang, Z.; Zhang, F.; Zhang, Y.; Xu, G.; Wu, Z.; Zhang, Q.; Li, Y.; Yin, H.; Luo, J.; Wang, W.; et al. Ultradense One-Memristor Ternary-Content-Addressable Memory Based on Ferroelectric Diodes. IEEE Electron Device Lett. 2023, 44, 64–67. [Google Scholar] [CrossRef]
  89. Kao, R.-W.; Peng, H.-K.; Chen, K.-Y.; Wu, Y.-H. HfZrOx-Based Switchable Diode for Logic-in-Memory Applications. IEEE Trans. Electron Devices 2021, 68, 545–549. [Google Scholar] [CrossRef]
  90. Ma, T.P.; Han, J.-P. Why is Nonvolatile Ferroelectric Memory Field-Effect Transistor Still Elusive? IEEE Electron Device Lett. 2002, 23, 386–388. [Google Scholar] [CrossRef]
  91. Bae, H.; Nam, S.G.; Moon, T.; Lee, Y.; Jo, S.; Choe, D.-H.; Kim, S.; Lee, K.-H.; Heo, J. Sub-ns Polarization Switching in 25 nm FE FinFET toward Post CPU and Spatial-Energetic Mapping of Traps for Enhanced Endurance. In Proceedings of the 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 12–18 December 2020. [Google Scholar]
  92. Liao, C.-Y.; Hsiang, K.-Y.; Lou, Z.-F.; Tseng, H.-C.; Lin, C.-Y.; Li, Z.-X.; Hsieh, F.-C.; Wang, C.-C.; Chang, F.-S.; Ray, W.-C.; et al. Endurance > 1011 Cycling of 3D GAA Nanosheet Ferroelectric FET with Stacked HfZrO2 to Homogenize Corner Field Toward Mitigate Dead Zone for High-Density eNVM. In Proceedings of the 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, 12–17 June 2022. [Google Scholar]
  93. Chen, C.-K.; Fang, Z.; Hooda, S.; Lal, M.; Chand, U.; Xu, Z.; Pan, J.; Tsai, S.-H.; Zamburg, E.; Thean, A.V.-Y. First Demonstration of Ultra-low Dit Top-Gated Ferroelectric Oxide-Semiconductor Memtransistor with Record Performance by Channel Defect Self-Compensation Effect for BEOL-Compatible Non-Volatile Logic Switch. In Proceedings of the 2022 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 3–7 December 2022. [Google Scholar]
  94. Yu, S. Neuro-Inspired Computing With Emerging Nonvolatile Memorys. Proc. IEEE 2018, 106, 260–285. [Google Scholar] [CrossRef]
  95. Jeong, D.S.; Hwang, C.S. Nonvolatile Memory Materials for Neuromorphic Intelligent Machines. Adv. Mater. 2018, 30, e1704729. [Google Scholar] [CrossRef]
  96. Oh, S.; Kim, T.; Kwak, M.; Song, J.; Woo, J.; Jeon, S.; Yoo, I.K.; Hwang, H. HfZrOx-Based Ferroelectric Synapse Device with 32 Levels of Conductance States for Neuromorphic Applications. IEEE Electron Device Lett. 2017, 38, 732–735. [Google Scholar] [CrossRef]
  97. Nako, E.; Toprasertpong, K.; Nakane, R.; Takenaka, M.; Takagi, S. Experimental demonstration of novel scheme of HZO/Si FeFET reservoir computing with parallel data processing for speech recognition. In Proceedings of the 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, 12–17 June 2022. [Google Scholar]
  98. Chung, W.; Si, M.; Shrestha, P.R.; Campbell, J.P.; Cheung, K.P.; Peide, D.Y. First Direct Experimental Studies of Hf0.5Zr0.5O2 Ferroelectric Polarization Switching Down to 100-picosecond in Sub-60mV/dec Germanium Ferroelectric Nanowire FETs. In Proceedings of the 2018 IEEE Symposium on VLSI Technology, Honolulu, HI, USA, 18–22 June 2018. [Google Scholar]
  99. Bae, H.; Park, T.J.; Noh, J.; Chung, W.; Si, M.; Ramanathan, S.; Peide, D.Y. First demonstration of robust tri-gate β-Ga2O3 nano-membrane field-effect transistors. Nanotechnology 2021, 33, 125201. [Google Scholar] [CrossRef] [PubMed]
  100. Noh, J.; Alajlouni, S.; Tadjer, M.J.; Culbertson, J.C.; Bae, H.; Si, M.; Zhou, H.; Bermel, P.A.; Shakouri, A.; Peide, D.Y. High Performance β-Ga2O3 Nano-Membrane Field Effect Transistors on a High Thermal Conductivity Diamond Substrate. IEEE J. Electron Devices Soc. 2019, 7, 914–918. [Google Scholar] [CrossRef]
  101. Luo, Z.-D.; Zhang, S.; Liu, Y.; Zhang, D.; Gan, X.; Seidel, J.; Liu, Y.; Han, G.; Alexe, M.; Hao, Y. Dual-Ferroelectric-Coupling-Engineered Two-Dimensional Transistors for Multifunctional In-Memory Computing. ACS Nano 2022, 16, 3362–3372. [Google Scholar] [CrossRef]
  102. Francois, T.; Grenouillet, L.; Coignus, J.; Blaise, P.; Carabasse, C.; Vaxelaire, N.; Magis, T.; Aussenac, F.; Loup, V.; Pellissier, C.; et al. Demonstration of BEOL-compatible ferroelectric Hf0.5Zr0.5O2 scaled FeRAM co-integrated with 130nm CMOS for embedded NVM applications. In Proceedings of the 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 7–11 December 2019. [Google Scholar]
  103. Mikolajick, T.; Park, M.H.; Begon-Lours, L.; Slesazeck, S. From Ferroelectric Material Optimization to Neuromorphic Devices. Adv. Mater. 2022, e2206042. [Google Scholar] [CrossRef]
  104. Okuno, J.; Kunihiro, T.; Konishi, K.; Maemura, H.; Shuto, Y.; Sugaya, F.; Materano, M.; Ali, T.; Kuehnel, K.; Seidel, K. SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf0. 5Zr0. 5O2. In Proceedings of the 2020 IEEE Symposium on VLSI Technology, Honolulu, HI, USA, 16–19 June 2020. [Google Scholar]
  105. Sung, M.; Rho, K.; Kim, J.; Cheon, J.; Choi, K.; Kim, D.; Em, H.; Park, G.; Woo, J.; Lee, Y.; et al. Low Voltage and High Speed 1Xnm 1T1C FE-RAM with Ultra-Thin 5nm HZO. In Proceedings of the 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 11–16 December 2021. [Google Scholar]
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Figure 1. Conduction band schematic by polarization during FTJ operation of an MFM and MIFM structure: (a) Asymmetric screening length x from other effective tunneling barrier height Φ: LRS (On); (b) HRS (Off); (c) direct tunneling through tunneling barriers; (d) Fowler-Nordheim tunneling that passes through only part of the tunneling barrier [47].
Figure 1. Conduction band schematic by polarization during FTJ operation of an MFM and MIFM structure: (a) Asymmetric screening length x from other effective tunneling barrier height Φ: LRS (On); (b) HRS (Off); (c) direct tunneling through tunneling barriers; (d) Fowler-Nordheim tunneling that passes through only part of the tunneling barrier [47].
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Figure 2. (a) Endurance characteristics and (b) retention characteristics of FTJ devices with a TiO2 layer inserted in the HZO film with permission from Ref. [49], 2021, IEEE.
Figure 2. (a) Endurance characteristics and (b) retention characteristics of FTJ devices with a TiO2 layer inserted in the HZO film with permission from Ref. [49], 2021, IEEE.
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Figure 3. (a) Molecular structure of Hf0.5Zr0.5O2 and structural mimetic diagram of a Fe-diode; (b) Energy band diagram showing Schottky to ohmic internal contact in a TiN/HZO/TiN structure modulated from polarization; (c) Nonlinear I-V curve for two polarizations of ferroelectric with permission from Ref. [52], 2020, Springer Nature.
Figure 3. (a) Molecular structure of Hf0.5Zr0.5O2 and structural mimetic diagram of a Fe-diode; (b) Energy band diagram showing Schottky to ohmic internal contact in a TiN/HZO/TiN structure modulated from polarization; (c) Nonlinear I-V curve for two polarizations of ferroelectric with permission from Ref. [52], 2020, Springer Nature.
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Figure 4. (a) Schematic of HfO2 using bottom insert layer in an HZO MFM structure; (b) remanent polarization of the thickness of the HfO2 bottom insert layer; (c) endurance and (d) retention characteristics with no HfO2 insert layer or location with permission from Ref. [58], 2020, IEEE.
Figure 4. (a) Schematic of HfO2 using bottom insert layer in an HZO MFM structure; (b) remanent polarization of the thickness of the HfO2 bottom insert layer; (c) endurance and (d) retention characteristics with no HfO2 insert layer or location with permission from Ref. [58], 2020, IEEE.
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Figure 5. (a). Section cut of 3D vertical ferroelectric HZO−based FTJ array structure. (b) Diagram of 1/2 bias training of FTJ array structure. (c) The curve of the change in conductance according to the pulse number, the difference in conductance between the selected-synapse and the half-selected synapse effectively changed. (d) The test set trained 50 letter patterns at 20 epochs, and these characters recorded high accuracy of more than 96%. With permission from Ref. [80], 2018, RSC.
Figure 5. (a). Section cut of 3D vertical ferroelectric HZO−based FTJ array structure. (b) Diagram of 1/2 bias training of FTJ array structure. (c) The curve of the change in conductance according to the pulse number, the difference in conductance between the selected-synapse and the half-selected synapse effectively changed. (d) The test set trained 50 letter patterns at 20 epochs, and these characters recorded high accuracy of more than 96%. With permission from Ref. [80], 2018, RSC.
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Figure 6. (a) The RL system in a parallel structure operates by read operation the maximum current from Word-line to Bit−line. (b) Changes in conductivity of FTJ by positive and negative pulses. (c) Minimum convergence time and optimal voltage by different conductance. (d) Vm in inverse proportion to HZO thickness. (e) Vm in inverse proportion to Zr concentration with permission from Ref. [81], 2019, IEEE.
Figure 6. (a) The RL system in a parallel structure operates by read operation the maximum current from Word-line to Bit−line. (b) Changes in conductivity of FTJ by positive and negative pulses. (c) Minimum convergence time and optimal voltage by different conductance. (d) Vm in inverse proportion to HZO thickness. (e) Vm in inverse proportion to Zr concentration with permission from Ref. [81], 2019, IEEE.
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Figure 7. (a) ID-VG curve with 3-bit operation from double HZO layers; (b) decreased polarization in corner region for GAA FeFET with a single HZO layer by TCAD; (c) endurance (>1011) and MW (=0.9 V) characteristics obtained using double HZO layer; and (d) schematic of the effect of polarization field on corner areas when single and double HZO layers are used with permission from Ref. [92], 2022, IEEE.
Figure 7. (a) ID-VG curve with 3-bit operation from double HZO layers; (b) decreased polarization in corner region for GAA FeFET with a single HZO layer by TCAD; (c) endurance (>1011) and MW (=0.9 V) characteristics obtained using double HZO layer; and (d) schematic of the effect of polarization field on corner areas when single and double HZO layers are used with permission from Ref. [92], 2022, IEEE.
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Figure 8. (a) Trap density for interface/bulk of deep-level through C-V measurement; (b) XPS analysis confirms the effective inhibition of oxygen vacancies in the ITO-IGZO channel device; (c) 200 ns delay occurred during read after programming operation; (d) The energy band diagram shows that the self-compensation effect is capable of good passivation for defects with permission from Ref. [93], 2022, IEEE.
Figure 8. (a) Trap density for interface/bulk of deep-level through C-V measurement; (b) XPS analysis confirms the effective inhibition of oxygen vacancies in the ITO-IGZO channel device; (c) 200 ns delay occurred during read after programming operation; (d) The energy band diagram shows that the self-compensation effect is capable of good passivation for defects with permission from Ref. [93], 2022, IEEE.
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Figure 9. (a) Programming identical pulse; (b) increasing programming pulse width; (c) increasing programming pulse voltage; (d) the polarization states of 32 levels did not overlap each other, resulting from the cycle-to-cycle variation of each polarization state; (e) as a result of the simulation for three neural networks, the pattern recognition accuracy was 84.34% recorded with permission from Ref. [96], 2017, IEEE.
Figure 9. (a) Programming identical pulse; (b) increasing programming pulse width; (c) increasing programming pulse voltage; (d) the polarization states of 32 levels did not overlap each other, resulting from the cycle-to-cycle variation of each polarization state; (e) as a result of the simulation for three neural networks, the pattern recognition accuracy was 84.34% recorded with permission from Ref. [96], 2017, IEEE.
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Figure 10. (a) 3D structure of nanowire FET with Ge-channel; (b) ID-Accumulated pulse time curve showing polarization switching limits less than 10 ns; and (c) accumulated 100 ps pulse train to detect polarization transition with permission from Ref. [98], 2018, IEEE.
Figure 10. (a) 3D structure of nanowire FET with Ge-channel; (b) ID-Accumulated pulse time curve showing polarization switching limits less than 10 ns; and (c) accumulated 100 ps pulse train to detect polarization transition with permission from Ref. [98], 2018, IEEE.
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Figure 11. Polarization state by applying different voltage pulses to the top and bottom gates of the (a) MoS2 FET; and (b) MoTe2 FET; (c) ‘And’ and ‘XNOR’ Boolean logic gate operation results table with permission from Ref. [101], 2018, ACS.
Figure 11. Polarization state by applying different voltage pulses to the top and bottom gates of the (a) MoS2 FET; and (b) MoTe2 FET; (c) ‘And’ and ‘XNOR’ Boolean logic gate operation results table with permission from Ref. [101], 2018, ACS.
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Yoo, J.; Song, H.; Lee, H.; Lim, S.; Kim, S.; Heo, K.; Bae, H. Recent Research for HZO-Based Ferroelectric Memory towards In-Memory Computing Applications. Electronics 2023, 12, 2297. https://doi.org/10.3390/electronics12102297

AMA Style

Yoo J, Song H, Lee H, Lim S, Kim S, Heo K, Bae H. Recent Research for HZO-Based Ferroelectric Memory towards In-Memory Computing Applications. Electronics. 2023; 12(10):2297. https://doi.org/10.3390/electronics12102297

Chicago/Turabian Style

Yoo, Jaewook, Hyeonjun Song, Hongseung Lee, Seongbin Lim, Soyeon Kim, Keun Heo, and Hagyoul Bae. 2023. "Recent Research for HZO-Based Ferroelectric Memory towards In-Memory Computing Applications" Electronics 12, no. 10: 2297. https://doi.org/10.3390/electronics12102297

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