Search Results (753)

This paper proposes an energy-efficient LiDAR receiver topology based on a time-to-voltage converter (TVC) followed by a 5-bit SAR ADC. By converting the time-interval between START and STOP signals into the voltage domain, the proposed topology avoids the complexity of conventional TDC-based designs and enables the use of a moderate-speed, energy-efficient SAR ADC. The proposed TVC in the proposed LiDAR receiver consists of an on-chip avalanche photodiode (APD), a CMOS transimpedance-limiting amplifier (CTLA), a time-gating circuit, a ramp generator, and a peak-and-hold (PDH) block. Thereafter, the converted voltages are digitized by a VCM-based single-ended SAR ADC with a binary-weighted CDAC, a strong-arm latch comparator, and custom digital logic. A reset generator is also incorporated to coordinate the sampling, comparison, and settling phases. The proposed LiDAR receiver is implemented in a 180 nm CMOS process, where the TVC occupies an area of 171 μm × 98.8 μm, while the TVC-SAR receiver occupies 417 μm × 356 μm, respectively. The proposed LiDAR receiver consumes 13 mW from a single 1.8 V supply, in which the SAR ADC consumes 3.68 mW only. The TVC-SAR receiver resolves the time-intervals ranging from 7 ns to 32.1 ns with a resolution of 0.81 ns. Hence, the proposed topology provides an energy-efficient solution along with its reduced circuit complexity and chip implementation for short-range LiDAR applications. Full article

Edge Internet of Things (IoT) blockchain deployments increasingly rely on continuous transaction ingestion from resource-constrained IoT devices to nearby edge gateways over heterogeneous wireless links. In this setting, transient channel noise and packet corruption can inject invalid payloads into the edge processing pipeline and trigger unnecessary buffering, parsing, and, most critically, computationally expensive cryptographic operations such as digital signature verification. This leads to wasted computation, increased latency, and reduced energy efficiency at the edge, particularly under dense IoT traffic. This paper presents an energy-aware and fault-tolerant Quantum-Dot Cellular Automata (QCA)-based integrity pre-filter for IoT-to-edge blockchain transaction ingestion. At the circuit level, we adapt and modify a previously reported fault-tolerant five-input majority gate (MV5) structure and use it as a robust primitive for nanoscale integrity-screening circuits. Building on this modified MV5, we design a set of QCA integrity blocks, including a parity checker, a compact XNOR gate circuit, a parity-bit generation circuit, and a sender-to-channel/receiver nano-communication integrity workflow suitable for early screening of corrupted payloads. Compared with the best previously reported baseline considered in this study, the modified MV5 achieves 76.47% tolerance to single-cell omission defects, corresponding to a 17.47 percentage-point increase and an approximately 29.61% relative improvement over the prior 59% omission-tolerance result, while preserving 100% tolerance against extra-cell deposition defects. At the system level, the proposed circuit is discussed as a potential early screening stage for edge-IoT blockchain transaction ingestion. A bounded analytical model is used to estimate the possible reduction in unnecessary signature-verification workload under assumed corruption and detection conditions. This analysis is not intended as a deployment-level validation; full edge-node implementation, throughput measurement, queueing-delay evaluation, real traffic traces, retransmission behavior, and empirical signature-verification profiling remain future work. The proposed parity/chunk-parity pre-filter is designed for low-cost detection of random transmission-induced corruption and does not replace cryptographic authentication, hashing, digital signatures, CRC-based detection, or blockchain validation. All proposed designs are validated using QCADesigner tools. Full article

The demands for equalization accuracy in traveling wave tube power amplifiers (TWTAs) are increasingly stringent, and traditional analog equalizers are no longer sufficient. Furthermore, the low level of digitization in TWTAs makes the direct application of digital equalization techniques difficult. This study designs a digital equalizer system for Ka-band TWTAs that controls high-precision digital step attenuators (DSAs). By processing the RF link, the dynamic analog power signal was converted into a digital square wave, and digital equalization control was achieved using an STM32F103 microcontroller (STMicroelectronics, Geneva, Switzerland; Origin: Taiwan, China). Simulation and experimental results show that the system operates stably within the input dynamic power range of −20 to 0 dBm, with an overall control delay of approximately 2 ms, a frequency measurement error of less than 0.02%, and an equalization accuracy better than 0.25 dB. This work addresses the critical interface bottleneck between high-frequency analog TWT chains and digital control circuits, offering a reusable engineering solution for the digital upgrade of TWTA products. Full article

Memristors, as programmable resistive switching devices, offer two fundamental computational modalities for artificial intelligence: static conductance for parallel data processing and dynamic switching for temporal, logical, and stochastic operations. This Review systematically distinguishes these two modalities and evaluates their respective hardware implementations. In terms of our review scope, we first examine how static conductance modality is exploited in analog matrix computing, which encompasses matrix–vector multiplication and matrix equation solving, and discuss how these primitives enable efficient neural network inference and training. Second, we survey dynamic switching modality and its algorithmic applications, including stateful logic for digital in-memory acceleration, attractor networks for associative memory, reservoir computing and spatiotemporal signal processing using transient device dynamics, biologically inspired spike-timing-dependent plasticity, and stochastic computation. In addition, we discuss key challenges such as device variability, stochastic switching, interconnect parasitics, peripheral circuit overhead, and endurance limitations. We also highlight opportunities for future development, emphasizing algorithm–hardware co-design to leverage application-specific error tolerance and mitigate device non-idealities. Finally, we outline promising research directions aimed at realizing robust, scalable, and energy-efficient memristor-based AI systems. Full article

Accurate measurement of spool displacement is essential for achieving high-performance closed-loop control and condition monitoring in hydraulic systems. However, conventional inductive displacement transducers typically rely on sinusoidal excitation and complex analog signal conditioning circuits, resulting in higher hardware cost and limited system integration. To address these issues, this paper proposes a software-based demodulation method for a differential inductive displacement transducer under symmetric complementary square-wave excitation. First, the structure and operating principle of the transducer are analyzed, and an electromagnetic model describing the nonlinear relationship between coil inductance and the position of the inductive core is established, along with its electrical characteristics. Then, a simplified signal acquisition circuit is designed to enable digital extraction of inductance variations using a microprocessor. Compared with conventional approaches, the proposed scheme significantly reduces hardware complexity and cost while being more suitable for embedded system integration. A simulation model is developed to analyze the inductance variation and to validate the proposed hardware circuit. In addition, a test platform is built to conduct static calibration and dynamic response experiments. The experimental results show that the proposed method achieves a linearity of 2.36% and a sensitivity of 155.6 mV/mm and exhibits strong robustness against switching noise. Finally, application tests in a hydraulic valve system demonstrate that the proposed transducer and demodulation method enable accurate and stable spool position measurement, providing a low-cost and easily integrated solution for embedded hydraulic control systems. Full article

This paper presents a time-domain closed-loop resistive temperature sensor architecture. The design employs a frequency-locked loop (FLL)-based oscillator as the sensing element, generating a monotonic frequency response to temperature variations. The output frequency is digitized on-chip and converted into a temperature code. Within the oscillator core, a switched-capacitor technique converts frequency to voltage for closed-loop control, reducing charging/discharging voltage swings and significantly lowering dynamic power consumption. The FLL topology enhances frequency stability, minimizes distortion, and suppresses power supply sensitivity. Fabricated in a 180 nm CMOS process with a core area of 0.12 mm², the sensor achieves a peak-to-peak inaccuracy of +1.2 °C/−0.9 °C from −40 °C to 125 °C. Operating at 1 V, the circuit consumes only 10 μW with a resolution of 51 mK within 12 ms. Full article

With the rapid advancement of digital integrated circuits, transistor sizes and integration levels have grown at an unprecedented rate, leading to increasingly complex design processes. A key challenge in digital layout design is the placement and routing of standard cell circuit layouts, which directly impact chip quality and performance. Power is a critical factor in evaluating standard cells. To enable low-power standard cell layouts, the depth-first search (DFS) algorithm is proposed to model and place the standard cell. Additionally, the study aims to satisfy Design Rule Checking (DRC), a grid routing strategy based on the deep reinforcement learning (DRL) algorithm, which quickly identifies cell boundaries and barriers such as existing nets as well as contacts, while optimizing metal routing to achieve minimal power. Results show that the standard cell layouts generated by the DRL-based model achieve over a 90% reduction in design time and approximately 5% improvements in power compared with manual layouts. The proposed method facilitates the rapid development of standard cell library and has important engineering value. Full article

All-optical logic gates have emerged as a critical technology for enabling broadband, low-loss, and high-speed communication systems, addressing the inherent bandwidth limitations of electronic counterparts. Here, we propose a Y-shaped structure leveraging unidirectional modes in the terahertz regime, which enables the realization of multifunctional all-optical logic gates within the lower- and upper-frequency bandwidth regions, including, but not limited to, AND, OR, NOT, and XNOR gates. Numerical simulations and theoretical analyses confirm that the proposed logic gates exhibit robust one-way propagation characteristics, with electromagnetic signals demonstrating complete immunity to backscattering even in the presence of structural defects. Furthermore, nonlocal effects are found to have a negligible impact on the operational bandwidths of our design. Building upon this Y-shaped configuration, we further develop an all-optical digital logic system (AODLS) capable of supporting bifrequency multi-input and multi-output logic operations. When lower- and upper-frequency signals are injected into separate input ports, their corresponding output signals remain fully independent, eliminating cross-talk and enabling true parallel computation. This dual-band parallel processing capability represents a significant advance over conventional single-band all-optical logic systems, opening new avenues for high-throughput all-optical computing and integrated photonic circuits. Full article

Microchannel plate gated framing camera is commonly used in inertial confinement fusion diagnostics. However, it is a vacuum electronic device with bulkiness and non-single-line-of-sight imaging. To reduce the size of the camera and achieve a single line of sight image, a CMOS image sensor composed of a pixel unit and a readout circuit is presented to form the framing camera. The CMOS image sensor has a 32 × 32 × 4 pixel array with ultrashort shutter-time and four-frame imaging. The pixel array and analog to digital converter (ADC) readout circuit are designed using a standard 0.18 μm CMOS process. The pixel array includes 5T structured pixel units, a voltage-controlled delay, a clock tree and the row decoding scan circuits. A temporal resolution of 65 ps for the pixel circuit is achieved. The ADC readout circuit is composed of a counter, a comparator, a ramp generator and a register, which operates at a sampling frequency of 24.41 kS/s. An effective number of bits of 11.3, a spurious free dynamic range (SFDR) of 73.4 dB, and a signal-to-noise ratio (SNR) of 70.0 dB for the ADC are achieved. The CMOS image sensor will provide a novel and important imaging method for the field of ultrafast science. Full article

Heart rate variability (HRV) is a key physiological marker for autonomic nervous system function and cardiovascular health. Photoplethysmography (PPG) is commonly used to derive HRV metrics in wearable and low-cost monitoring systems. This study presents a comparative assessment of basic HRV metrics obtained from a MAX30102 optical sensor and a custom analog circuitry with an ADS1115 analog-to-digital converter (ADC). Both measurement pathways were carefully aligned using analog high-pass and low-pass filters and a consistent digital filtering pipeline, ensuring that the frequency bands relevant to HRV were preserved. PPG signals were recorded simultaneously, and inter-beat intervals were extracted to calculate the Standard Deviation of NN intervals (SDNN), Root Mean Square of Successive Differences (RMSSD), and Percentage of successive NN intervals >50 ms (pNN50) across multiple 30-s windows. Bland–Altman analysis was employed to evaluate agreement between the two methods. Results indicate that the analog circuit with an ADS1115 achieves comparable HRV basic metrics to the MAX30102 sensor, with improved Signal-to-Noise Ratio (SNR) due to high-resolution ADC and low-noise analog amplification. These findings demonstrate that a carefully designed analog acquisition system can reliably reproduce HRV basic parameters from PPG signals, providing an alternative approach for low-cost, flexible biosensing platforms. Full article

In the era of highly integrated circuits, continuous miniaturization has significantly increased routing complexity, thereby directly impacting circuit performance. As process scaling advances and the number of on-chip metal layers increases, conventional standard cell libraries face limitations that cause severe routing bottlenecks. To overcome these limitations, this paper proposes a dual-component approach. First, we introduce a novel standard cell structure that improves routing flexibility by expanding the degrees of freedom for pin access, particularly in highly congested regions. Second, we present a physical design methodology specifically designed to ensure seamless integration with existing electronic design automation (EDA) tools, allowing new cells to be effectively placed and routed without major modifications to current flows. The proposed approach was validated using the open-source ASAP7 process design kit (PDK). Experimental results confirm significant reductions in via count and total wirelength, leading to improved routability, reduced power consumption, and enhanced performance. These findings demonstrate that combining the new cell architecture with a tailored design methodology provides a practical alternative to conventional solutions, enabling more efficient and scalable circuit designs for future technology nodes. Full article

Mixed-signal simulation is indispensable for verifying modern integrated circuits that tightly couple analog and digital subsystems, yet the field lacks a unified framework for systematically comparing its diverse methodologies. This paper addresses that gap by proposing a novel three-axis taxonomy that classifies simulation methods along abstraction level, solver methodology, and analysis type, together with a comparative evaluation framework based on five quantitative metrics: accuracy, throughput, capacity, convergence reliability, and scalability. Applying this framework, we systematically compare thirteen classical method categories—spanning SPICE, FastSPICE, RF/periodic steady-state, behavioral modeling, co-simulation, and model order reduction—and eight AI/ML approaches including Gaussian process surrogates, graph neural networks, physics-informed neural networks, Bayesian optimization, and reinforcement learning. Our analysis reveals a clear maturity stratification: classical methods remain the only signoff-accurate approaches, Bayesian optimization represents the most industrially validated AI contribution with integration across all three major EDA platforms, while Neural ODE solvers and LLM-based design tools remain at the research stage. We identify a persistent academic-to-industry gap driven by foundry model complexity, limited benchmark diversity, and topology-specific overfitting. The proposed taxonomy and comparative framework provide practitioners with structured guidance for simulation method selection and highlight specific research directions needed to bridge the gap between AI promise and industrial deployment. Full article

In digital signal processing, the finite impulse response (FIR) filter is a fundamental tool for processing discrete-time signals. This paper explores the implementation of FIR filters using quantum computation methods. In this study, a quantum circuit for the FIR filter is designed using a normalized filter coefficient vector, orthogonal triangular decomposition commonly known as QR decomposition, and the transpilation tools provided by IBM’s software Qiskit SDK V2.3. Then, each block of the input signal is normalized to a unit-norm vector, loaded into a quantum register, and processed by the FIR filter quantum circuit to produce an output state. Quantum measurement is then performed on the output state to obtain a histogram, from which the first-bin data are scaled to compute the output sample of the filter. Finally, signal filtering experiments using FIR mean filters are conducted to demonstrate the effectiveness of the proposed quantum computation approach. Full article

A monolithic digital Silicon Photomultiplier (SiPM) featuring 1024 microcells with a 30-micrometer pitch and a 50% fill factor has been designed in a 110-nanometer CMOS image sensor technology. The device under consideration integrates both SPAD sensors and front-end electronics in the same substrate. It can count up to 1024 photons in less than 22 ns, while assigning timestamps to the first and last detected photons with a time resolution of less than 100 ps. A parallel counter structure combined with a fast adder tree provides photon counting in digital form with low latency, whereas a carefully balanced fast NAND tree ensures a fixed-pattern time uncertainty not exceeding 26 ps. The architecture incorporates in-pixel memory for individual cell disabling and configurable thresholding on the timing signal for noise mitigation. In order to optimize the fill factor, a part of the electronics is placed outside the array, while the most sensitive elements of the timing and counting circuits are laid out close to the sensor, in the SPAD array. A serial readout is employed to provide a single output connection per SiPM, thereby simplifying system integration. Full article

Cultural heritage, in all its tangible and intangible expressions, is undergoing a process of renewal driven by the integration of digital technologies and participatory approaches. This study presents a pilot project developed within the SAMOTHRACE Fundation, focused on the design of a Serious Game dedicated to the Norman Castle of Aci Castello in Sicily. The project explores how game-based learning and interactive storytelling can enhance visitor engagement, accessibility, and understanding of small-scale heritage sites that are often excluded from major cultural circuits. Using Unity and Blender, the prototype combines historical research, 3D reconstruction, and narrative interaction to transform the castle into an immersive educational environment. This initial phase also served as the basis for an academic thesis, laying the methodological groundwork for future expansion and evaluation. The results of this pilot provide preliminary quantitative evidence that serious games can support cultural communication strategies, foster emotional engagement, and stimulate curiosity toward minor heritage sites, while remaining compatible with the constraints of modest institutions. Ultimately, the project illustrates how even modest institutions can leverage digital innovation to revitalize their heritage assets, promote inclusive participation, and explore new models of interactive archaeology and community-centered cultural engagement. Full article