Search Results (73)

With their superior switching speed, GaN high-electron-mobility transistors (HEMTs) enable high power density, reduce energy losses, and increase power efficiency in a wide range of applications, such as power electronics, due to their high breakdown voltage. GaN-HEMT devices are subject to long-term reliability due to the self-heating effect and lattice mismatch between the SiC substrate and the GaN. Depletion-mode GaN HEMTs are utilized for radio frequency applications, and this work investigates three wide-bandgap (WBG) GaN HEMT fixed-frequency oscillators with output buffers. The first GaN-on-SiC HEMT oscillator consists of an HEMT amplifier with an LC feedback network. With the supply voltage of 0.8 V, the single-ended GaN oscillator can generate a signal at 8.85 GHz, and it also supplies output power of 2.4 dBm with a buffer supply of 3.0 V. At 1 MHz frequency offset from the carrier, the phase noise is −124.8 dBc/Hz, and the figure of merit (FOM) of the oscillator is −199.8 dBc/Hz. After the previous study, the hot-carrier stressed RF performance of the GaN oscillator is studied, and the oscillator was subject to a drain supply of 8 V for a stressing step time equal to 30 min and measured at the supply voltage of 0.8 V after the step operation for performance benchmark. Stress study indicates the power oscillator with buffer is a good structure for a reliable structure by operating the oscillator core at low supply and the buffer at high supply. The second balanced oscillator can generate a differential signal. The feedback filter consists of a left-handed transmission-line LC network by cascading three unit cells. At a 1 MHz frequency offset from the carrier of 3.818 GHz, the phase noise is −131.73 dBc/Hz, and the FOM of the 2nd oscillator is −188.4 dBc/Hz. High supply voltage operation shows phase noise degradation. The third GaN cross-coupled VCO uses 8-shaped inductors. The VCO uses a pair of drain inductors to improve the Q-factor of the LC tank, and it uses 8-shaped inductors for magnetic coupling noise suppression. At the VCO-core supply of 1.3 V and high buffer supply, the FOM at 6.397 GHz is −190.09 dBc/Hz. This work enhances the design techniques for reliable GaN HEMT oscillators and knowledge to design high-performance circuits. Full article

This paper presents a wideband low-power/low-voltage 60-GHz low-noise amplifier (LNA) in a 28-nm bulk CMOS technology. The LNA has been designed for high-speed millimeter-wave (mm-wave) communications. It consists of two pseudo-differential amplifying stages and a buffer stage included for 50-Ohm on-wafer measurements. Two integrated input/output baluns guarantee both simultaneous 50-ohm input–noise/output matching at input/output radio frequency (RF) pads. A power-efficient design strategy is adopted to make the LNA suitable for low-power applications, while minimizing the noise figure (NF). Thanks to the adopted design strategy, the post-layout simulation results show an excellent trade-off between power gain and 3-dB bandwidth (BW_3dB) with 13.5 dB and 7 GHz centered at 60 GHz, respectively. The proposed LNA consumes only 11.6 mA from a 0.9-V supply voltage with an NF of 8.4 dB at 60 GHz, including the input transformer loss. The input 1 dB compression point (IP_1dB) of −15 dBm at 60 GHz confirms the first-rate linearity of the proposed amplifier. Human body model (HBM) electrostatic discharge (ESD) protection is guaranteed up to 2 kV at the RF input/output pads thanks to the input/output integrated transformers. Full article

This paper presents a broadband near-field probe designed for measuring the normal magnetic field ($H_z$) in radio frequency (RF) circuits operating within a frequency range of 2–8 GHz. The proposed probe uses a cost-effective 4-layer printed circuit board (PCB) structure made with an FR-4 substrate. The probe primarily consists of an $H_z$ detection unit, a broadband microstrip balun, and a coaxial-like output. The broadband balun facilitates the conversion from differential to single-ended signals, thereby enhancing the probe’s common-mode rejection capability. This design ensures that the probe achieves both cost efficiency and high broadband measurement performance. Additionally, this work investigates the feasibility of employing microstrip lines as calibration standards for the $H_z$ probe. The probe’s structural parameters and magnetic field response were initially determined through simulations, and the calibration factor was subsequently verified by calibration experiments. In practical measurements, the field distributions above a microstrip line and a low-noise amplifier (LNA) were captured. The measured field distribution of the microstrip line was compared with simulation results to verify the probe’s performance. Meanwhile, the measured field distribution of the LNA was utilized to identify the radiating components within the amplifier. Full article

This paper presents a fully integrated bandpass filter (BPF) with high tunability based on a novel differential active inductor (DAI), designed for sensor interface circuits operating in the ultra-high frequency (UHF) band. The design of the proposed DAI is based on a symmetrical configuration, utilizing a differential amplifier for the feedforward transconductance and a common-source (CS) transistor for the feedback transconductance. By integrating a cascode scheme with a feedback resistor, the quality factor of the active inductor is significantly improved, leading to enhanced mid-band gain for the bandpass filter. To facilitate independent tuning of the BPF‘s center frequency and mid-band gain, an active resistor adjustment and bias voltage control are employed, providing precise control over the filter’s operational parameters. Post-layout simulations and process corner results are conducted with 0.13 µm CMOS technology at 1.2 V supply voltage. The proposed second order BPF achieves a broad tuning range of 280 MHz to 2.426 GHz, with a passband gain between 8.9 dB and 16.54 dB. The design demonstrates a maximum noise figure of 16.54 dB at 280 MHz, an input-referred 1 dB compression point of −3.78 dBm, and a third-order input intercept point (IIP3) of −0.897 dBm. Additionally, the BPF occupies an active area of only 68.2×30 µm², including impedance-matching part, and consumes a DC power of 14–20 mW. The compact size and low power consumption of the design make it highly suitable for integration into modern wireless sensor interfaces where performance and area efficiency are critical. Full article

In order to meet the application requirements for high-precision and low-noise accelerometers in micro-vibration measurement and navigation fields, this paper presents the design and testing of an ultra-high-capacitance resolution capacitive readout circuit with attofarad-level precision. First, a differential charge amplifier circuit is employed for the first stage of capacitance detection. To suppress noise interference in the circuit, a frequency-domain modulation technique is utilized to mitigate low-frequency noise. Subsequently, a differential subtraction circuit is implemented to reduce common-mode noise. Additionally, an improved filtering circuit is designed to suppress noise interference in the final stage. The test results indicate that the designed circuit operates at a carrier frequency of 1 MHz, achieving a capacitance resolution of up to 0.103 aF/H${\mathrm{z}}^{1/2}$ and a noise floor of 25.6 $\mathsf{\mu }$g/H${\mathrm{z}}^{1/2}$, thereby meeting the requirements for high-precision and low-noise capacitance detection in MEMS accelerometers. Full article

Continuous-time Sigma-Delta (CTSD) Analog-to-Digital Converter (ADC) is widely used in wireless receivers due to its built-in anti-aliasing and resistive input. In order to achieve a wide bandwidth while ensuring low power consumption, this paper proposes a CT 2-2 Multi-stAge Noise-sHaping (MASH) ADC for wireless communication. In order to reduce power consumption, the loop filter adopts a feedforward structure, and the operational amplifier uses complementary differential input pairs and feedforward compensation. The pseudo-random sequence injection and Least Mean Squares (LMS) algorithm are adopted to calibrate the digital noise cancelation filter to match the analog transfer function. The simulation results obtained in 40 nm CMOS show that the presented 2-2 CT MASH ADC achieves a 76.8 dB signal-to-noise-and-distortion ratio (SNDR) at a 50MHz bandwidth (BW) with a 1.6 GHz sampling rate and consumes 29.7 mW power under 1.2/0.9 V supply, corresponding to an excellent figure of merit (FoM) of 169.1 dB. Full article

The feed-through effect of resonant pressure sensors usually introduces interfering noise signals, leading to the degradation of sensitivity, linearity, and other performances of the sensor test system. A low-noise charge amplifier and its feed-through compensation circuit are designed to realize high-precision measurements. The designed improved charge amplifier has a differential common-source structure as the output buffer stage, which can effectively reduce the output noise of the circuit while increasing the input impedance, thus improving the accuracy of the feed-through compensation coefficient. By establishing the equivalent circuit model of the sensor and analyzing the influence of the feed-through effect on the sensor test, the feed-through compensation circuit is designed to suppress the feed-through signal. Experimental testing of the sensor proves that the designed circuit can effectively suppress the feed-through effect of the sensor. The noise power spectral density of the improved charge amplifier is tested to be 26.74 nV/√Hz, which is a 65% reduction in noise density. The feed-through compensation circuit eliminates the interference frequency of 34,919 Hz introduced by the feed-through capacitor. Additionally, the resonance peak of the intrinsic resonance frequency of the pressure sensor is −40.75 dBV, which is reduced by 8 dBV compared with that before the feed-through compensation. The feed-through compensation circuit effectively reduces the feed-through interference signal of the sensor, improves the measurement accuracy of the test system, and provides technical support for the design of a low-noise, high-precision, stable, and reliable sensor test system. Full article

This paper presents a low-power, fully differential, programmable gain amplifier (PGA) for ultrasound receiver analog front-ends (AFE). It consists of a programmable attenuator implemented by a capacitive voltage divider and a closed-loop amplifier based on a differential difference amplifier (DDA). A suitable sizing strategy provides orthogonal control over gain and bandwidth. The PGA was designed using a standard 180 nm CMOS process. The gain value can be set between −18 dB and +20 dB in 2 dB steps; the bandwidth can be programmed independently of gain, to values from 5 MHz to 20 MHz, in 5 MHz steps; it draws 600 µA from a 1.8 V supply line. It achieves a differential output swing of 0.8 V peak-to-peak differential with no more than 1.7% total harmonic distortion (THD) and an input-referred noise density of 22 nV/√Hz at 10 MHz, measured at the gain of 20 dB. The PGA exhibits high input impedance and low output resistance for easy integration within the AFE signal chain. The digitally controlled gain and bandwidth make this PGA suitable for ultrasound imaging applications requiring precise time gain compensation and adjustable frequency response and/or additional anti-aliasing filtering. Full article

Semiconductor radiation detectors usually use a specific signal conditioning circuit, ensuring the required detection system parameters. This paper details the noise properties of specific input stages in photoreceivers that detect various types of radiation. For this purpose, the popular silicon PIN photodiode (BPW34) and two different types of low-noise operational amplifiers (AD797A and ADA4625-1) were used. In the presented experiments, noise measurements were provided for voltage and transimpedance amplifiers operating in input stages, comparing their noise and bandwidths. This made it possible to obtain results for bipolar junction transistor (BJT)- and field-effect transistor (FET)-based input stages of circuity, cooperating directly with a photodiode. Analyzing the obtained characteristics and considering the photodiode operation mode, it is evident that the transimpedance amplifier and photoconductive mode should be considered a typical first-choice solution. In some cases, the performances, such as bandwidth and noise, may be similar to those of voltage. Nevertheless, the bias method used in TIA and feedback compensation can also affect the resulting output noise spectral characteristics due to the photodiode and other capacitances existing in the circuit. In the case of a high transimpedance, the FET-based op-amps ensure lower output noise than the BJT-based ones due to the significantly lower current noise. The simple radiation detector with two-channel differential TIA was also proposed and tested based on the results obtained. Full article

This paper proposes a low-power 10-bit 20 MS/s pipelined analog-to-digital converter (ADC) designed for the burgeoning needs of low-data-rate communication systems, particularly within the Internet of Things (IoT) domain. To reduce power usage, multiple power-saving techniques are combined, such as sample-and-hold amplifier-less (SHA-less) architecture, capacitor scaling, and dynamic comparators. In addition, this paper presents a novel operational amplifier (op-amp) with gain boosting, featuring a dual-input differential pair that enables internal pipeline stage switching, effectively alleviating the crosstalk and memory effects inherent in conventional shared op-amp configurations, thereby further reducing power consumption. A prototype ADC was fabricated in a 180 nm CMOS process and the core size was 0.333 mm². The ADC implemented operated at a 20 MHz sampling rate under a 1.8 V supply voltage. It achieved a spurious-free dynamic range (SFDR) of 61.83 dB and a signal-to-noise-and-distortion ratio (SNDR) of 54.15 dB while demonstrating a maximum differential non-linearity (DNL) of 0.36 least significant bit (LSB) and a maximum integral non-linearity (INL) of 0.67 LSB. Notably, the ADC consumed less than 5 mW of power at the mentioned sampling frequency, showcasing excellent power efficiency. Full article

This paper introduces an analog differential optoelectronic receiver (ADOR) integrated with digital slicers for short-range LiDAR systems, consisting of a spatially modulated P⁺/N-well on-chip avalanche photodiode (APD), a cross-coupled differential transimpedance amplifier (CCD-TIA) with cross-coupled active loads, a continuous-time linear equalizer (CTLE), a limiting amplifier (LA), and dual digital slicers. A key feature is the integration of an additional on-chip dummy APD at the differential input node, which enables the proposed ADOR to outperform a traditional single-ended TIA in terms of common-mode noise rejection ratio. Also, the CCD-TIA utilizes cross-coupled PMOS-NMOS active loads not only to generate the symmetric output waveforms with maximized voltage swings, but also to provide wide bandwidth characteristics. The following CTLE extends the receiver bandwidth further, allowing the dual digital slicers to operate efficiently even at high sampling rates. The LA boosts the output amplitudes to suitable levels for the following slicers. Then, the inverter-based slicers with low power consumption and a small chip area produce digital outputs. The fabricated ADOR chip using a 180 nm CMOS process demonstrates a 20 dB dynamic range from 100 μA_pp to 1 mA_pp, 2 Gb/s data rate with a 490 fF APD capacitance, and 22.7 mW power consumption from a 1.8 V supply. Full article

The design of transformers, a key component of radio frequency integrated circuits (RFICs), is traditionally carried out through an iterative process involving extensive electromagnetic simulations. While process design kits (PDKs) offer tools based on interpolation or fitting equations to simplify parameter estimation, these tools are restricted to standard geometries, leaving designers to manually simulate and optimize custom designs. This approach is inefficient and resource intensive. This paper proposes an automated process to generate a database containing the physical and electrical parameters of a wide range of transformers. This database is part of a tool designed to efficiently identify the desired transformer. To evaluate the tool’s effectiveness in reducing the time required for design, a millimeter-wave (mm-Wave) 69.4–74.2 GHz differential low-noise amplifier (LNA) is designed using GlobalFoundries 45 nm silicon-on-insulator (SOI) technology. This circuit demonstrates a noise figure (NF) of 4.1 dB, a gain of 10.1 dB, an input third-order intercept point (IIP3) of −10.78 dBm, and a power consumption of 4.7 mW from a 0.406 V DC supply. Moreover, the simulated performance achieves these specifications within a highly compact area of 0.12 mm². The transformer selection process for the circuit takes only a few seconds, whereas the conventional method of manual transformer design and electromagnetic simulation would require a significantly greater amount of time. Full article

This paper introduces a Ku-band fully differential low-power high-input 1 dB compression point (P1dB) low-noise amplifier (LNA). A fully differential structure is employed to enhance the input P1dB, common-mode noise rejection, and second harmonic cancellation. The first stage adopts large transistors and is optimized for power consumption and noise figure (NF). The output stage is designed with class AB bias, resulting in improved P1dB, power consumption, and linearity. The proposed two-stage fully differential common-source (CS) LNA was implemented using 65 nm bulk complementary metal oxide semiconductor (CMOS) technology. The fabricated LNA achieved a minimum NF of 2.7 dB at 13.6 GHz. Furthermore, it achieved a maximum gain of 19.92 dB at 12.2 GHz. Additionally, the LNA has an input P1dB of −7.45 dBm and an output power 1 dB compression point (OP1dB) of 10.09 dBm, both measured at 15.6 GHz. The LNA operates with a power consumption of 11 mW at a 1 V supply, and occupies a core size of 0.75 mm × 0.35 mm. Full article

Micro-electro-mechanical system (MEMS) gas flowmeters are innovative devices that use microfabrication technology to measure gas flow with high precision and sensitivity. With MEMS technology, flow measurement can now be performed more accurately and compactly than ever, using low-power, compact, and highly accurate sensors. MEMS gas flowmeters utilize various principles to measure gas flow, including thermal, Coriolis, and pressure differential methods. A micro-flowmeter was developed by combining a MEMS sensor with a weak signal acquisition technique. High heat isolation and sensitivity can be achieved using a MEMS sensor with a thermal resistor-suspended VO₂ structure. Since SU-8 gum is used for the flow channel, the technology is simple and affordable, making it suitable for batch production. To acquire high-resolution, low-noise data, the device uses a super low bias current operational amplifier, aided by guard ring protection, and a 24-bit high-resolution ADC. The sensor and data acquisition combination shows that the flowmeter has favorable linearity and sensitivity between 0 and 50 mL/min at a specific offset voltage. Biochemical detection and medicine require a high-sensitivity, high-stability, and low-cost flowmeter. Full article

This paper presents a low-power 60 GHz low-noise amplifier (LNA) designed for Gbit/s applications using 28 nm CMOS technology. The LNA exploits a single-stage pseudo-differential architecture with integrated input transformer for both electrostatic discharge (ESD) protection and simultaneous noise/impedance matching. An effective power-constrained design strategy is adopted to pursue the lowest current consumption at the minimum noise figure (NF), with the best tradeoff between gain and frequency bandwidth. The LNA, which has been designed to drive an on–off keying (OOK) demodulator, is operated at a supply voltage as low as 0.9 V and achieves a voltage gain of about 21 dB with a 3 dB bandwidth of 2 GHz around 60 GHz. Thanks to the proper impedance transformation at the 60 GHz input, the amplifier exhibits an NF of 6.3 dB, also including the input transformer loss with a very low power consumption of about 5 mW. The adoption of a single-stage topology also allows an excellent input 1 dB compression point (IP_1dB) of −4.7 dBm. The input transformer guarantees up to 2 kV human body model (HBM) ESD protection. Full article