Search Results (75)

The present work proposes a novel fractional-order multifunction filter topology in current-mode (CM), which is designed based on the Modified Current Feedback Operational Amplifier (MCFOA). The proposed design simultaneously generates fractional-order low-pass (FO-LPF), high-pass (FO-HPF), and band-pass (FO-BPF) outputs while utilizing an optimized set of essential active and passive elements, thereby ensuring simplicity, cost efficiency, and compatibility with integrated circuits (ICs). The fractional-order feature allows precise control over the transition slope between the passband and the stopband, enhancing design flexibility. PSpice simulations validated the filter’s theoretical performance, confirming a 1 kHz cut-off frequency, making it suitable for VLF applications such as military communication and submarine navigation. Monte Carlo analyses demonstrate robustness against parameter variations, while a low THD, a wide dynamic range, and low power consumption highlight its efficiency for high-precision, low-power applications. This work offers a practical and adaptable approach to fractional-order circuit design, with significant potential in communication, control, and biomedical systems. Full article

In this paper, we present a novel enhanced recycling folded cascode (ERFC) operational transconductance amplifier (OTA), which exhibits high efficiency and a fast transient response under weak inversion. Our innovative combination of adaptive biasing with nested local feedback (ABNLF) effectively enhances the input transconductance and slew rate (SR), thus improving the transient response. By incorporating coupling capacitors at the output stage, we achieve a stable operating region with large signal responses. Both the traditional RFC OTA and the proposed ERFC OTA were designed in a 0.18 $\mathsf{\mu }$m CMOS process, operating at a power supply of 1.8 V, with quiescent currents of 8 $\mathsf{\mu }$A and 10.4 $\mathsf{\mu }$A, respectively. Post-layout simulations reveal a remarkable enhancement in the proposed ERFC OTA over the traditional RFC OTA, with the SR and gain–bandwidth (GBW) surging by 120- and 5.95-fold, respectively. This advancement boosts the efficiency of the traditional RFC OTA and provides an impressive figure of merit (FoM) of 130.04 (V/$\mathsf{\mu }$s)·pF/$\mathsf{\mu }$A. Full article

Conventional operational amplifier designs often experience parameter performance issues during the transition between complementary input differential stages, which restricts the full rail-to-rail common mode voltage swing. This paper presents an innovative charge pump architecture featuring a feedback supply selector that optimizes the transition performance. The proposed approach employs a switched-capacitor technique to boost the supply voltage by 1.5 V relative to the input voltage, thereby enabling the use of a single pMOS differential input stage. The novel supply selector dynamically chooses the maximum available voltage between the external supply and the boosted output, ensuring efficient transistor switching and improved biasing. Schematic-level and post-layout simulations in a 250 nm CMOS process validate the design under varied load currents, supply voltages, temperatures, and process corners. Results show a significant reduction in output voltage ripple, with a maximum value of 48 mV achieved post-layout, and enhanced overall efficiency, even under higher load currents. This architecture provides a robust and scalable solution for advanced operational amplifiers, particularly in fields where high performance and stability are critical. Full article

This paper reviews various design approaches for sensing schemes that utilize silicon nanowire (SiNW) ion-sensitive field-effect transistors (ISFETs) for pH-sensing applications. SiNW ISFETs offer advantageous characteristics, including a high surface-to-volume ratio, fast response time, and suitability for integration with complementary metal oxide semiconductor (CMOS) technology. This review focuses on SiNW ISFET-based biosensors in three key aspects: (1) major fabrication processes and device structures; (2) theoretical analysis of key performance parameters in readout circuits such as sensitivity, linearity, noise immunity, and output range in different system configurations; and (3) an overview of existing readout circuits with quantitative evaluations of N-type and P-type current-mirror-based circuits, highlighting their strengths and limitations. Finally, this paper proposes a modified N-type readout scheme integrating an operational amplifier with a negative feedback network to overcome the low sensitivity of conventional N-type circuits. This design enhances gain control, linearity, and noise immunity while maintaining stability. These advancements are expected to contribute to the advancement of the current state-of-the-art SiNW ISFET-based readout circuits. Full article

The recent trend in analog design to replace typical analog circuits with digital implementations has led to the use of resistive feedback to pull a CMOS inverter into the switching threshold region to achieve gain, which is ideal for analog operations. Here, we report a three-transistor (3T) CMOS resistive-feedback inverter-based amplifier capable of achieving high gain paralleled with reduced noise, low power consumption, and enhanced stability. Unlike conventional resistive-feedback inverter-based amplifiers, the transistors are operated in the subthreshold region, which allows for a lower supply voltage and current, leading to lower power consumption. Subthreshold conduction also reduces typical amplifier noise sources. This design provides a novel approach to resistive feedback in the inverter amplifier, allowing for a large gain while occupying minimal layout area. The reported amplifier design facilitates unique capabilities, e.g., detection of ultra-low (fC) charges or sub-pA currents for newly emerging PHz electronic and optoelectronic devices driven by few-cycle laser pulses. As proof of concept, the specifications of the proposed amplifier are successfully measured and verified by multiple test chips designed and fabricated in TSMC’s 180 nm CMOS process. The fabricated amplifier operates at a 1.35 V power supply with a measured voltage gain of 53.61 dB (or 480 V/V), a bandwidth of 94 kHz, and an equivalent input voltage noise of 6.4 nV/$\sqrt{\mathrm{Hz}}$, consuming only 13.5 µW. Full article

Semiconductor radiation detectors usually use a specific signal conditioning circuit, ensuring the required detection system parameters. This paper details the noise properties of specific input stages in photoreceivers that detect various types of radiation. For this purpose, the popular silicon PIN photodiode (BPW34) and two different types of low-noise operational amplifiers (AD797A and ADA4625-1) were used. In the presented experiments, noise measurements were provided for voltage and transimpedance amplifiers operating in input stages, comparing their noise and bandwidths. This made it possible to obtain results for bipolar junction transistor (BJT)- and field-effect transistor (FET)-based input stages of circuity, cooperating directly with a photodiode. Analyzing the obtained characteristics and considering the photodiode operation mode, it is evident that the transimpedance amplifier and photoconductive mode should be considered a typical first-choice solution. In some cases, the performances, such as bandwidth and noise, may be similar to those of voltage. Nevertheless, the bias method used in TIA and feedback compensation can also affect the resulting output noise spectral characteristics due to the photodiode and other capacitances existing in the circuit. In the case of a high transimpedance, the FET-based op-amps ensure lower output noise than the BJT-based ones due to the significantly lower current noise. The simple radiation detector with two-channel differential TIA was also proposed and tested based on the results obtained. Full article

This paper presents a low-noise CMOS transimpedance-limiting amplifier (CTLA) for application in LiDAR sensor systems. The proposed CTLA employs a dual-feedback architecture that combines the passive and active feedback mechanisms simultaneously, thereby enabling automatic limiting operations for input photocurrents exceeding 100 µA_pp (up to 1.06 mA_pp) without introducing signal distortions. This design methodology can eliminate the need for a power-hungry multi-stage limiting amplifier, hence significantly improving the power efficiency of LiDAR sensors. The practical implementation for this purpose is to insert a simple NMOS switch between the on-chip avalanche photodiode (APD) and the active feedback amplifier, which then can provide automatic on/off switching in response to variations of the input currents. In particular, the feedback resistor in the active feedback path should be carefully optimized to guarantee the circuit’s robustness and stability. To validate its practicality, the proposed CTLA chips were fabricated in a 180 nm CMOS process, demonstrating a transimpedance gain of 88.8 dBΩ, a −3 dB bandwidth of 629 MHz, a noise current spectral density of 2.31 pA/√Hz, an input dynamic range of 56.6 dB, and a power dissipation of 23.6 mW from a single 1.8 V supply. The chip core was realized within a compact area of 180 × 50 µm². The proposed CTLA shows a potential solution that is well-suited for power-efficient LiDAR sensor systems in real-world scenarios. Full article

In analyzing the decoupling of emissions from economic growth, current literature foregoes the nonlinear complexities of macroeconomic systems, leading to ineffective energy transition policies, specifically for developing countries. This study focuses on the Indian energy–economy–emission nexus to establish a control system that internalizes inflation, trade openness, and fossil fuel imports with economic growth and macro-emissions to visualize the complex pathways of decoupling. Through long-term cointegration and vector error correction modeling, it was found that GDP and energy affect capital, inflation and energy imports, which are locked in a long-run negative feedback loop that ultimately increases emissions. Capital growth enables decoupling at 0.7% CO₂ emissions reduction for every 1% capital growth, while 1% inflation growth inhibits decoupling by increasing CO₂ emissions by 0.8%. A cybernetic fractional circuit of R-C elements and operational amplifiers was utilized to examine the delay of pulses from GDP to the loop elements, which revealed that capital is periodic with GDP pulses. However, inflation, being aperiodic with the clock pulses of GDP, causes the pulse-width of capital to decrease and fossil fuel imports to increase. Through the circuital model, it was possible to determine the exact policy intervention schedule in business cycle growth and recession phases that could build clean energy capital and limit inflation-induced recoupling. Full article

This paper presents a novel optoelectronic transimpedance amplifier (OTA) for short-range LiDAR sensors used in 180 nm CMOS technology, which consists of a main transimpedance amplifier (m-TIA) with an on-chip P⁺/N-well/Deep N-well avalanche photodiode (P⁺/NW/DNW APD) and a replica TIA with another on-chip APD, not only to acquire circuit symmetry but to also obtain concurrent automatic gain control (AGC) function within a narrow single pulse-width duration. In particular, for concurrent AGC operations, 3-bit PMOS switches with series resistors are added in parallel with the passive feedback resistor in the m-TIA. Then, the PMOS switches can be turned on or off in accordance with the DC output voltage amplitudes of the replica TIA. The post-layout simulations reveal that the OTA extends the dynamic range up to 74.8 dB (i.e., 1 µA_pp~5.5 mA_pp) and achieves a 67 dBΩ transimpedance gain, an 830 MHz bandwidth, a 16 pA/$\surd \mathrm{Hz}$ noise current spectral density, a −31 dBm optical sensitivity for a 10⁻¹² bit error rate, and a 6 mW power dissipation from a single 1.8 V supply. The chip occupies a core area of 200 × 120 µm². Full article

Current Differencing Buffered Amplifiers (CDBAs) are a critical class of analog circuit components capable of handling both current and voltage signals with minimal power consumption. Due to their low impedance voltage output, they play a significant role in modern electronics for developing high-performance, high-precision analog and mixed-signal circuits. But, designing and characterizing CDBAs pose several challenges, such as ensuring stability at high frequencies, minimizing noise impact for high-precision applications, and enhancing adaptability. Integrating CDBAs with other analog components to create multifunctional integrated circuits opens many opportunities in the analog signal-processing domain. This paper reviews the evolution and applications of CDBAs in analog signal processing. Various implementation schemes, including those using commercial Current Feedback Amplifiers (CFAs) and novel CMOS configurations, are analyzed for their performance metrics such as supply voltage, power dissipation, input/output impedances, and technology node. Future trends and challenges in advancing CDBA technology towards higher integration and lower-voltage operation are discussed, highlighting potential applications in next-generation electronics. Full article

A direct bidirectional current discharge path between the input/output (I/O) and ground (GND) is essential for the robust protection of charging device models (CDM) in the tightly constrained design parameters of advanced low-voltage (LV) processes. Dual-direction silicon controlled rectifiers (DDSCRs) serve as ESD protection devices with high efficiency unit area discharge, enabling bidirectional electrostatic protection. However, the high trigger voltage of conventional DDSCR makes it unsuitable for ASICs used for the preamplification of biomedical signals, which only operate at low supply voltage. To address this issue, a self-biased triggered DDSCR (STDDSCR) structure is proposed to further reduce the trigger voltage. When the ESD pulse comes, the external RC trigger circuit controls the PMOS turn-on by self-bias, and the current release path is opened in advance to reduce the trigger voltage. As the ESD pulse voltage increases, the SCR loop opens to establish positive feedback and drain the amplified current. Additionally, the junction capacitance is decreased through high-resistance epitaxy and low-concentration P-well injection to further lower the trigger voltage. The simulation results of LTspice and TCAD respectively demonstrate that ESD devices can clamp transient high voltages earlier, with low parasitic capacitance and leakage current suitable for ESD protection of high-speed ports up to 1.5 V under normal operating conditions. Full article

A lightning current measurement method using a Rogowski coil based on an integral circuit with low-frequency attenuation feedback was proposed to address the issue of low-frequency distortion in the measurement of lightning currents on transmission lines using Rogowski coils. Firstly, the causes of low-frequency distortion in lightning current measurements using Rogowski coils were analyzed from the perspective of frequency domains. On this basis, an integration correction optimization circuit with a low-frequency attenuation feedback network was designed to correct the low-frequency distortion. The optimized integration circuit can also reduce the impact of low-frequency noise and the DC bias of the operational amplifier (op-amp) on the integration circuit due to the high low-frequency gain. Additionally, a high-pass filtering and voltage-divided sampling circuit has been added to ensure the normal operation of the integrator and improve the measurement range of the measurement system. Then, according to the relationship between the amplitude–frequency characteristics of the measurement system and the parameters of each component, the appropriate types of components and op-amp were selected to expand the measurement bandwidth. Finally, a simulation verification was conducted, and the simulation results show that this measurement method can effectively expand the lower measurement frequency limit to 20 Hz, correct the low-frequency distortion caused by Rogowski coils measuring lightning currents on transmission lines, and accurately restore the measured lightning current waveform. Full article

An approach to design analog building blocks based on digital standard cells is presented in this work. By ensuring that every CMOS inverter from a standard-cell library operates with a well-defined quiescent current and output voltage, the suggested method makes it possible to construct analog circuits that are resistant against PVT variations. The method uses the local supply voltages connected to the source terminals of the p-channel and n-channel MOS transistors of the standard-cell inverters as control inputs. It is based on adaptive supply voltage generator (ASVG) reusable blocks, which are comparable to those used in digital applications to handle process variations. All of the standard-cell inverters used for analog functions receive the local supply voltages produced by the ASVGs, which enable setting each cell’s quiescent current to a multiple of a reference current and each cell’s static output voltage to an appropriate reference voltage. Both the complete custom design of the ASVG blocks and a theoretical study of the feedback loop of the ASVG are presented. An application example through the design of a fully synthesizable two-stage operational transconductance amplifier (OTA) is also provided. The TSMC 180 nm CMOS technology has been used to implement both the OTA and the ASV generators. Simulation results have demonstrated that the proposed approach allows to accurately set the quiescent current of standard-cell inverters, dramatically reducing the effect of PVT variations on the pmain performance parameters of the standard-cell-based two-stage OTA. Full article

This paper presents an inverter-based active feedback transimpedance amplifier (IAF-TIA), in which an active feedback is applied to a voltage-mode inverter-based TIA, and therefore, the controlled positive regeneration process enables the proposed IAF-TIA to achieve the limiting operations for input currents greater than 100 μA_pp. However, the active inverter feedback mechanism might be prone to instability, hence mandating a very careful optimization of the loop gain. For this purpose, a diode-connected NMOS transistor is employed as a switch in the feedback path with its gate connected to the input, which helps not only to mitigate the corresponding issue but also to accommodate large input currents up to 1.5 mA_pp. The proposed IAF-TIA implemented in a standard 180 nm CMOS process demonstrates a 70.5 dBΩ transimpedance gain, 1.21 GHz bandwidth, 4.3$\mathrm{pA}/\sqrt{\mathrm{Hz}}$ noise current spectral density, 63.5 dB input dynamic range, and 23.6 mW power dissipation from a single 1.8 V supply. The chip core occupies an area of 180 × 50 μm², including an on-chip P⁺/N-well/Deep N-well avalanche photodiode as an optical detector. Full article

The design of a mixed-mode proportional-integral-derivative (PID) controller circuit using current-feedback operational amplifiers (CFOAs) as active components is proposed. With the same circuit topology, the proposed configuration of three CFOAs, four resistors, and two capacitors is capable of performing the PID controller in each of the following four modes: voltage mode, trans-admittance mode, current mode, and trans-impedance mode. Numerous mathematical analyses are conducted to determine the controller’s performance under both ideal and non-ideal conditions. Additionally, the mixed-mode second-order lowpass filter is suggested and also used to examine the workability of the proposed mixed-mode PID controller in a feedback control structure. The proposed PID controller is implemented with the commercially available IC-type CFOA AD844, and the simulation results are presented to illustrate the functionality of the controller and its closed-loop control system. According to the findings, the total power consumption of the proposed PID controller is 0.348 W, with symmetrical supply voltages of ±9 V. It also has a temperature variation of less than 0.2% over the AD844’s usable range. Monte Carlo statistical analysis results revealed that the gain responses of the controller exhibited a deviation of no more than 7.72% from the theoretical value. The controlled filter in a closed-loop control system has a 43% faster rise time and peak time than the uncontrolled filter in all four modes of operation. It also has a steady-state error less than 0.2 mV for voltage responses and 0.72 µA for current responses. Full article