Search Results (29)

This paper presents an optimized 868 MHz low-noise amplifier (LNA) based on a bipolar junction transistor (BJT), specifically designed for wake-up receivers operating in the sub-GHz band. The proposed LNA achieves low noise, high gain, and good impedance matching while consuming only $3.2$ mA from a $3.3$ V supply, resulting in a total power consumption of $10.56$ mW. Designing efficient sub-GHz LNAs for low-power applications involves a careful balance between multiple performance metrics. Higher gain typically requires increased biasing current, which can raise power consumption, while achieving a low noise figure often conflicts with input-matching constraints. The presented design addresses these trade-offs by leveraging the BFP740 BJT and employing a stub-based microstrip matching network to simultaneously optimize the gain, noise figure, and input–output matching. Simulation results, using both external lumped elements and microstrip techniques, show a forward gain ($S_{21}$) of $15.2$ dB at 868 MHz, with an input reflection coefficient ($S_{11}$) of $-6.9$ dB and an output reflection coefficient ($S_{22}$) of $-6.3$ dB. The amplifier achieves a minimum noise figure of approximately $1.77$ dB, which is notably low for this frequency band. These results demonstrate that the proposed LNA offers a compact, energy-efficient, and cost-effective solution, ideally suited for always-on, low-power wireless applications such as Internet of Things (IoT) devices and wireless sensor networks. Full article

This study systematically investigates the electrical characteristics of the vertical NPN bipolar junction transistor (VNPN BJT) in the strong magnetic field environment, focusing on analyzing the effects of magnetic field direction and intensity on key parameters such as terminal current and current gain (β). The simulation results show that the magnetic field induces changes in the carrier distribution, thereby affecting the current transport path. Through the in-depth analysis of electron motion trajectories, potential distribution, and Hall voltage, this paper reveals the physical mechanisms behind the device’s characteristic changes under the magnetic field and discovers that the inherent asymmetry of the BJT structure induces significant magnetic anisotropy effects. On this basis, a design for interference-resistant structures in strong magnetic field environments is proposed, effectively suppressing the adverse effects of magnetic-field-sensitive directions on BJT performance and significantly improving the device’s stability in complex magnetic field environments. Full article

Semiconductor radiation detectors usually use a specific signal conditioning circuit, ensuring the required detection system parameters. This paper details the noise properties of specific input stages in photoreceivers that detect various types of radiation. For this purpose, the popular silicon PIN photodiode (BPW34) and two different types of low-noise operational amplifiers (AD797A and ADA4625-1) were used. In the presented experiments, noise measurements were provided for voltage and transimpedance amplifiers operating in input stages, comparing their noise and bandwidths. This made it possible to obtain results for bipolar junction transistor (BJT)- and field-effect transistor (FET)-based input stages of circuity, cooperating directly with a photodiode. Analyzing the obtained characteristics and considering the photodiode operation mode, it is evident that the transimpedance amplifier and photoconductive mode should be considered a typical first-choice solution. In some cases, the performances, such as bandwidth and noise, may be similar to those of voltage. Nevertheless, the bias method used in TIA and feedback compensation can also affect the resulting output noise spectral characteristics due to the photodiode and other capacitances existing in the circuit. In the case of a high transimpedance, the FET-based op-amps ensure lower output noise than the BJT-based ones due to the significantly lower current noise. The simple radiation detector with two-channel differential TIA was also proposed and tested based on the results obtained. Full article

This work develops a novel compact Silicon-Controlled Rectifier (SCR) model incorporating self-heating effects, extending the conventional Ebers–Moll (E–M) framework for Bipolar Junction Transistors (BJTs) by comprehensively integrating parasitic effects. The temperature dependence of critical device parameters, including junction capacitances, emitter resistances, and saturation currents, is systematically characterized to accurately predict the device’s electrical behavior under Electrostatic Discharge (ESD) stress. Furthermore, a self-heating modeling approach is introduced based on the SCR layout characteristics. The impact of self-heating on SCR transient response was verified by comparing simulation results with measurements from SCR devices fabricated in a 0.18 µm Bipolar-CMOS-DMOS (BCD) process. Comparative analysis demonstrates superior accuracy over existing models. The proposed SCR model includes a complete definition of parameters and electrical relationships, ensuring compatibility with various Electronic Design Automation (EDA) platforms. Full article

Two-dimensional layered materials, characterized by their atomically thin thicknesses and surfaces that are free of dangling bonds, hold great promise for fabricating ultrathin, lightweight, and flexible bipolar junction transistors (BJTs). In this paper, a van der Waals (vdW) BJT was fabricated by vertically stacking MoS₂, WSe₂, and MoS₂ flakes in sequence. The AC characteristics of the vdW BJT were studied for the first time, in which a maximum common emitter voltage gain of around 3.5 was observed. By investigating the time domain characteristics of the device under various operating frequencies, the frequency response of the device was summarized, which experimentally proved that the MoS₂/WSe₂/MoS₂ BJT has voltage amplification capability in the 0–200 Hz region. In addition, the phase response of the device was also investigated. A phase inversion was observed in the low-frequency range. As the operating frequency increases, the relative phase between the input and output signals gradually shifts until it is in phase at frequencies exceeding 2.3 kHz. This work demonstrates the signal amplification applications of the vdW BJTs for neuromorphic computing and wearable healthcare devices. Full article

Two-dimensional (2D) materials have attracted great attention in the past few years and offer new opportunities for the development of high-performance and multifunctional bipolar junction transistors (BJTs). Here, a van der Waals BJT based on vertically stacked n⁺-MoS₂/WSe₂/MoS₂ was demonstrated. The electrical performance of the device was investigated under common-base and common-emitter configurations, which show relatively large current gains of α ≈ 0.98 and β ≈ 225. In addition, the breakdown characteristics of the vertically stacked n⁺-MoS₂/WSe₂/MoS₂ BJT were investigated. An open-emitter base-collector breakdown voltage (BV_CBO) of 52.9 V and an open-base collector-emitter breakdown voltage (BV_CEO) of 40.3 V were observed under a room-temperature condition. With the increase in the operating temperature, both BV_CBO and BV_CEO increased. This study demonstrates a promising way to obtain 2D-material-based BJT with high current gains and provides a deep insight into the breakdown characteristics of the device, which may promote the applications of van der Waals BJTs in the fields of integrated circuits. Full article

This paper presents a bandgap reference (BGR) with high-order temperature-segmented compensation. The compensation signal is generated using the voltage difference between two bipolar junction transistor (BJT) emitter bases, each of which individually loads a proportional-to-absolute temperature (PTAT) current and a zero-to-absolute temperature (ZTAT) current. The proposed BGR achieves a low-temperature coefficient (TC) over a wide temperature range. Simulations using the 0.18 μm Bipolar-CMOS-DMOS process show a typical TC of 2.25 ppm/°C from −40 °C to 125 °C. With an active area of 0.07986 mm², it consumes 36 μW power under an operating voltage of 1 V. The integrated output noise from 0.1 Hz to 10 Hz is 81.1 μV. Full article

This paper introduces a new design of silicon nanowire (Si NW) phototransistor (PT) arrays conceived explicitly for improved CMOS image sensor performance, and comprehensive numerical investigations clarify the characteristics of the proposed devices. Each unit within this array architecture features a top-layer vertical Si NW optimized for the maximal absorption of incoming light across the visible spectrum. This absorbed light generates carriers, efficiently injected into the emitter–base junction of an underlying npn bipolar junction transistor (BJT). This process induces proficient amplification of the output collector current. By meticulously adjusting the diameters of the NWs, the PTs are tailored to exhibit distinct absorption characteristics, thus delineating the visible spectrum’s blue, green, and red regions. This specialization ensures enriched color fidelity, a sought-after trait in imaging devices. Notably, the synergetic combination of the Si NW and the BJT augments the electrical response under illumination, boasting a quantum efficiency exceeding 10. In addition, by refining parameters like the height of the NW and gradient doping depth, the proposed PTs deliver enhanced color purity and amplified output currents. Full article

Image sensors such as single-photon avalanched diode (SPAD) arrays typically adopt in-pixel quenching and readout circuits, and the under-illumination first-stage readout circuits often employs high-threshold input/output (I/O) or thick-oxide metal-oxide-semiconductor field-effect transistors (MOSFETs). We have observed reliability issues with high-threshold n-channel MOSFETs when they are exposed to strong visible light. The specific stress conditions have been applied to observe the drain current (I_d) variations as a function of gate voltage. The experimental results indicate that photo-induced hot electrons generate interface trap states, leading to I_d degradation including increased off-state current (I_off) and decreased on-state current (I_on). The increased I_off further activates parasitic bipolar junction transistors (BJT). This reliability issue can be avoided by forming an inversion layer in the channel under appropriate bias conditions or by reducing the incident photon energy. Full article

Silicon (Si)-based semiconductor devices have long dominated the power electronics industry and are used in almost every application involving power conversion. Examples of these include metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), gate turn-off (GTO), thyristors, and bipolar junction transistor (BJTs). However, for many applications, power device requirements such as higher blocking voltage capability, higher switching frequencies, lower switching losses, higher temperature withstand, higher power density in power converters, and enhanced efficiency and reliability have reached a stage where the present Si-based power devices cannot cope with the growing demand and would usually require large, costly cooling systems and output filters to meet the requirements of the application. Wide bandgap (WBG) power semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), and diamond (Dia) have recently emerged in the commercial market, with superior material properties that promise substantial performance improvements and are expected to gradually replace the traditional Si-based devices in various power electronics applications. WBG power devices can significantly improve the efficiency of power electronic converters by reducing losses and making power conversion devices smaller in size and weight. The aim of this paper is to highlight the technical and market potential of WBG semiconductors. A detailed short-term and long-term analysis is presented in terms of cost, energy impact, size, and efficiency improvement in various applications, including motor drives, automotive, data centers, aerospace, power systems, distributed energy systems, and consumer electronics. In addition, the paper highlights the benefits of WBG semiconductors in power conversion applications by considering the current and future market trends. Full article

In this work, the effects of total dose irradiation on the parasitic bipolar junction transistor (BTJ) in 130 nm PDSOI MOSFETs were investigated. The experimental results demonstrate that irradiation-induced oxide-trap charges can modify the E-B junction barrier, and thereby make the common-emitter gain ${\beta }_0$ of the parasitic BJT in NMOS device increase, while decreasing it in a PMOS device. Additionally, irradiation-generated oxide-trap charges in shallow trench isolation (STI) elevate the surface electrostatic potential of the gate above the STI sidewall, thus providing an additional channel from the emitter to the collector. Moreover, these charges may generate parasitic reverse conductive paths at the STI/Si interface under high dose irradiation, thereby enhancing the leakage current in the front gate channel and diminishing the significance of the parasitic BJT. Under irradiation, the electric field intensity difference between two biases leads to higher ${\beta }_0$ of the parasitic BJT in PG-biased devices than in ON-biased ones. Furthermore, the lifting effect of irradiation on ${\beta }_0$ increases in wide or short channel irradiated devices, which can be explained using simulations and an emitter current crowding effect model. Full article

A new precision-aware subthreshold-based MOSFET voltage reference is presented in this paper. The circuit was implemented TSMC−40 nm process technology. It consumed 9.6 $\mathsf{\mu }\mathrm{W}$ at the supply voltage of 1.2 V. In this proposed work, by utilizing subthreshold-based MOSFET instead of bipolar junction transistor (BJT), relatively lower power consumption was obtained in the design while offering comparable precision to that offered by its BJT counterpart. Through the proposed second-order compensation, it achieved the temperature coefficient (T.C.) of 3.0 ppm/$°C$ in the TT corner case and a 200-sample Monte-Carlo T.C. of 12.51 ppm/$°C$ from −40 $°C$ to 90 $°C$. This shows robust temperature insensitivity. The process sensitivity of $V_{ref}$ without and with trimming was 2.85% and 0.75%, respectively. The power supply rejection (PSR) was 71.65 dB at 100 Hz and 52.54 dB at 10 MHz. The Figure-of-Merit (FOM) for the total variation in output voltage was comparable with representative BJT circuits and better than subthreshold-based MOSFET circuits. Due to low T.C., low process sensitivity, and simplicity of the circuit architecture, the proposed work will be useful for sensor circuits with stringent requirements or other analog circuits that require high precision applications. Full article

This work aims to evaluate the possibility of fabricating conductive paths for printed circuit boards from low-temperature melting metal alloys on low-temperature 3D printed substrates and mounting through-hole electronic components using the fused deposition modeling for metals (FDMm) for structural electronics applications. The conductive materials are flux-cored solder wires Sn60Pb40 and Sn99Ag0.3Cu0.7. The deposition was achieved with a specially adapted nozzle. A comparison of solder wires with and without flux cores is discussed to determine whether the solder alloys exhibit adequate wettability and adhesion to the polymer substrate. The symmetrical astable multivibrator circuit based on bipolar junction transistors (BJT) was fabricated to demonstrate the possibility of simultaneous production of conductive tracks and through-hole mountings with this additive technique. Additional perspectives for applying this technique to 3D-printed structural electronic circuits are also discussed. Full article

In this paper, a novel super-junction trench silicon-on-insulator laterally-diffused metal-oxide-semiconductor (SJT SOI LDMOS) power device with additional hole leakage paths to improve single-event burnout (SEB) performance under high liner energy transfer (LET) is proposed for the first time. The electrical characteristics and SEB performance of the proposed SJT SOI LDMOS are both enhanced effectively. The replacement of a lightly doped N drift region with a heavily doped P pillar and N pillar considerably improves the tradeoff between breakdown voltage (BV_DS) and specific on-resistance (R_on,sp). Compared with the conventional trench SOI LDMOS (CT SOI LDMOS), the static figures of merit (FOM, BV_DS²/R_on,sp) of the SJT SOI LDMOS increases by 239%. The SEB performance of the SJT SOI LDMOS is significantly improved as the holes induced by the heavy ion can be quickly absorbed to the trench source metal through the heavily doped P+ region and P buried region rather than the base resistor of the parasitic bipolar junction transistor (BJT). The SEB threshold voltage (V_SEB) of the CT SOI LDMOS is 58 V (39% of the BV_DS) and that of the SJT SOI LDMOS is up to 173 V (87% of the BV_DS) at high LET of 1 pC/μm. Full article

High switching-speed Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistor (SiC MOSFET) has serious crosstalk issues. During the turn-ON transition and turn-OFF transition of the active switch in a phase-leg configuration, the voltage drops across the common-source inductor and the displacement current of the gate-drain capacitor of the OFF-state switch induce a spurious pulse on its gate-source voltage. This paper proposes a new gate driver using two Bipolar Junction Transistors (BJTs) and one diode to connect the gate terminal of SiC MOSFET and the negative driver voltage, which provides a low impedance path to bypass the displacement current of the gate-drain capacitor when crosstalk issues occur. The simulation results prove the proposed driver is valid on suppressing the crosstalk issue. The comparisons between the prior drivers and the proposed driver show the superiority of the proposed driver. Finally, the proposed gate driver is successfully implemented and experimentally verified on a 1.1 kW synchronous buck prototype. Full article