A Compact Model with Self-Heating Effect Applying to the SCR Device for ESD Protection

Abstract

This work develops a novel compact Silicon-Controlled Rectifier (SCR) model incorporating self-heating effects, extending the conventional Ebers–Moll (E–M) framework for Bipolar Junction Transistors (BJTs) by comprehensively integrating parasitic effects. The temperature dependence of critical device parameters, including junction capacitances, emitter resistances, and saturation currents, is systematically characterized to accurately predict the device’s electrical behavior under Electrostatic Discharge (ESD) stress. Furthermore, a self-heating modeling approach is introduced based on the SCR layout characteristics. The impact of self-heating on SCR transient response was verified by comparing simulation results with measurements from SCR devices fabricated in a 0.18 µm Bipolar-CMOS-DMOS (BCD) process. Comparative analysis demonstrates superior accuracy over existing models. The proposed SCR model includes a complete definition of parameters and electrical relationships, ensuring compatibility with various Electronic Design Automation (EDA) platforms.

1. Introduction

Owing to the high fabrication and measurement cost of the Integrated Circuits (ICs), the design and simulation of ICs’ electrical performance are becoming increasingly important in reducing the development time and cost. Simulation Program with Integrated Circuit Emphasis (SPICE) models are well established for conventional IC simulation, while system-level simulation that includes Electrostatic Discharge (ESD) protection devices has not been fully developed. Traditional ESD protection structures, including Bipolar Junction Transistors (BJTs), Gate-Grounded N-type MOS (GGNMOS), and diodes, are commonly modeled using standard model libraries provided by a foundry. These models provide accurate results for low-current operations but fail to represent the complex behaviors under ESD stress. With the quick development of the ICs’ fabrication process and electrical performance, those conventional ESD protection devices cannot meet the requirements of advanced ICs, due to the large area and weak ESD robustness. The Silicon-Controlled Rectifier (SCR) shows significant potential as an alternative ESD protection structure, due to its superior ESD robustness and area efficiency [1,2,3].

The SCR comprised coupled PNP and NPN BJTs in electrical characteristics; the electrical models of SCR suited for evaluating the large current discharge behavior resulted from the avalanche effect. Several SCR modeling approaches have been reported in the literature. An improved compact model compatible with industry-standard SPICE was proposed [4], but lacked comprehensive system-level simulation capabilities. A scalable SCR compact model [5] considered layout spacing and self-heating effects, but simulations of its snapback characteristics showed limited accuracy. The exist SCR models, including the parameter-efficient CMOS-SCR compact model [6] and the simplified physics-based model [7], have addressed simulation accuracy and convergence issues, respectively. However they fail to accurately capture the electrical performance variations caused by self-heating effects under ESD stress [8].

Despite attempts to incorporate complex physical models for parasitic effects, temperature-dependent variations in key device parameters (turn-on resistance, junction capacitance, and leakage current) remain for a challenge to modeling SCR device accurately. Although chip-level electro-thermal simulators that construct detailed 3D thermal networks can effectively analyze temperature profiles and hot spots, this approach involves extensive integration calculations [9,10]. These calculations impose unnecessary burdens for self-heating analysis of single-device ESD protection circuits and may introduce convergence issues in simulations. Such modeling methods are more suited for VLSI chip evaluations than for device-level ESD protection circuits. In some power device modeling studies, the impact of both environmental and internal device temperatures on heat dissipation efficiency has been considered [11,12,13]. This enhances the model’s accuracy in characterizing temperature variations within the device. However, these models lack an analysis of temperature-dependent parasitic parameters, making the influence of self-heating effects on the device’s electrical characteristics less apparent. Using a Cauer ladder thermal equivalent circuit to represent the temperature variations caused by self-heating effects within ESD protection devices has proven to be a viable approach [14,15]. However, further research is needed on the extraction of thermal capacitance and resistance of SCR devices, as well as how to effectively characterize the impact of self-heating on the electrical characteristics of SCRs. Using Technology Computer-Aided Design (TCAD) simulations to analyze the electrical characteristics of ESD protection devices has proven to be an excellent approach [16,17,18], yielding remarkable results. This method provides new insights and feasible strategies for further investigating the physical behaviors of ESD protection devices.

To more accurately describe the impact of self-heating effects on the electrical performance of SCRs and better predict their behavior under ESD stress, a compact SCR model incorporating self-heating effects is proposed. This model is based on a Cauer ladder thermal equivalent circuit, with thermal capacitance and thermal resistance parameters extracted from the SCR’s layout based on TCAD simulation results. It precisely simulates the lattice temperature variations caused by self-heating in the SCR, and temperature-sensitive physical parameters—including emitter resistance, junction capacitance, and reverse saturation current—are represented as functions of temperature to characterize the impact of self-heating on SCR electrical properties. This approach addresses the absence of proprietary self-heating models for SCR devices in earlier studies. Furthermore, the model is achieved using Verilog-A hardware description language, describing the coupling between SCR self-heating and electrical effects through loop algorithms. The simulation results obtained from SPICE demonstrate good agreement with experimental measurements, verifying the model’s accuracy in predicting the electrical characteristics of SCR devices.

2. Model Description

2.1. Silicon-Controlled Rectifier (SCR) Compact Model

Traditional SCR models feature a pair of mutually coupled transistors ($T_{pnp}$ and $T_{npn}$) and two linear well resistors ($R_{nw}$ and $R_{pw}$) that provide bias to represent the equivalent circuit characteristics, as depicted in Figure 1. Although this simplified model is applicable under small-signal conditions, it fails to accurately capture the complex physical behaviors of the SCR under actual operating conditions. Especially when under ESD stress, the traditional SCR models (such as Ebers–Moll (E–M) and Gummel–Poon (G–P) models) are inadequate in reflecting nonlinear properties, including avalanche effects in the N-well/P-well regions and self-heating effects. The Vertical Bipolar Inter-Company (VBIC) transistor model can provide relevant nonlinear analysis but focuses on the I–V characteristics of individual transistors, making it unsuitable for describing the complex electro-thermal coupling within the SCR.

Based on the aforementioned analysis, an improved transistor E–M model is proposed to describe SCR devices. As illustrated in Figure 2, the model introduces forward diodes $D_{ep}$, $D_{en}$, and reverse diode $D_r$, along with voltage-controlled current sources $I_{linkp}$ and $I_{linkn}$, forming a typical transistor EM coupled current transmission model. In addition, an avalanche current source $I_{av}$ is used to describe the avalanche breakdown characteristics at the N-well/P-well reverse-biased junction when the electric field intensity reaches a critical value. Nonlinear resistances $R_{cp}$, $R_{cn}$, $R_{ep},$ and $R_{en}$ are introduced to characterize the conductivity modulation and self-heating effects induced by large current injection under ESD stress. Moreover, the model includes parasitic capacitance modeling, which significantly impacts the SCR’s transient response. For the forward-biased p-n junctions at P+/N-well and P-well/N+, only the dominant diffusion capacitances $C_{ep}$ and $C_{en}$, are considered. For the reverse-biased N-well/P-well junction, the parasitic capacitance is represented by the diffusion capacitance $C_r$ and the junction capacitance $C_j$.

The currents flowing through the forward diode $D_{ep}$, the reverse diode $D_r$, and the voltage-controlled current source $I_{linkp}$ are given by Equations (1)–(3), as follows [5]:

$$I_{D_{ep}}={\displaystyle \frac{I_S}{{\beta }_f}}\left[exp\left({\displaystyle \frac{V_{ep}}{V_T}}\right)-1\right]$$

(1)

$$I_{D_r}={\displaystyle \frac{I_S}{{\beta }_r}}\left[exp\left({\displaystyle \frac{V_r}{V_T}}\right)-1\right]$$

(2)

$$I_{linkp}=I_S\left[exp\left({\displaystyle \frac{V_{ep}}{V_T}}\right)-\left({\displaystyle \frac{V_r}{V_T}}\right)\right]$$

(3)

where $I_S$ is the reverse saturation current, $V_T$ is the thermal voltage, and ${\beta }_f$ and ${\beta }_r$ are the forward and reverse gains of the transistor, respectively, which are taken as constants. $V_{ep}$ and $V_r$ are the voltage drops across the forward diode $D_{ep}$ and the reverse diode $D_r$, respectively. The equations for the diode $D_{en}$ and the voltage-controlled current source $I_{linkn}$ are similar to those for $D_{ep}$ and $I_{linkp}$, respectively.

The avalanche current source $I_{Av}$ is modeled using a piecewise function. When the voltage is lower than the critical breakdown voltage, the avalanche current is described by the equation shown in Equation (4). When the voltage exceeds the critical breakdown voltage, a linear equation, as shown in Equation (5), is used to avoid convergence issues [7,19].

$$I_{Av}=\left(I_S+I_{linkn}+I_{linkp}\right)\ast \left({\displaystyle \frac{1}{1-{\left(\frac{V_r}{V_B}\right)}^S}}-1\right)$$

(4)

$$I_{Av}=\left(I_S+I_{linkn}+I_{linkp}\right)\ast \left({\displaystyle \frac{1}{1-k^S}}-1\right)+{\displaystyle \frac{V_r-k\ast V_B}{R_k}}$$

(5)

where $V_B$ is the critical breakdown voltage, $S$ is a constant related to the physical properties of semiconductor material, the value of $k$ is close to 1 to ensure that breakdown occurs near the threshold, and $R_k$ is the differential resistance near the breakdown voltage.

The expression for the collector resistance $R_{cp}$ is given by Equation (6), as shown below [7,20]:

$$R_{cp}={\displaystyle \frac{R_{c0}}{1+\frac{Q_D}{Q_{D0}}}}$$

(6)

where $R_{c0}$ is the resistance value at zero bias, $Q_{D0}$ is the threshold charge, and $Q_D$ is the number of charge injected into the N-well/P-well junction, which can be expressed by Equation (7):

$$Q_D=I_S{\tau }_r\left[exp\left({\displaystyle \frac{V_r}{V_T}}\right)-1\right]$$

(7)

where ${\tau }_r$ is the transit time of the N-well/P-well junction. The equation for the collector resistance $R_{cn}$ is similar to that for $R_{cp}$.

The currents flowing through the diffusion capacitors $C_{ep}$ and $C_r$ are given by Equations (8) and (9), as shown below [5]:

$$I_{C_{ep}}={\displaystyle \frac{d}{dt}}\left[I_S{\tau }_f\left[exp\left({\displaystyle \frac{V_{ep}}{V_T}}\right)-1\right]\right]$$

(8)

$$I_{C_r}={\displaystyle \frac{d}{dt}}\left[I_S{\tau }_r\left[exp\left({\displaystyle \frac{V_r}{V_T}}\right)-1\right]\right]$$

(9)

where ${\tau }_f$ and ${\tau }_r$ are the forward and reverse transit times, respectively. The equation for the diffusion capacitance $C_{en}$ is similar to that for $C_{ep}$.

In addition to the description of the electrical characteristics mentioned above, this study focused on the impact of self-heating effects on the electrical properties of SCRs. Under ESD stress, the power dissipation of the device causes an increase in lattice temperature, which triggers a series of temperature-dependent effects. This temperature dependence primarily manifests in the deviation of physical quantities, such as emitter resistance, junction capacitance, and reverse saturation current, from their initial values as temperature changes, significantly affecting the SCR’s electrical characteristics. Among these, the temperature dependence of the emitter resistance $R_{ep}$ can be described by Equation (10) as follows [21,22]:

$$R_{ep}=R_{e0}{\left(1+{\displaystyle \frac{T-T_0}{T_0}}\right)}^{\chi }$$

(10)

where $R_{e0}$ represents the standard resistance value at room temperature, and $\chi$ is the temperature-dependent exponent. $T$ is the current temperature and $T_0$ is the initial temperature (ambient temperature), with $T$ values derived from the self-heating model. The equation for the emitter resistance $R_{en}$ is similar to that for $R_{ep}$. When increasing temperature, the enhanced carrier–lattice scattering in heavily doped emitter regions of SCR reduces carrier mobility, resulting in a super-linear growth in resistance. This nonlinear characteristic becomes particularly significant under high-current injection conditions, representing a critical physical phenomenon that conventional linear models fail to accurately describe.

The temperature dependence of junction capacitance $C_j$ involves complex physical mechanisms. The capacitance is primarily constrained by the width of the depletion region, and its temperature dependence can be expressed as follows [22]:

$$C_j=C_{j0}\left[1+m\left(A\left(T-T_0\right)-{\displaystyle \frac{{\phi -\phi }_0}{{\phi }_0}}\right)\right]$$

(11)

where $C_{j0}$ represents the junction capacitance at room temperature, $m$ is the temperature coefficient, $A$ is a fitting parameter set to 4 × 10⁻⁴, and $\phi$ is the built-in potential, which is inversely proportional to temperature. ${\phi }_0$ is the initial built-in potential. The equation describes two fundamental mechanisms of how temperature affects the junction capacitance. As temperature increases, the intrinsic carrier concentration rises, enhancing the screening effect of the carriers on the electric field in the depletion region. Simultaneously, the increase in temperature reduces the semiconductor bandgap, thereby decreasing the built-in potential. Both effects lead to a narrowing of the depletion region, which in turn reduces the junction capacitance. The combined influence of these mechanisms determines the temperature-dependent behavior of the junction capacitance.

Apart from the effects on $R_{ep}$, $R_{en}$, and $C_j$, temperature significantly influences the reverse saturation current. When temperature increases, enhanced thermal generation enables more carriers to overcome the bandgap, intensifying the carrier generation-recombination processes. This temperature-dependent behavior can be expressed by the following equation [22,23]:

$$I_S=I_{S0}\ast {\left({\displaystyle \frac{T}{T_0}}\right)}^{{\displaystyle \frac{X_{TI}}{n}}}\ast exp\left[-{\displaystyle \frac{E_{G0}}{nkT}}\left(1-{\displaystyle \frac{T}{T_0}}\right)\right]$$

(12)

$X_{TI}$ represents the temperature exponent factor, $n$ is the ideality factor, and $E_{G0}$ denotes the bandgap width at room temperature. The equation accurately describes the mechanism by which temperature influences the reverse saturation current. Specifically, the term ${\left(\frac{T}{T_0}\right)}^{\frac{X_{TI}}{n}}$ characterizes the variation in carrier concentration with temperature, while the exponential term $exp\left[-\frac{E_{G0}}{nkT}\left(1-\frac{T}{T_0}\right)\right]$ reflects the impact of temperature on the carrier generation and recombination processes. This dual temperature dependence indicates that increased temperature substantially enhances carrier generation, resulting in strongly nonlinear characteristics of reverse saturation current.

The equation described above allows the model, as shown in Figure 2, to accurately capture the electro-thermal coupling within the SCR. This multi-physics coupling modeling approach significantly enhances the model’s accuracy under ESD stress conditions, demonstrating particular advantages in predicting device behavior under high-current injections. The parameters used in the compact model are listed in

Table 1. Reference values of parameters for the compact model.

Parameters [Unit]	Values	Parameters [Unit]	Values
$R_{nw}$ [Ω]	500	$E_{G0}$ [eV]	1.16
$R_{pw}$ [Ω]	500	${\beta }_f$	2
$R_{c0}$ [Ω]	98	${\beta }_r$	1
$R_{e0}$ [Ω]	0.45	${\tau }_f$	1 × 10−9
$Q_{D0}$ [C]	3.95 × 10−10	${\tau }_r$	5 × 10−8
$C_{j0}$ [F]	3.09 × 10−13	$S$	3
$I_{S0}$ [A]	0.9 × 10−13	$k$	0.99
$V_B$ [V]	14.2	$m$	1
$T_0$ [K]	300	$A$	4 × 10−4
$V_T$ [V]	0.026	$X_{TI}$	3
$R_k$ [Ω]	0.01	$n$	1.3

for reference; all parameter values are obtained from relevant process manuals or fitted using tested results.

2.2. SCR Self-Heating Model

Based on the previously described physical models, a self-heating model is developed to accurately characterize the impact of lattice temperature rise on SCR device characteristics. A novel self-heating modeling approach is proposed considering the specific SCR structure.

To precisely model the temperature distribution characteristics of SCR devices under ESD stress, 3D-TCAD simulations were conducted according to the SCR layout structure, as illustrated in Figure 3a. The SCR length is set to 8 µm, and the width is 100 µm (Since the device width is linearly proportional to the overcurrent capability, the width was scaled down by a factor of 10 during the simulation to improve computational speed, resulting in a simulated width of 10 µm). The diffusion depth of the lattice temperature is approximately 4 µm, and this portion is analyzed.

Cross-sectional analyses were performed along the A–A1 and B–B1 directions depicted in Figure 3a. Figure 3b presents the temperature distribution profile along the A–A1 direction, clearly showing that the highest temperature region is located near the N-well/P-well junction, exhibiting distinct radial diffusion characteristics. This distribution pattern corresponds with the current concentration effect observed under ESD stress, reflecting the local hotspot phenomena induced by carrier injection. Figure 3c illustrates the temperature distribution along the B–B1 direction, revealing the lateral diffusion of heat. Based on the temperature gradient distribution characteristics, the SCR device is segmented into three distinct regions: Region 1, the central hotspot area with the highest temperature and steepest gradient; Region 2, the transitional area with moderate temperature and gradual gradient change; Region 3, the peripheral area with lower temperature approaching ambient conditions.

TCAD simulation results suggest that the heat dissipation region can be approximated as a semi-cylindrical space, as illustrated in Figure 4a. The region with radius $r_1$ corresponds to the highest temperature red hot spot (Region 1) in Figure 3b,c, followed by the region between $r_1$ and $r_2$. The outermost region between $r_2$ and $r_3$, represented by the blue area (Region 3), exhibits temperature values approaching the ambient temperature, forming a distinct temperature gradient with the high-temperature central region.

Based on the thermal conduction characteristics of each region, the thermal energy volume and heat dissipation efficiency of each region are described using thermal capacitance $C_{Tn}$ and thermal resistances $R_{Tn}$. Here, $C_{Tn}$ and $R_{Tn}$ are modeled as fixed values that depend solely on the material and dimensions, neglecting the effects of dissipated power and internal temperature variations on heat dissipation efficiency. This simplification is made because the self-heating model is intended to provide a reference lattice temperature for the temperature-dependent parameters in the compact SCR model. The primary focus of the calculations is on the heat source temperature, and the nonlinear variations in heat dissipation efficiency, being small, have limited impact on the heat source temperature during thermal conduction. Additionally, since SCRs typically operate in low-frequency application, the changes in thermal accumulation during conduction are relatively gradual, and nonlinear effects do not significantly affect the overall thermal response. Therefore, by neglecting the nonlinear changes in heat dissipation efficiency, sufficient accuracy is maintained while avoiding the introduction of complex nonlinear calculations that could cause convergence issues, thus improving computational efficiency. The corresponding thermal resistance and thermal capacitance are represented by Equations (13)–(16) as shown below [24]:

$$R_{T1}={\displaystyle \frac{1}{4\pi kW{r}_1}}$$

(13)

$$R_{Tn}={\displaystyle \frac{ln\left(r_n/r_{n-1}\right)}{4\pi kW}}$$

(14)

$$C_{T1}={\displaystyle \frac{1}{2}}\pi \rho CW{r_1}^2$$

(15)

$$C_{Tn}={\displaystyle \frac{1}{2}}\pi \rho CW\left({r_n}^2-{r_{n-1}}^2\right)$$

(16)

Here, $k$ represents the thermal conductivity of silicon, which varies with temperature and doping concentration; $W$ denotes the effective width of the device; $r_n$ correspond to the characteristic radii of each region; $\rho$ is the silicon density; $C$ is the specific heat capacity of silicon. Both the $\rho$ and $C$ determines the heat transfer characteristics within the device.

Table 2. Reference values of parameters for the self-heating model.

Key Parameters	Values	Other Parameters	Values
$C_{T1}$ [nF]	0.07	$r_1$ [µm]	0.5
$C_{T2}$ [nF]	1.10	$r_2$ [µm]	2
$C_{T3}$ [nF]	3.51	$r_3$ [µm]	4
$R_{T1}$ [Ω]	15.92	$W$ [µm]	100
$R_{T2}$ [Ω]	11.04	$C$ [J/g·K]	0.8
$R_{T3}$ [Ω]	5.11	$k$ [W/µm·K]	0.1 × 10−3
		$\rho$ [g/µm³]	2.33 × 10−12

lists the parameters of the above self-heating model for reference.

Based on Equations (13)–(16), a SPICE-compatible equivalent circuit model is implemented using Cauer network topology, while retaining the physical heat conduction characteristics. As illustrated in Figure 4b, the thermal resistances $R_{Tn}$ and thermal capacitances $C_{Tn}$ of the temperature regions are converted into a series RC network. The excitation source $P_{T0}$ originates from the transient output power of the SCR compact model and can be mapped as a current source in this thermal network. The node voltages net1, net2, and net3 correspond to temperature values that decrease progressively from the hot spot to the outer region. This layered RC structure not only reflects the spatial characteristics of heat transfer but also accurately describes the temperature coupling relationships between regions. The model provides reliable simulation of transient thermal response during ESD events, enabling accurate assessment of device thermodynamic behavior.

The self-heating model is tightly integrated with the previously described SCR physical model through a feedback loop, as depicted in Figure 5, thereby establishing a comprehensive temperature feedback system. Under ESD stress conditions, this coupling manifests as a dynamic feedback process. The ESD current generates Joule heating, leading to temperature rise, which modifies device parameters (such as mobility and depletion region width). These parameter variations alter the current distribution, resulting in new temperature profiles and forming a sustained positive feedback loop. Appropriate feedback mechanisms must be established in the model to account for these complex thermal-electrical coupling effects. The model presented in this study was developed using the hardware description language Verilog-A, enabling this feedback mechanism to be realized through a looping algorithm during programming.

3. Model Verification

To verify the proposed self-heating model, SCR devices with a width of 100 μm were fabricated in a 0.18 μm Bipolar-CMOS-DMOS (BCD) process. 3D-TCAD simulations provided reference data by obtaining lattice temperature distributions across different device regions under ESD stress. The Direct Current (DC) turn-on characteristics were then measured using semiconductor parameter analyzer. A Transmission Line Pulse (TLP) system with 10 ns rise time and 100 ns pulse width was employed to evaluate the transient characteristics and quasi-static characteristics (V–T and I–V curves), enabling comprehensive assessment of self-heating effects on device performance.

3.1. Analysis of Self-Heating Effects in Compact Model

SPICE simulation was performed to analyze the transient thermal response of the proposed SCR model under ESD stress. A 1A current pulse with 100 ns duration was applied to the compact SCR model incorporating the self-heating effects. As shown in Figure 6, the temperature response curves of the three characteristic regions demonstrate rapid temperature rise at pulse onset followed by gradual decrease after ESD pulse, revealing the device’s thermal dynamic characteristics. The spatial temperature distribution shows a consistent decrease from Region 1 to Region 3, aligning with the physical heat diffusion process from center to periphery.

To further validate the model accuracy, transient temperature distributions of the SCR device by stressing the 1A current pulse were analyzed using 3D-TCAD simulations. Figure 7 shows the lattice temperature distribution along line C–C1 in Figure 3b at t = 50 ns. The spatial regions in the self-heating model were divided into three zones (indicated by pink, green, and blue colors in Figure 7), and compared with SPICE simulation results at the same point in time. Despite using piecewise linear approximation, the proposed model predicts temperature distributions that closely match the continuous temperature field from TCAD simulations. The good agreement between temperature predictions in different regions demonstrates the model effectiveness.

3.2. Analysis of Key Parameters in Compact Model

3.2.1. Emitter Resistance

The impact of emitter resistance self-heating on SCR compact model accuracy was evaluated by comparing simulations with and without the self-heating model under a 1A current pulse, as shown in Figure 8. During steady-state (70–90 ns), experimental measurements (black dotted lines) show a clamping voltage of 5.75 V. Simulations without self-heating (red curve) predict 4.98 V, yielding an 11% error due to neglecting temperature-dependent resistance increases. Including the self-heating model (blue curve) corrects the on-state resistance temperature dependence, resulting in a predicted clamping voltage of 5.77 V with approximately 1% error. The minor voltage fluctuations observed between 30–50 ns in the experimental curve originate from TLP measurement system reflections rather than intrinsic SCR characteristics and can be excluded from model considerations.

3.2.2. Junction Capacitance

Similar to the emitter resistance analysis, the junction capacitance self-heating model was evaluated. Equation (17) was adopted for practical simulations due to the complexity of the built-in potential expression in Equation (11) and potential numerical convergence issues:

$$C_j=C_{j0}\ast \left[1+m\left(T-T_0\right)\right]$$

(17)

The junction capacitance primarily affects the overshoot voltage in SCR transient characteristics. Under a 1A current pulse (Figure 9), experimental measurements showed an overshoot voltage of 39.3 V. Simulations without the self-heating model predicted 41.5 V (5.6% error), as the underestimated capacitance reduced transient current suppression capabilities. Incorporating temperature-dependent junction capacitance corrected the overshoot voltage to 39.3 V, matching experimental results. This improvement is particularly significant for high-frequency applications where accurate overshoot voltage prediction is crucial for device protection assessment.

3.2.3. Reverse Saturation Current

Temperature dependency of reverse saturation current significantly influences SCR device behavior. The exponential growth of reverse saturation current with temperature enhances carrier generation and internal electric field formation. This results in reduced trigger threshold voltage and accelerated post-trigger anode current increase. Consequently, the device exhibits faster overshoot voltage decay and improved conducting state stability.

A comparative analysis of transient response with and without temperature effects was performed under a 1A current pulse, as shown in Figure 10. Without temperature effects, the model predicted an overshoot voltage of 42.2 V compared to the measured 39.3 V. The discrepancy became more pronounced during voltage decay: at 25 ns post-pulse, the measured voltage decreased to 8.9 V, while the model without temperature effects showed 13.5 V. Including temperature effects on reverse saturation current improved the prediction accuracy significantly, with simulated voltage decreasing to 9.8 V. This enhancement demonstrates the critical role of temperature-dependent reverse saturation current in modeling transient conduction behavior for ESD protection applications.

3.3. Analysis of the Direct Current (DC) and Quasi-Static Characteristics of Compact Model

DC characteristics were measured using a voltage source with 0.2 V steps and 1 mA current limit, as shown in Figure 11. The measured data (black dotted lines) show strong avalanche breakdown at the N-well/P-well junction when voltage reaches 14.2 V, causing the current to rise rapidly to the 1 mA limit. The device exhibits good off-state performance with a leakage current below 1 pA. The simulation results (red curve) accurately demonstrate both turn-on and turn-off characteristics, validating the model’s effectiveness.

It should be noted that, prior to SCR turn-on, the device’s leakage current is too small to cause a noticeable rise in lattice temperature, so the impact of self-heating effects on the DC response of the SCR is negligible. However, once the SCR is turned on, self-heating effects significantly influence the SCR’s quasi-static I–V characteristics.

The quasi-static I–V characteristics were validated using TLP measurements. The I–V curve was extracted by averaging voltage and current values within 70–90 ns window under various TLP pulses, as shown in Figure 12. The experimental results (black dotted lines) show a trigger voltage of 18.6 V, holding voltage of 4.5 V, and on-state resistance Ron of 1.9 Ω. The simulation results without self-heating effects (red curve) show a trigger voltage of 18.9 V, a holding voltage of 4.3 V, and an on-state resistance of 0.9 Ω. This error primarily stems from the temperature dependence of junction capacitance, reverse saturation current, and emitter resistance, which were detailed in Section 3.2. The most significant issue is the approximately halved on-state resistance, which can severely impact the model’s predictive accuracy. In contrast, the simulation results with self-heating effects (blue curve) demonstrate good agreement with measurements, validating the accuracy of the model in characterizing the SCR device’s behavior. These results establish a reliable basis for both ESD protection circuit design and SCR device optimization.

4. Conclusions

This study proposes a compact SCR model incorporating self-heating effects. The model represents lattice temperature variations under ESD stress through a thermal network and describes temperature-dependent physical parameters within the SCR. Experimental validation demonstrates that the compact SCR model, with self-heating effects included, exhibits high accuracy in predicting both DC and transient responses, accurately characterizing the SCR’s turn-on and clamping behaviors. For circuit designers, this model provides a reliable choice for the design and optimization of ESD protection units. Furthermore, the model is implemented in Verilog-A, independent of predefined process model libraries. All parameters and circuit connections are defined within the code, enabling seamless integration with mainstream Electronic Design Automation (EDA) tools such as Advanced Design System (ADS) and Virtuoso, offering excellent portability and ease of use for circuit designers.

However, there are potential limitations in the application of this model under extreme conditions. To improve simulation convergence and computational efficiency, the model simplifies by neglecting nonlinear variations in heat dissipation efficiency during thermal conduction. This simplification has negligible effects on simulation results in typical ESD protection scenarios but may influence accuracy in high-frequency applications due to the repeated accumulation of heat. Future studies can address this issue by modeling thermal resistance as a function of temperature and dissipated power. Additionally, under extreme high-temperature conditions, the device’s thermal failure must be considered. The model can be extended to include critical temperature markers, providing investigators with timely feedback to prevent simulated current from exceeding the device’s limits.