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11 pages, 3368 KB

Open AccessArticle

Charge-Domain Type 2.2 µm BSI Global Shutter Pixel with Dual-Depth DTI Produced by Thick-Film Epitaxial Process

by Toshifumi Yokoyama, Masafumi Tsutsui, Yoshiaki Nishi, Yoshihiro Noguchi, Masahiko Takeuchi, Masahiro Oda and Fenigstein Amos

Sensors 2025, 25(22), 6997; https://doi.org/10.3390/s25226997 - 16 Nov 2025

Viewed by 431

Abstract

We developed a 2.2 µm backside-illuminated (BSI) global shutter (GS) pixel featuring true charge-domain-correlated double sampling (CDS). To enhance the inverse parasitic light sensitivity (1/PLS), we implemented a thick-film epitaxial process incorporating a dual-depth deep trench isolation (DTI) structure. The thickness of the [...] Read more.

We developed a 2.2 µm backside-illuminated (BSI) global shutter (GS) pixel featuring true charge-domain-correlated double sampling (CDS). To enhance the inverse parasitic light sensitivity (1/PLS), we implemented a thick-film epitaxial process incorporating a dual-depth deep trench isolation (DTI) structure. The thickness of the epitaxial substrate was 8.5 µm. This structure was designed using optical simulation. By using a thick epitaxial substrate, it is possible to reduce the amount of light that reaches the memory node. The dual-depth DTI design, with a shallower trench on the readout side, enables efficient signal transfer from the photodiode (PD) to the memory node. To achieve this structure, we developed a process for thick epitaxial substrate, and the dual-depth DTI can be fabricated with a single mask. This pixel represents the smallest charge-domain GS pixel developed to date. Despite its compact size, it achieves a high quantum efficiency (QE) of 83% (monochrome sample: wavelength = 560 nm) and a 1/PLS exceeding 10,000 (white halogen lamp with IR-cut filter). The pixel retains 80% of its peak QE at ±15° incident angles and maintains stable 1/PLS performance even under low F-number (F#) conditions. Full article

(This article belongs to the Special Issue Special Issue on the 2025 International Image Sensor Workshop (IISW2025))

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11 pages, 4034 KB

Open AccessArticle

Fresnel Diffraction Model for Laser Dazzling Spots of Complementary Metal Oxide Semiconductor Cameras

by Xinyu Wang, Zhongjie Xu, Hairong Zhong, Xiang’ai Cheng, Zhongyang Xing and Jiangbin Zhang

Sensors 2024, 24(17), 5781; https://doi.org/10.3390/s24175781 - 5 Sep 2024

Cited by 1 | Viewed by 1916

Abstract

Laser dazzling on complementary metal oxide semiconductor (CMOS) image sensors is an effective method in optoelectronic countermeasures. However, previous research mainly focused on the laser dazzling under far fields, with limited studies on situations that the far-field conditions were not satisfied. In this [...] Read more.

Laser dazzling on complementary metal oxide semiconductor (CMOS) image sensors is an effective method in optoelectronic countermeasures. However, previous research mainly focused on the laser dazzling under far fields, with limited studies on situations that the far-field conditions were not satisfied. In this paper, we established a Fresnel diffraction model of laser dazzling on a CMOS by combining experiments and simulations. We calculated that the laser power density and the area of saturated pixels on the detector exhibit a linear relationship with a slope of 0.64 in a log-log plot. In the experiment, we found that the back side illumination (BSI-CMOS) matched the simulations, with an error margin of 3%, while the front side illumination (FSI-CMOS) slightly mismatched the simulations, with an error margin of 14%. We also found that the full-screen saturation threshold for the BSI-CMOS was 25% higher than the FSI-CMOS. Our work demonstrates the applicability of the Fresnel diffraction model for BSI-CMOS, which provides a valuable reference for studying laser dazzling. Full article

(This article belongs to the Special Issue Selected Papers from the International Conference on Next-Generation Electronics & Photonics (INGEP 2024))

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19 pages, 9339 KB

Open AccessArticle

Towards a Better Understanding of the Back-Side Illumination Mode on Photocatalytic Metal–Organic Chemical Vapour Deposition Coatings Used for Treating Wastewater Polluted by Pesticides

by Cristian Yoel Quintero-Castañeda, Claire Tendero, Thibaut Triquet, Paola Andrea Acevedo, Laure Latapie, María Margarita Sierra-Carrillo and Caroline Andriantsiferana

Water 2024, 16(1), 1; https://doi.org/10.3390/w16010001 - 19 Dec 2023

Cited by 3 | Viewed by 2712

Abstract

Pesticides are emerging contaminants that pose various risks to human health and aquatic ecosystems. In this work, diuron was considered as a contaminant model to investigate the influence of the back-side illumination mode (BSI) on the photocatalytic activity of TiO₂ coatings grown [...] Read more.

Pesticides are emerging contaminants that pose various risks to human health and aquatic ecosystems. In this work, diuron was considered as a contaminant model to investigate the influence of the back-side illumination mode (BSI) on the photocatalytic activity of TiO₂ coatings grown on Pyrex plates by metal–organic chemical vapour deposition (MOCVD). A photoreactor working in recirculation mode was irradiated at 365 nm with ultraviolet A (UVA) light-emitting diodes in BSI. The degradation of diuron and its transformation products was analysed by high-performance liquid chromatography, ion chromatography, and total organic carbon analysis. The coatings were characterised by X-ray diffraction analysis and scanning electron microscopy. Five coatings containing 3, 7, 10, 12 and 27 mg of TiO₂ exhibited different morphology, crystallinity, thickness and photocatalytic activities. The morphology and crystallinity of the coatings had no significant influence on their photocatalytic activity, unlike their mass and thickness. TiO₂ contents less than 10 mg limit the photocatalytic activity, whereas those greater than 15 mg are inefficient in the BSI because of their thickness. The maximum efficiency was achieved for coatings of thickness 1.8 and 2 µm with TiO₂ contents of 10 and 12 mg, revealing that the photocatalyst thickness controls the photocatalytic efficiency in the BSI. Full article

(This article belongs to the Special Issue Application of Photocatalysis in Water/Wastewater Treatment: Latest Advances and Prospects)

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16 pages, 8018 KB

Open AccessArticle

Visible-Band Nanosecond Pulsed Laser Damage Thresholds of Silicon 2D Imaging Arrays

by Christopher Westgate and David James

Sensors 2022, 22(7), 2526; https://doi.org/10.3390/s22072526 - 25 Mar 2022

Cited by 15 | Viewed by 6417

Abstract

Laser-induced camera damage thresholds were measured for several sensors of three different sensor architectures using a Q-switched Nd:YAG laser in order to determine their pulsed laser-induced damage thresholds. Charge coupled device (CCD), front-side illuminated complimentary metal-oxide semiconductor (FSI CMOS), and back-side illuminated (BSI) [...] Read more.

Laser-induced camera damage thresholds were measured for several sensors of three different sensor architectures using a Q-switched Nd:YAG laser in order to determine their pulsed laser-induced damage thresholds. Charge coupled device (CCD), front-side illuminated complimentary metal-oxide semiconductor (FSI CMOS), and back-side illuminated (BSI) CMOS sensors were assessed under laboratory and outdoor environments by increasing the focused laser intensity onto the sensors and recording the sensor output. The damage sites were classified qualitatively into damage types, and pixel counting methods were applied to quantitatively plot damage scale against laser intensity. Probit-fits were applied to find the intensity values where a 95% probability of damage would occur (FD₉₅) and showed that FD₉₅ was approximately the same under laboratory conditions for CCD, FSI CMOS, and BSI CMOS sensors (mean 532 nm FD₉₅ of 0.077 ± 0.01 Jcm⁻²). BSI CMOS sensors were the most robust to large-scale damage effects—BSI sensor kill was found at approximately 10³ Jcm⁻², compared to 10 Jcm⁻² for FSI CMOS, and between ~1.6 and 2.7 Jcm⁻² for CCDs. Full article

(This article belongs to the Section Sensing and Imaging)

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13 pages, 3938 KB

Open AccessLetter

CMOS Depth Image Sensor with Offset Pixel Aperture Using a Back-Side Illumination Structure for Improving Disparity

by Jimin Lee, Sang-Hwan Kim, Hyeunwoo Kwen, Juneyoung Jang, Seunghyuk Chang, JongHo Park, Sang-Jin Lee and Jang-Kyoo Shin

Sensors 2020, 20(18), 5138; https://doi.org/10.3390/s20185138 - 9 Sep 2020

Cited by 1 | Viewed by 6584

Abstract

This paper presents a CMOS depth image sensor with offset pixel aperture (OPA) using a back-side illumination structure to improve disparity. The OPA method is an efficient way to obtain depth information with a single image sensor without additional external factors. Two types [...] Read more.

This paper presents a CMOS depth image sensor with offset pixel aperture (OPA) using a back-side illumination structure to improve disparity. The OPA method is an efficient way to obtain depth information with a single image sensor without additional external factors. Two types of apertures (i.e., left-OPA (LOPA) and right-OPA (ROPA)) are applied to pixels. The depth information is obtained from the disparity caused by the phase difference between the LOPA and ROPA images. In a CMOS depth image sensor with OPA, disparity is important information. Improving disparity is an easy way of improving the performance of the CMOS depth image sensor with OPA. Disparity is affected by pixel height. Therefore, this paper compared two CMOS depth image sensors with OPA using front-side illumination (FSI) and back-side illumination (BSI) structures. As FSI and BSI chips are fabricated via different processes, two similar chips were used for measurement by calculating the ratio of the OPA offset to pixel size. Both chips were evaluated for chief ray angle (CRA) and disparity in the same measurement environment. Experimental results were then compared and analyzed for the two CMOS depth image sensors with OPA. Full article

(This article belongs to the Section Physical Sensors)

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10 pages, 4479 KB

Open AccessFeature PaperArticle

A 120-ke⁻ Full-Well Capacity 160-µV/e⁻ Conversion Gain 2.8-µm Backside-Illuminated Pixel with a Lateral Overflow Integration Capacitor

by Isao Takayanagi, Ken Miyauchi, Shunsuke Okura, Kazuya Mori, Junichi Nakamura and Shigetoshi Sugawa

Sensors 2019, 19(24), 5572; https://doi.org/10.3390/s19245572 - 17 Dec 2019

Cited by 18 | Viewed by 9316

Abstract

In this paper, a prototype complementary metal-oxide-semiconductor (CMOS) image sensor with a 2.8-μm backside-illuminated (BSI) pixel with a lateral overflow integration capacitor (LOFIC) architecture is presented. The pixel was capable of a high conversion gain readout with 160 μV/e⁻ for low light [...] Read more.

In this paper, a prototype complementary metal-oxide-semiconductor (CMOS) image sensor with a 2.8-μm backside-illuminated (BSI) pixel with a lateral overflow integration capacitor (LOFIC) architecture is presented. The pixel was capable of a high conversion gain readout with 160 μV/e⁻ for low light signals while a large full-well capacity of 120 ke⁻ was obtained for high light signals. The combination of LOFIC and the BSI technology allowed for high optical performance without degradation caused by extra devices for the LOFIC structure. The sensor realized a 70% peak quantum efficiency with a normal (no anti-reflection coating) cover glass and a 91% angular response at ±20° incident light. This 2.8-μm pixel is potentially capable of higher than 100 dB dynamic range imaging in a pure single exposure operation. Full article

(This article belongs to the Special Issue Special issue on the 2019 International Image Sensor Workshop (IISW2019))

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4 pages, 887 KB

Open AccessProceeding Paper

A Back-Illuminated Time-of-Flight Image Sensor with SOI-Based Fully Depleted Detector Technology for LiDAR Application

by Sanggwon Lee, Keita Yasutomi, Ho Hai Nam, Masato Morita and Shoji Kawahito

Proceedings 2018, 2(13), 798; https://doi.org/10.3390/proceedings2130798 - 22 Nov 2018

Cited by 5 | Viewed by 3642

Abstract

A back-illuminated time-of-flight (ToF) image sensor based on a 0.2 µm silicon-on-insulator (SOI) CMOS detector technology using fully-depleted substrate is developed for the light detection and ranging (LiDAR) applications. A fully-depleted 200 µm-thick bulk silicon is used for the higher quantum efficiency (QE) [...] Read more.

A back-illuminated time-of-flight (ToF) image sensor based on a 0.2 µm silicon-on-insulator (SOI) CMOS detector technology using fully-depleted substrate is developed for the light detection and ranging (LiDAR) applications. A fully-depleted 200 µm-thick bulk silicon is used for the higher quantum efficiency (QE) in a near-infrared (NIR) region. The developed SOI pixel structure has a 4-tapped charge modulator with a draining function to achieve a higher range resolution and to cancel background light signal. A distance is measured up to 27 m with a range resolution of 12 cm at the outdoor and average light power density is 150 mW/m²@30 m. Full article

(This article belongs to the Proceedings of EUROSENSORS 2018)

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11 pages, 4496 KB

Open AccessArticle

Toward the Ultimate-High-Speed Image Sensor: From 10 ns to 50 ps

by Anh Quang Nguyen, Vu Truong Son Dao, Kazuhiro Shimonomura, Kohsei Takehara and Takeharu Goji Etoh

Sensors 2018, 18(8), 2407; https://doi.org/10.3390/s18082407 - 24 Jul 2018

Cited by 17 | Viewed by 6771

Abstract

The paper summarizes the evolution of the Backside-Illuminated Multi-Collection-Gate (BSI MCG) image sensors from the proposed fundamental structure to the development of a practical ultimate-high-speed silicon image sensor. A test chip of the BSI MCG image sensor achieves the temporal resolution of 10 [...] Read more.

The paper summarizes the evolution of the Backside-Illuminated Multi-Collection-Gate (BSI MCG) image sensors from the proposed fundamental structure to the development of a practical ultimate-high-speed silicon image sensor. A test chip of the BSI MCG image sensor achieves the temporal resolution of 10 ns. The authors have derived the expression of the temporal resolution limit of photoelectron conversion layers. For silicon image sensors, the limit is 11.1 ps. By considering the theoretical derivation, a high-speed image sensor designed can achieve the frame rate close to the theoretical limit. However, some of the conditions conflict with performance indices other than the frame rate, such as sensitivity and crosstalk. After adjusting these trade-offs, a simple pixel model of the image sensor is designed and evaluated by simulations. The results reveal that the sensor can achieve a temporal resolution of 50 ps with the existing technology. Full article

(This article belongs to the Section Physical Sensors)

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13 pages, 5392 KB

Open AccessArticle

A 750 K Photocharge Linear Full Well in a 3.2 μm HDR Pixel with Complementary Carrier Collection

by Frédéric Lalanne, Pierre Malinge, Didier Hérault, Clémence Jamin-Mornet and Nicolas Virollet

Sensors 2018, 18(1), 305; https://doi.org/10.3390/s18010305 - 20 Jan 2018

Cited by 10 | Viewed by 8750

Abstract

Mainly driven by automotive applications, there is an increasing interest in image sensors combining a high dynamic range (HDR) and immunity to the flicker issue. The native HDR pixel concept based on a parallel electron and hole collection for, respectively, a low signal [...] Read more.

Mainly driven by automotive applications, there is an increasing interest in image sensors combining a high dynamic range (HDR) and immunity to the flicker issue. The native HDR pixel concept based on a parallel electron and hole collection for, respectively, a low signal level and a high signal level is particularly well-suited for this performance challenge. The theoretical performance of this pixel is modeled and compared to alternative HDR pixel architectures. This concept is proven with the fabrication of a 3.2 μm pixel in a back-side illuminated (BSI) process including capacitive deep trench isolation (CDTI). The electron-based image uses a standard 4T architecture with a pinned diode and provides state-of-the-art low-light performance, which is not altered by the pixel modifications introduced for the hole collection. The hole-based image reaches 750 kh+ linear storage capability thanks to a 73 fF CDTI capacitor. Both images are taken from the same integration window, so the HDR reconstruction is not only immune to the flicker issue but also to motion artifacts. Full article

(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))

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14 pages, 7346 KB

Open AccessArticle

Design and Performance of a Pinned Photodiode CMOS Image Sensor Using Reverse Substrate Bias

by Konstantin D. Stefanov, Andrew S. Clarke, James Ivory and Andrew D. Holland

Sensors 2018, 18(1), 118; https://doi.org/10.3390/s18010118 - 3 Jan 2018

Cited by 24 | Viewed by 13559

Abstract

A new pinned photodiode (PPD) CMOS image sensor with reverse biased p-type substrate has been developed and characterized. The sensor uses traditional PPDs with one additional deep implantation step to suppress the parasitic reverse currents, and can be fully depleted. The first prototypes [...] Read more.

A new pinned photodiode (PPD) CMOS image sensor with reverse biased p-type substrate has been developed and characterized. The sensor uses traditional PPDs with one additional deep implantation step to suppress the parasitic reverse currents, and can be fully depleted. The first prototypes have been manufactured on an 18 µm thick, 1000 Ω·cm epitaxial silicon wafers using 180 nm PPD image sensor process. Both front-side illuminated (FSI) and back-side illuminated (BSI) devices were manufactured in collaboration with Teledyne e2v. The characterization results from a number of arrays of 10 µm and 5.4 µm PPD pixels, with different shape, the size and the depth of the new implant are in good agreement with device simulations. The new pixels could be reverse-biased without parasitic leakage currents well beyond full depletion, and demonstrate nearly identical optical response to the reference non-modified pixels. The observed excessive charge sharing in some pixel variants is shown to not be a limiting factor in operation. This development promises to realize monolithic PPD CIS with large depleted thickness and correspondingly high quantum efficiency at near-infrared and soft X-ray wavelengths. Full article

(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))

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21 pages, 13577 KB

Open AccessArticle

Statistical Analysis of the Random Telegraph Noise in a 1.1 μm Pixel, 8.3 MP CMOS Image Sensor Using On-Chip Time Constant Extraction Method

by Calvin Yi-Ping Chao, Honyih Tu, Thomas Meng-Hsiu Wu, Kuo-Yu Chou, Shang-Fu Yeh, Chin Yin and Chih-Lin Lee

Sensors 2017, 17(12), 2704; https://doi.org/10.3390/s17122704 - 23 Nov 2017

Cited by 17 | Viewed by 10509

Abstract

A study of the random telegraph noise (RTN) of a 1.1 μm pitch, 8.3 Mpixel CMOS image sensor (CIS) fabricated in a 45 nm backside-illumination (BSI) technology is presented in this paper. A noise decomposition scheme is used to pinpoint the noise source. [...] Read more.

A study of the random telegraph noise (RTN) of a 1.1 μm pitch, 8.3 Mpixel CMOS image sensor (CIS) fabricated in a 45 nm backside-illumination (BSI) technology is presented in this paper. A noise decomposition scheme is used to pinpoint the noise source. The long tail of the random noise (RN) distribution is directly linked to the RTN from the pixel source follower (SF). The full 8.3 Mpixels are classified into four categories according to the observed RTN histogram peaks. A theoretical formula describing the RTN as a function of the time difference between the two phases of the correlated double sampling (CDS) is derived and validated by measured data. An on-chip time constant extraction method is developed and applied to the RTN analysis. The effects of readout circuit bandwidth on the settling ratios of the RTN histograms are investigated and successfully accounted for in a simulation using a RTN behavior model. Full article

(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))

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20 pages, 4509 KB

Open AccessReview

Toward 100 Mega-Frames per Second: Design of an Ultimate Ultra-High-Speed Image Sensor

by Dao Vu Truong Son, Takeharu Goji Etoh, Masatoshi Tanaka, Nguyen Hoang Dung, Vo Le Cuong, Kohsei Takehara, Toshiro Akino, Kenji Nishi, Hitoshi Aoki and Junichi Nakai

Sensors 2010, 10(1), 16-35; https://doi.org/10.3390/s100100016 - 24 Dec 2009

Cited by 28 | Viewed by 16718

Abstract

Our experiencein the design of an ultra-high speed image sensor targeting the theoretical maximum frame rate is summarized. The imager is the backside illuminated in situ storage image sensor (BSI ISIS). It is confirmed that the critical factor limiting the highest frame rate [...] Read more.

Our experiencein the design of an ultra-high speed image sensor targeting the theoretical maximum frame rate is summarized. The imager is the backside illuminated in situ storage image sensor (BSI ISIS). It is confirmed that the critical factor limiting the highest frame rate is the signal electron transit time from the generation layer at the back side of each pixel to the input gate to the in situ storage area on the front side. The theoretical maximum frame rate is estimated at 100 Mega-frames per second (Mfps) by transient simulation study. The sensor has a spatial resolution of 140,800 pixels with 126 linear storage elements installed in each pixel. The very high sensitivity is ensured by application of backside illumination technology and cooling. The ultra-high frame rate is achieved by the in situ storage image sensor (ISIS) structure on the front side. In this paper, we summarize technologies developed to achieve the theoretical maximum frame rate, including: (1) a special p-well design by triple injections to generate a smooth electric field backside towards the collection gate on the front side, resulting in much shorter electron transit time; (2) design technique to reduce RC delay by employing an extra metal layer exclusively to electrodes responsible for ultra-high speed image capturing; (3) a CCD specific complementary on-chip inductance minimization technique with a couple of stacked differential bus lines. Full article

(This article belongs to the Special Issue Image Sensors 2009)

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