Search Results (19)

A simple algorithm for respiratory activity detection in data produced by Frequency-Modulated Continuous-Wave (FMCW) radars is presented in this paper. The proposed computational architecture can be directly mapped onto custom digital–analog VLSI hardware, which is a unique approach in research on intelligent FMCW sensor development, offering a potential energy-efficient data analysis solution for target applications, such as preventing human trafficking or providing life-sign detection under limited visibility. The algorithm comprises two main modules. The first one summarizes radar-produced data into a descriptor reflecting the amount of motion that occurs within appropriately determined time intervals. The second one classifies a sequence of the produced descriptors using a recurrent neural network composed of gated recurrent units. To ensure the algorithm’s implementation feasibility, an analog VLSI circuit comprising its main functional blocks has been designed, manufactured, and tested, providing constraints for neural model derivation. The adverse effects of the primary constraint, the severe restriction on admissible weight resolution, have been handled by introducing a novel training loss component and a simple mechanism for diversifying the effective weight sets of different network neurons. Experimental evaluation of the presented method, performed using the dataset of indoor recordings, indicates that the proposed simple, hardware implementation-friendly algorithm provides over 94% human detection accuracy and similar F1 scores. Full article

This paper presents an original algorithm and the application of a Via Check script implemented in the PVS/Pegasus Verification System Tool (Cadence). The algorithm was written in the physical verification language. Via Check is mainly looking for places in the layout where connections (vias) between metals within the same net are missing or could be reinforced. The designed tool was equipped with special user interface graphics to filter the obtained results for more convenient use. It was successfully used in many projects involving advanced submicron technologies like cmos65lp, cmos40lp, stios40nm, stios28nm, 16ff, and 12ff for almost two years. Its application supported by examples of the results from ongoing projects is also included in this publication. Full article

This study introduces a low-power analog integrated Euclidean distance radial basis function classifier. The high-level architecture is composed of several Manhattan distance circuits in connection with a current comparator circuit. Notably, each implementation was designed with modularity and scalability in mind, effectively accommodating variations in the classification parameters. The proposed classifier’s operational principles are meticulously detailed, tailored for low-power, low-voltage, and fully tunable implementations, specifically targeting biomedical applications. This design methodology materialized within a 90 nm CMOS process, utilizing the Cadence IC Suite for the comprehensive management of both the schematic and layout design aspects. During the verification phase, post-layout simulation results were meticulously cross-referenced with software-based classifier implementations. Also, a comparison study with related analog classifiers is provided. Through the simulation results and comparative study, the design architecture’s accuracy and sensitivity were effectively validated and confirmed. Full article

A Spiking Neural Network (SNN) is realized within a 65 nm CMOS process to demonstrate the feasibility of its constituent cells. Analog hardware neural networks have shown improved energy efficiency in edge computing for real-time-inference applications, such as speech recognition. The proposed network uses a leaky integrate and fire neuron scheme for computation, interleaved with a Spike Timing Dependent Plasticity (STDP) circuit for implementing synaptic-like weights. The low-power, asynchronous analog neurons and synapses are tailored for the VLSI environment needed to effectively make use of hardware SSN systems. To demonstrate functionality, a feed-forward Spiking Neural Network composed of two layers, the first with ten neurons and the second with six, is implemented. The neuron design operates with 2.1 pJ of power per spike and 20 pJ per synaptic operation. Full article

This study introduces a general methodology for the design of analog integrated bell-shaped classifiers. Each high-level architecture is composed of several Gaussian function circuits in conjunction with a Winner-Take-All circuit. Notably, each implementation is designed with modularity and scalability in mind, effectively accommodating variations in classification parameters. The operating principles of each classifier are illustrated in detail and are used in low-power, low-voltage, and fully tunable implementations targeting biomedical applications. The realization of this design methodology occurred within a 90 nm CMOS process, leveraging the Cadence IC suite for both electrical and layout design aspects. In the verification phase, post-layout simulation outcomes were meticulously compared against software-based implementations of each classifier. Through the simulation results and comparison study, the design methodology is confirmed in terms of accuracy and sensitivity. Full article

Nowadays, sensors with built-in sigma–delta modulators (ΣΔMs) are widely used in consumer, industrial, automotive, and medical applications, as they have become a cost-effective and convenient way to deliver data to digital processors. This is the case for micro-electro-mechanical system (MEMS), digital microphones that convert analog audio to a pulse-density modulated (PDM) bitstream. However, as the ΣΔMs output a PDM signal, sensors require either built-in or external high-order decimation filters to demodulate the PDM signal to a baseband multi-bit pulse-code modulated (PCM) signal. Because of this extra circuit requirement, the implementation of sensor array algorithms, such as beamforming in embedded systems (where the processing resources are critical) or in very large-scale integration (VLSI) circuits (where the power and area are crucial) becomes especially expensive as a large number of parallel decimation filters are required. This article proposes a novel architecture for beamforming algorithm implementation that fuses delay and decimation operations based on maximally flat (MAXFLAT) filters to make array processing more affordable. As proof of concept, we present an implementation example of a delay-and-sum (DAS) beamformer at given spatial and frequency requirements using this novel approach. Under these specifications, the proposed architecture requires 52% lower storage resources and 19% lower computational resources than the most efficient state-of-the-art architecture. Full article

There is always a need for low-power, area-efficient VLSI (Very Large-Scale Integration) design and this need is increasing day by day. However, conventional design methods based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) devices and Complementary Metal-Oxide-Semiconductor Transistor (CMOS) technology cannot meet the performance requirements. The memristor, as a promising computing and memory integration device, offers a new research idea for conventional logic circuit structure and architecture innovation, given its non-volatility, scalability, low power consumption, fast switching speed, etc. This paper proposes a brief overview of the characteristics and current status of memristor-based logic circuits and analyzes their applications in numerical expression and memory. The benefits and drawbacks of various analog logic circuit structures are summarized and compared. In addition, some solution strategies for these issues are presented. Finally, this paper offers prospects for the applications of memristors in the logic implementation of large-scale memristor arrays, the novel structure of in-memory computing, and neural network computing. Full article

A new improved accuracy CMOS Gaussian function generator will be presented. The original sixth-order approximation function that represents the basis for designing the proposed Gaussian circuit allows a large increase in the circuit accuracy and also of the input variable maximal range. The original proposed computational structure has a large dynamic output range of 27 dB, for a variation smaller than 1 dB as compared with the ideal Gaussian function. The circuit is simulated for 0.18 μm CMOS technology and has a low supply voltage (V_DD = 0.7 V). Its power consumption is smaller than 0.22 μW, for V_DD = 0.7 V, while the chip area is about 7 μm². The new proposed architecture is re-configurable, the convenient modification of the coefficients allowing to obtain many mathematical functions using the same computational structure. Full article

Electromyography is a diagnostic medical procedure used to assess the state of a muscle and its related nerves. Electromyography signals are monitored to detect neuromuscular abnormalities and diseases but can also prove useful in decoding movement-related signals. This information is vital to controlling prosthetics in a more natural way. To this end, a novel analog integrated voting classifier is proposed as a hand gesture recognition system. The voting classifiers utilize 3 separate centroid-based classifiers, each one attached to a different electromyographic electrode and a voting circuit. The main building blocks of the architecture are bump and winner-take-all circuits. To confirm the proper operation of the proposed classifier, its post-layout classification results (91.2% accuracy) are compared to a software-based implementation (93.8% accuracy) of the same voting classifier. A TSMC 90 nm CMOS process in the Cadence IC Suite was used to design and simulate the following circuits and architectures. Full article

We report on fabricated titanium dioxide (TiO₂) thin films along with a transimpedance amplifier (TIA) test setup as a photoconductivity detector (sensor) in the ultraviolet-C (UV-C) wavelength region, particularly at 260 nm. TiO₂ thin films deposited on high-resistivity undoped silicon-substrate at thicknesses of 100, 500, and 1000 nm exhibited photoresponsivities of 81.6, 55.6, and 19.6 mA/W, respectively, at 30 V bias voltage. Despite improvements in the crystallinity of the thicker films, the decrease in photocurrent, photoconductivity, photoconductance, and photoresponsivity in thicker films is attributed to an increased number of defects. Varying the thickness of the film can, however, be leveraged to control the wavelength response of the detector. Future development of a chip-based portable UV-C detector using TiO₂ thin films will open new opportunities for a wide range of applications. Full article

This paper presents a new analog front-end classification system that serves as a wake-up engine for digital back-ends, targeting embedded devices for epileptic seizure prediction. Predicting epileptic seizures is of major importance for the patient’s quality of life as they can lead to paralyzation or even prove fatal. Existing solutions rely on power hungry embedded digital inference engines that typically consume several µW or even mW. To increase the embedded device’s autonomy, a new approach is presented combining an analog feature extractor with an analog Gaussian mixture model-based binary classifier. The proposed classification system provides an initial, power-efficient prediction with high sensitivity to switch on the digital engine for the accurate evaluation. The classifier’s circuit is chip-area efficient, operating with minimal power consumption (180 nW) at low supply voltage (0.6 V), allowing long-term continuous operation. Based on a real-world dataset, the proposed system achieves 100% sensitivity to guarantee that all seizures are predicted and good specificity (69%), resulting in significant power reduction of the digital engine and therefore the total system. The proposed classifier was designed and simulated in a TSMC 90 nm CMOS process, using the Cadence IC suite. Full article

CMOS microelectronics design has evolved tremendously during the last two decades. The evolution of CMOS devices to short channel designs where the feature size is below 1000 nm brings a great deal of uncertainty in the way the microelectronics design cycle is completed. After the conceptual idea, developing a thinking model to understand the operation of the device requires a good “ballpark” evaluation of transistor sizes, decision making, and assumptions to fulfill the specifications. This design process has iterations to meet specifications that exceed in number of the available degrees of freedom to maneuver the design. Once the thinking model is developed, the simulation validation follows to test if the design has a good possibility of delivering a successful prototype. If the simulation provides a good match between specifications and results, then the layout is developed. This paper shows a useful open science strategy, using the Excel software, to develop CMOS microelectronics hand calculations to verify a design, before performing the computer simulation and layout of CMOS analog integrated circuits. The full methodology is described to develop designs of passive components, as well as CMOS amplifiers. The methods are used in teaching CMOS microelectronics to students of electronic engineering with industrial partner participation. This paper describes an exhaustive example of a low-voltage operational transconductance amplifier (OTA) design which is used to design an instrumentation amplifier. Finally, a test is performed using this instrumentation amplifier to implement a front-end signal conditioning device for CMOS-MEMS biomedical applications. Full article

This paper reports a “single-transistor” Class-F⁻¹ power amplifier (PA) in 65 nm CMOS, which operates at the microwave center frequency of 6 GHz. The PA is loaded with a Class-F⁻¹ harmonic control network, employing a new “parasitic-aware” topology deduced using a novel iterative algorithm. A dual-purpose output matching network is designed, which not only serves the purpose of output impedance matching, but also reinforces the harmonic control of the Class-F⁻¹ harmonic network. This proposed PA yields a peak power-added efficiency (PAE) of 47.8%, which is one of the highest when compared to previously reported integrated microwave/millimeter-wave PAs in CMOS and SiGe technologies. The amplifier shows a saturated output power of 14.4 dBm along with an overall gain of 13.8 dB. Full article

The interest in large-scale integrated (LSI) microfluidic systems that perform high-throughput biological and chemical laboratory investigations on a single chip is steadily growing. Such highly integrated Labs-on-a-Chip (LoC) provide fast analysis, high functionality, outstanding reproducibility at low cost per sample, and small demand of reagents. One LoC platform technology capable of LSI relies on specific intrinsically active polymers, the so-called stimuli-responsive hydrogels. Analogous to microelectronics, the active components of the chips can be realized by photolithographic micro-patterning of functional layers. The miniaturization potential and the integration degree of the microfluidic circuits depend on the capability of the photolithographic process to pattern hydrogel layers with high resolution, and they typically require expensive cleanroom equipment. Here, we propose, compare, and discuss a cost-efficient do-it-yourself (DIY) photolithographic set-up suitable to micro-pattern hydrogel-layers with a resolution as needed for very large-scale integrated (VLSI) microfluidics. The achievable structure dimensions are in the lower micrometer scale, down to a feature size of 20 µm with aspect ratios of 1:5 and maximum integration densities of 20,000 hydrogel patterns per cm². Furthermore, we demonstrate the effects of miniaturization on the efficiency of a hydrogel-based microreactor system by increasing the surface area to volume (SA:V) ratio of integrated bioactive hydrogels. We then determine and discuss a correlation between ultraviolet (UV) exposure time, cross-linking density of polymers, and the degree of immobilization of bioactive components. Full article

A concept for creating a large class of lightweight stream ciphers as Key Stream Generators KSGs is presented. The resulting class-size exceeds 2³²³ possible different KSGs. If one unknown cipher from the KSG-class is randomly picked-up and stored irreversibly within a VLSI device, the device becomes physically hard-to-clone. The selected cipher is only usable by the device itself, therefore cloning it requires an invasive attack on that particular device. Being an unknown selection out of 2³²³ possible KSGs, the resulting cipher is seen as a Secret Unknown Cipher (SUC). The SUC concept was presented a decade ago as a digital alternative to the inconsistent traditional analog Physically Unclonable Functions (PUFs). This work presents one possible practical self-creation technique for such PUFs as hard-to-clone unknown KSGs usable to re-identify VLSI devices. The proposed sample cipher-structure is based on non-linear merging of randomly selected 16 Nonlinear Feedback Shift Registers (NLFSRs). The created KSGs exhibit linear complexities exceeding 2⁸¹ and a period exceeding 2¹⁶¹. The worst-case device cloning time complexity approaches 2¹⁶². A simple lightweight identification protocol for physically identifying such SUC structures in FPGA-devices is presented. The required self-reconfiguring FPGAs for embedding such SUCs are not yet available, however, expected to emerge in the near future. The security analysis and hardware complexities of the resulting clone-resistant structures are evaluated and shown to offer scalable security levels to cope even with the post-quantum cryptography. Full article