Search Results (47)

Based on the GSMC 180 nm SiGe BiCMOS process, a parallel-summation logarithmic amplifier is presented in this paper. The logarithmic amplifier adopts a cascaded structure of nine-stage fully-differential limiting amplifiers (LA) to achieve high dynamic range. The ten-stage rectifier completes the conversion of amplified voltage to a logarithmic current signal. A log slope adjuster is proposed. It can provide slopes of 17–30 mV/dB by configuring an off-chip resistor to meet the detection requirements of different input power. Meanwhile, a power-down control unit is designed to reduce the power consumption to only 162 μW in standby mode. The post-simulation results show that under 5 V power supply voltage, the dynamic range exceeds 80 dB and the 3 dB bandwidth is 20 MHz–4 GHz. It also has a fast response time of 42 ns with a power consumption of 109 mW in normal operation mode. Full article

This paper presents an active phase shifter for phased array system applications, implemented using 0.18 μm SiGe BiCMOS technology. The phase shifter circuit consists of a wideband quadrature signal generator, a vector modulator, an input balun, and an output balun. To enhance the bandwidth, a polyphase filter is employed as the quadrature signal generator, and a two-stage RC-CR filter with a highly symmetrical miniaturized layout is cascaded to create multiple resonant points, thus extending the phase shifter’s bandwidth to cover the required range. The gain of the variable-gain amplifier within the vector modulator is adjustable by varying the tail current, thereby enlarging the range of selectable points, improving phase-shifting accuracy, and reducing gain fluctuations. The measurement results show that the proposed active phase shifter achieves an RMS phase error of less than 2° and a gain variation ranging from −1.2 dB to 0.1 dB across a 20 GHz to 30 GHz bandwidth at room temperature. The total chip area is 0.4 mm², with a core area of 0.165 mm², and consumes 19.5 mW of power from a 2.5 V supply. Full article

In this paper, a novel Colpitts voltage-controlled oscillator (VCO) with low phase noise and an octave frequency tuning range is presented. To achieve low phase noise and a wide tuning range concurrently, the designed VCO employs quad-core-coupled structures, series resonators, dual-mode-coupled inductors, and push–push structures. The quad-core-coupled structures are used for phase noise improvement. The presented series resonators effectively expand the tuning range while reducing phase noise deterioration from amplitude-to-phase modulation (AM/PM) conversion. The dual-mode operation based on coupled inductors and quad-core structures further expands the tuning range. In addition, the adopted push–push structure increases the output frequency. Designed in a 180 nm SiGe BiCMOS process, the proposed Colpitts VCO operates from 7.2 to 14.5 GHz with an octave tuning range of 67.3%. The phase noise ranges from −131.4 to −121.8 dBc/Hz with a peak figure-of-merit (FoM) of 183.0 dBc/Hz and figure-of-merit-tuning (FoM_T) of 199.5 dBc/Hz at a 1 MHz offset. The proposed VCO exhibits superior performance in phase noise and tuning range and achieves an octave tuning range for the first time in Colpitts VCOs. Full article

This paper presents a compact V-band low-noise amplifier (LNA) featuring temperature compensation, implemented in a 130 nm SiGe BiCMOS process. A negative temperature coefficient bias circuit generates an adaptive current for temperature compensation, enhancing the LNA’s temperature robustness. A T-type inductive network is employed to establish two dominant poles at different frequencies, significantly broadening the amplifier’s bandwidth. Over the wide temperature range of −55 °C to 85 °C, the LNA prototype exhibits a gain variation of less than 1.5 dB at test frequencies from 40 GHz to 65 GHz, corresponding to a temperature coefficient of 0.01 dB/°C. At −55 °C, 25 °C, and 85 °C, the measured peak gains are 25.5 dB, 25 dB, and 24.4 dB, respectively, with minimum noise figures (NF) of 3.0 dB, 3.5 dB, and 4.2 dB, and DC power consumptions of 22.3 mW, 27.6 mW, and 34.4 mW. Moreover, the total silicon area of the LNA chip is 0.37 mm², including all test pads, while the core area is only 0.09 mm². Full article

This paper introduces a high-gain wideband power amplifier (PA) designed for V-band applications, operating across 52 to 65 GHz. The proposed PA design employs a combination of techniques, including pole-gain distribution, base-capacitive peaking, and the parallel configuration of multiple small-sized transistors. These strategies enable significant bandwidth extension while maintaining high gain, substantial output power, and a compact footprint. A two-stage PA using the combination technique was developed and fabricated in a 130 nm SiGe BiCMOS process. The PA prototype achieved a peak gain of 27.3 dB at 64 GHz, with a 3 dB bandwidth exceeding 13 GHz and a fractional bandwidth greater than 22.2%. It delivered a maximum saturated output power of 19.7 dBm and an output 1 dB compression point of 18 dBm. Moreover, the PA chip occupied a total silicon area of 0.57 mm², including all testing pads with a compact core size of 0.198 mm². Full article

This paper addresses the design of a CMOS modulator to control two quantum bits. The proposed architecture offers several advantages that are addressed and discussed in this paper. The proposed architecture is investigated through both mathematical modeling and Verilog simulations. Moreover, the circuit was designed using the cryogenic Design Kit of the 130 nm SiGe BiCMOS technology of the IHP foundry. The observed agreement between the modeling, Verilog, and transistor-level simulations proves the physical feasibility of the proposed architecture. Full article

The article presents the analysis, design, and low-cost implementation of application-specific AD converters for M-sequence-based UWB applications to minimize and integrate the whole UWB sensor system. Therefore, the main goal of this article is to integrate the AD converter’s own design with the UWB analog part into the system-in-package (SiP) or directly into the system-on-a-chip (SoC), which cannot be implemented with commercial AD converters, or which would be disproportionately expensive. Based on the current and used UWB sensor system requirements, to achieve the maximum possible bandwidth in the proposed semiconductor technology, a parallel converter structure is designed and presented in this article. Moreover, 5-bit and 4-bit parallel flash AD converters were initially designed as part of the research and design of UWB M-sequence radar systems for specific applications, and are briefly introduced in this article. The requirements of the newly proposed specific UWB M-sequence systems were established based on the knowledge gained from these initial designs. After thorough testing and evaluation of the concept of the early proposed AD converters for these specific UWB M-sequence systems, the design of a new AD converter was initiated. After confirming sufficient characteristics based on the requirements of UWB M-sequence systems for specific applications, a 7-bit AD converter in low-cost 0.35 µm SiGe BiCMOS technology from AMS was designed, fabricated, and presented in this article. The proposed 7-bit AD converter achieves the following parameters: ENOB = 6.4 bits, SINAD = 38 dB, SFDR = 42 dBc, INL = ±2-bit LSB, and DNL = ±1.5 LSB. The maximum sampling rate reaches 1.4 Gs/s, the power consumption at 20 Ms/s is 1050 mW, and at 1.4 Gs/s is 1290 mW, with a power supply of −3.3 V. Full article

This article proposes a chip antenna on millimeter-Waves. This antenna combined with TSMC 180 nm SiGe CMOS technology has the advantage of being small in size and is suitable for wireless communications. The multilayer architecture Horn antenna implemented on M4–M6 can meet both process reliability specifications and radiation performance. The results of the simulation show that the maximum gain is −4.2 dBi. The return loss measurement results are almost consistent with the simulation results, and the bandwidth range is 177.4–183 GHz. This article first describes the antenna production process and measurement results, analyses the impact of the parameters on the antenna, and further compares it with other designs. The excellence of this article is that it proposes a design that solves the problem of large millimeter wave loss and successfully reduces the area. At the same time, this article can contribute to readers’ future optimization and continued research directions, and at the same time contribute simulation and measurement trends to let readers understand the stability of CMOS chip antenna simulation and measurement. Full article

This paper presents a high-gain low-noise amplifier (LNA) operating at the 5G mm-wave band. The full design combines two conventional cascode stages: common base (CB) and common emitter (CS). The design technique reduces the miller effect and uses low-voltage supply and low-current-density transistors to simultaneously achieve high gain and low noise figures (NFs). The two-stage LNA topology is analyzed and designed using 0.25 µm SiGe BiCMOS process technology from NXP semiconductors. The measured circuit shows a small signal gain at 26 GHz of 26 dB with a gain error below 1 dB on the entire frequency band (26–28 GHz). The measured average NF is 3.84 dB, demonstrated over the full frequency band under 15 mA current consumption per stage, supplied with a voltage of 3.3 V. Full article

Amplification of wideband high-frequency and microwave signals is a fundamental element within every high-frequency circuit and device. Ultra-wideband (UWB) sensor applications use circuits designed for their specific application. The article presents the analysis, design, and implementation of ultra-wideband differential amplifiers for M-sequence-based UWB applications. The designed differential amplifiers are based on the Cherry–Hooper structure and are implemented in a low-cost 0.35 µm SiGe BiCMOS semiconductor process. The article presents an analysis and realization of several designs focused on different modifications of the Cherry–Hooper amplifier structure. The proposed amplifier modifications are focused on achieving the best result in one main parameter’s performance. Amplifier designs modified by capacitive peaking to achieve the largest bandwidth, amplifiers with the lowest possible noise figure, and designs focused on achieving the highest common mode rejection ratio (CMRR) are described. The layout of the differential amplifiers was created and the chip was manufactured and wire-bonded to the QFN package. For evaluation purposes, a high-frequency PCB board was designed. Schematic simulations, post-layout simulations, and measurements of the individual parameters of the designed amplifiers were performed. The designed and fabricated ultra-wideband differential amplifiers have the following parameters: a supply current of 100–160 mA at −3.3 V or 3.3 V, bandwidth from 6 to 12 GHz, gain (at 1 GHz) from 12 to 16 dB, noise figure from 7 to 13 dB, and a common mode rejection ratio of up to 70 dB. Full article

This paper presents the design and measurement of an IEEE 802.11ad standard compatible RF transceiver for 60 GHz wireless communication systems. In addition to the traditional half-duplex (HD) mode, this work supports full-duplex (FD) operations to deliver better channel utilization and faster response times for the system. The isolation between the transmitter and receiver from the architecture design to system integration for FD operations has been fully considered. A digital self-interference cancellation (DSIC) is implemented in MATLAB to verify the FD performance. The super-heterodyne architecture with an intermediate frequency (IF) of 12 GHz is designed to suppress the image frequencies without using extra filters. A flexible phase-locked loop (PLL) synthesizer provides a local oscillator (LO) frequency with a 2 kHz resolution. Other than the time division duplex (TDD) mode used in the conventional 60 GHz system, a wide-bandwidth baseband digital variable-gain amplifier (DVGA) with a 3 dB bandwidth of more than 4 GHz also supports frequency division duplex (FDD) operations. The transceiver chip is fabricated using the Tower Jazz 0.18 µm SiGe BiCMOS process. With an on-board antenna, the transceiver covers all four channels in the 802.11ad standard, with MCS-12 (7.04 Gbps under 1.76 GSym/s and 16-QAM) under 1.5 m. In the proposed system design, the RF frontend-based self-interference (SI) suppression from the local transmitter to receiver LNA is around 54 dB. To achieve a practical FD application, the SI is further suppressed with the help of a digital SI compensation. The measured power consumption for the transmitter and receiver configurations are 194 mW and 231 mW, respectively, in HD mode and 398 mW for the FDD or FD operation mode. Full article

In this work, we present a transceiver front-end in SiGe BiCMOS technology that can provide an ultra-wide bandwidth of 100 GHz at millimeter-wave frequencies. The front-end utilizes an innovative arrangement to efficiently distribute broadband-generated pulses and coherently combine received pulses with minimal loss. This leads to the realization of a fully integrated ultra-high-resolution imaging chip for biomedical applications. We realized an ultra-wide imaging band-width of 100 GHz via the integration of two adjacent disjointed frequency sub-bands of 10–50 GHz and 50–110 GHz. The transceiver front-end is capable of both transmit (TX) and receive (RX) operations. This is a crucial component for a system that can be expanded by repeating a single unit cell in both the horizontal and vertical directions. The imaging elements were designed and fabricated in Global Foundry 130-nm SiGe 8XP process technology. Full article

All ultra-wideband (UWB) sensor applications require hardware designed directly for their specific application. The switching of broadband radio frequency and microwave signals is an integral part of almost every piece of high-frequency equipment, whether in commercial operation or laboratory conditions. The trend of integrating various circuit structures and systems on a chip (SoC) or in a single package (SiP) is also related to the need to design these integrated switches for various measuring devices and instruments in laboratories, paradoxically for their further development. Another possible use is switching high-frequency signals in telecommunications devices, whether mobile or fixed networks, for example, for switching signals from several antennas. Based on these requirements, a high-frequency semiconductor integrated switch with NMOS transistors was designed. With these transistors, it is possible to achieve higher integration than with bipolar ones. Even though MOSFET transistors have worse frequency characteristics, we can compensate them to some extent with the precise design of the circuit and layout of the chip. This article describes the analysis and design of a high-frequency semiconductor integrated switch for UWB applications consisting of three series-parallel switches controlled by CMOS logic signals. They are primarily intended for UWB sensor systems, e.g., when switching and configuring the antenna MIMO system or when switching calibration tools. The design of the switch was implemented in low-cost 0.35 µm SiGe BiCMOS technology with an emphasis on the smallest possible attenuation and the largest possible bandwidth and isolation. The reason for choosing this technology was also that other circuit structures of UWB systems were realized in this technology. Through the simulations, individual parameters of the circuit were simulated, the layout of the chip was also created, and the parameters of the circuit were simulated with the parasitic extraction and the inclusion of parasitic elements (post-layout simulations). Subsequently, the chip was manufactured and its parameters were measured and evaluated. Based on these measurements, the designed and fabricated UWB switch was found to have the following parameters: a supply current of 2 mA at 3.3 V, a bandwidth of 6 GHz, an insertion loss (at 1 GHz) of −2.2 dB, and isolation (at 1 GHz) of $-33$ dB, which satisfy the requirements for our UWB sensor applications. Full article

In this work, the design of a wideband low-noise amplifier (LNA) using a resistive feedback network is proposed for potential multi-band sensing, communication, and radar applications. For achieving wide operational bandwidth and flat in-band characteristics simultaneously, the proposed LNA employs a variety of circuit design techniques, including a voltage–current (shunt–shunt) negative feedback configuration, inductive emitter degeneration, a main branch with an added cascode stage, and the shunt-peaking technique. The use of a feedback network and emitter degeneration provides broadened transfer characteristics for multi-octave coverage and a real impedance for input matching, respectively. In addition, the cascode stage pushes the band-limiting low-frequency pole, due to the Miller capacitance, to a higher frequency. Lastly, the shunt-peaking approach is optimized for the compensation of a gain reduction at higher frequency bands. The wideband LNA proposed in this study is fabricated using a commercial 0.13 μm silicon-germanium (SiGe) BiCMOS process, employing SiGe heterojunction bipolar transistors (HBTs) as the circuit’s core active elements in the main branch. The measurement results show an operational bandwidth of 2.0–29.2 GHz, a noise figure of 4.16 dB (below 26.5 GHz, which was the measurement limit), and a total power consumption of 23.1 mW under a supply voltage of 3.3 V. Regarding the nonlinearity associated with large-signal behavior, the proposed LNA exhibits an input 1-dB compression (IP1dB) point of −5.42 dBm at 12 GHz. These performance numbers confirm the strong viability of the proposed approach in comparison with other state-of-the-art designs. Full article

This paper presents a novel and compact vector modulator (VM) architecture implemented in 130 nm SiGe BiCMOS technology. The design is suitable for use in receive phased arrays for the gateways of major low Earth orbit (LEO) constellations that operate in the 17.8 to 20.2 GHz frequency range. The proposed architecture uses four variable gain amplifiers (VGA) that are active at any given time and are switched to generate the four quadrants. Compared to conventional architectures, this structure is more compact and produces double the output amplitude. The design offers 6-bit phase control for 360°, and the total root mean square (RMS) phase and gain errors are 2.36° and 1.46 dB, respectively. The design occupies an area of 1309.4 $\mathsf{\mu }$m × 1783.8 $\mathsf{\mu }$m (including pads). Full article