Search Results (54)

This work presents a systematic design flow for the fundamental building blocks (namely, the low-noise amplifier and the down-conversion mixer) of an analog receiver for 5G backhauling systems implemented in SiGe BiCMOS technology. The proposed methodology enables the sizing and optimization of receiver blocks up to post-layout simulations, starting from the specified performance requirements. It accounts for both the parasitic effects of active devices and the distributed effects of interconnects. The design flow was applied using STMicroelectronics BiCMOS55X technology to develop low-noise amplifiers and D-band to E-band downconverters capable of covering the 130–150 GHz and 150–165 GHz sub-bands. Preliminary measurement results obtained from both the standalone LNA blocks and the complete receivers are presented and discussed. Full article

Mixers are integral components in RF circuits for frequency conversion and are present in almost all RF front-ends. The relentless advancement of mobile communication standards, particularly towards 5G-Advanced and 6G, imposes ever more stringent and multi-dimensional performance requirements on mixer design. While previous surveys have capably summarized mixer technologies, this review distinguishes itself by providing a comprehensive and critical examination of millimeter-wave and sub-THz silicon-based integrated mixers, with explicit coverage extended from core RF bands to beyond 170 GHz. We place particular emphasis on the unique challenges and trade-offs inherent to silicon (CMOS and SiGe BiCMOS) platforms at these high frequencies. This work first summarizes the structural frameworks and underlying principles of mixers, examines multiple mixer variants, and performs an in-depth analysis of their key performance characteristics, encompassing conversion gain, noise figure (with distinctions between single-sideband (SSB) and double-sideband (DSB) definitions), isolation, and related metrics. Then, it compares and discusses the design of several mixers, especially analyzing their innovative points and key technologies, while critically evaluating their inherent limitations and trade-offs. Furthermore, a dedicated section synthesizes the most recent research trends, including heterogeneous integration, AI/ML-assisted design, and mixer architectures for integrated sensing and communication (ISAC), thereby addressing a notable gap in the current literature. Finally, it concludes with an outlook on future challenges and opportunities for mixers in next-generation communication systems. Full article

To address the challenges of ambient light interference and slow overload recovery in transimpedance amplifiers (TIAs) for automotive Light Detection and Ranging (LiDAR) systems, this paper proposes a high-performance TIA with integrated ambient light cancellation and fast recovery capabilities. The core design includes an adaptive ambient light cancellation (ALC) loop that eliminates background currents up to 3 mA without relying on AC coupling capacitors, achieving a low-frequency cutoff frequency of 321 kHz to ensure the signal-to-noise ratio (SNR) of weak target signals. A multi-stage clamping and current transfer mechanism is employed to realize rapid overload recovery: under 100 mA heavy overload conditions, the recovery time is controlled around 8.7 ns, and the pulse broadening is limited to 2.7 ns, avoiding measurement blind zones. Implemented in a 0.18-μm SiGe BiCMOS process, the proposed TIA occupies a compact area of 0.15 mm², with a transimpedance gain of 80 dBΩ (10 kΩ) and a −3 dB bandwidth of 421 MHz. The input-referred noise current spectral density is 4.7 $\mathrm{pA}/\sqrt{\mathrm{Hz}}$, and the integrated equivalent input noise current from 1 Hz to 250 MHz is 73.6 nA_rms. Operating over a temperature range of −40 ℃ to 125 ℃, the TIA meets the rigorous requirements of automotive-grade applications. Performance comparisons with commercial products and state-of-the-art designs demonstrate its competitive ambient light rejection and fast recovery capabilities, validating its potential for use in direct time-of-flight (dToF) LiDAR systems for autonomous driving. Full article

The current-mode logic (CML) driver has evolved alongside integrated circuit (IC) technology. Its typical structure contains a tail current source, differential amplifying transistors, and load resistors. It is widely used in modern optical transceivers and other serial link transceivers, and is compatible with various processes, including CMOS, SiGe BiCMOS, and InP DHBT. The basic performance indicators of CML driver include gain, bandwidth, power, and total harmonic distortion (THD). For different application scenarios, different tail currents and load resistance are required. Nowadays, as the performance requirements for drivers in various applications continue to increase, more techniques need to be employed to balance high speed, high output amplitude, high linearity, and low power, such as bandwidth expansion techniques, linearity improvement techniques, and gain control techniques. In this review, the electrical characteristics of basic CML circuits are highlighted and compared with other interface level standards. The advancement of CML drivers is summarized. Emerging CML structures and performance enhancement technologies are introduced and analyzed. Design considerations are concluded in terms of the challenges faced by high-speed drivers. The review provides comparative study and comprehensive reference for designers. Full article

This paper presents an advanced W-band bidirectional Power Amplifier–Low Noise Amplifier (PALNA) implemented using 130 nm SiGe BiCMOS technology. The proposed RF front-end eliminates the need for conventional transmit/receive (T/R) switches by employing a bidirectional architecture with a passive matching network. This approach minimizes area requirements and reduces signal losses. Post-layout simulation results demonstrate that the designed PALNA achieves a peak small-signal gain of 30 dB in Tx mode and 26 dB in Rx mode, with reverse isolation better than 40 dB. The 3 dB bandwidth spans from 94 to 106 GHz. In LNA mode, the design achieves a minimum noise figure of 6 dB at 100 GHz, remaining below 6.5 dB across the entire 3 dB bandwidth. In PA mode, the simulated saturated output power is 10.5 dBm, with a maximum power-added efficiency of 12% at 100 GHz. The chip size is 0.7 mm² including pads. It consumes 78 and 22 mW in the Tx and Rx modes, respectively. Full article

This paper presents a 90–100 GHz wideband digital phase shifter with a fine resolution of 5.625°, implemented in a 0.13 μm SiGe BiCMOS process. A switch-type architecture with six cascaded units, including a novel 180° cell based on a broadband coupler, enables full 0–360° phase coverage while improving phase accuracy, bandwidth, and process robustness. Post-layout simulations demonstrate an insertion loss below 15.5 dB, an RMS phase error under 2.3°, and an RMS amplitude error better than 0.9 dB across the 90–100 GHz band. The total chip area, including test pads, is 0.39 mm², making the design compact and well suited for high-density phased-array applications. Full article

This paper introduces a 0.5–5.8 GHz low-noise amplifier (LNA) incorporating a gyrator-C-based active inductor (AI) and an enhanced deep trench isolation (DTI) electrostatic discharge (ESD) diode. Results suggest that AIs exhibit excellent consistency under various process voltage temperatures (PVTs) as well as input powers and the improved DTI diodes reduce parasitic capacitance by an average of 8.5% compared to conventional ones. In terms of circuit design, comprehensive analyses of gain flatness and noise are conducted. Fabricated using a 0.18 μm SiGe BiCMOS technology, the LNA delivers a high S21 of 18.3 ± 0.3 dB, a minimum noise figure of 2.6 dB, and an S11 and S22 of less than −10 dB over the entire frequency band. Operating from a 3.3 V supply voltage with a core area of 0.049 mm², it consumes 10 mA of current. Full article

Based on the GSMC 180 nm SiGe BiCMOS process, a parallel-summation logarithmic amplifier is presented in this paper. The logarithmic amplifier adopts a cascaded structure of nine-stage fully-differential limiting amplifiers (LA) to achieve high dynamic range. The ten-stage rectifier completes the conversion of amplified voltage to a logarithmic current signal. A log slope adjuster is proposed. It can provide slopes of 17–30 mV/dB by configuring an off-chip resistor to meet the detection requirements of different input power. Meanwhile, a power-down control unit is designed to reduce the power consumption to only 162 μW in standby mode. The post-simulation results show that under 5 V power supply voltage, the dynamic range exceeds 80 dB and the 3 dB bandwidth is 20 MHz–4 GHz. It also has a fast response time of 42 ns with a power consumption of 109 mW in normal operation mode. Full article

This paper presents an active phase shifter for phased array system applications, implemented using 0.18 μm SiGe BiCMOS technology. The phase shifter circuit consists of a wideband quadrature signal generator, a vector modulator, an input balun, and an output balun. To enhance the bandwidth, a polyphase filter is employed as the quadrature signal generator, and a two-stage RC-CR filter with a highly symmetrical miniaturized layout is cascaded to create multiple resonant points, thus extending the phase shifter’s bandwidth to cover the required range. The gain of the variable-gain amplifier within the vector modulator is adjustable by varying the tail current, thereby enlarging the range of selectable points, improving phase-shifting accuracy, and reducing gain fluctuations. The measurement results show that the proposed active phase shifter achieves an RMS phase error of less than 2° and a gain variation ranging from −1.2 dB to 0.1 dB across a 20 GHz to 30 GHz bandwidth at room temperature. The total chip area is 0.4 mm², with a core area of 0.165 mm², and consumes 19.5 mW of power from a 2.5 V supply. Full article

In this paper, a novel Colpitts voltage-controlled oscillator (VCO) with low phase noise and an octave frequency tuning range is presented. To achieve low phase noise and a wide tuning range concurrently, the designed VCO employs quad-core-coupled structures, series resonators, dual-mode-coupled inductors, and push–push structures. The quad-core-coupled structures are used for phase noise improvement. The presented series resonators effectively expand the tuning range while reducing phase noise deterioration from amplitude-to-phase modulation (AM/PM) conversion. The dual-mode operation based on coupled inductors and quad-core structures further expands the tuning range. In addition, the adopted push–push structure increases the output frequency. Designed in a 180 nm SiGe BiCMOS process, the proposed Colpitts VCO operates from 7.2 to 14.5 GHz with an octave tuning range of 67.3%. The phase noise ranges from −131.4 to −121.8 dBc/Hz with a peak figure-of-merit (FoM) of 183.0 dBc/Hz and figure-of-merit-tuning (FoM_T) of 199.5 dBc/Hz at a 1 MHz offset. The proposed VCO exhibits superior performance in phase noise and tuning range and achieves an octave tuning range for the first time in Colpitts VCOs. Full article

This paper presents a compact V-band low-noise amplifier (LNA) featuring temperature compensation, implemented in a 130 nm SiGe BiCMOS process. A negative temperature coefficient bias circuit generates an adaptive current for temperature compensation, enhancing the LNA’s temperature robustness. A T-type inductive network is employed to establish two dominant poles at different frequencies, significantly broadening the amplifier’s bandwidth. Over the wide temperature range of −55 °C to 85 °C, the LNA prototype exhibits a gain variation of less than 1.5 dB at test frequencies from 40 GHz to 65 GHz, corresponding to a temperature coefficient of 0.01 dB/°C. At −55 °C, 25 °C, and 85 °C, the measured peak gains are 25.5 dB, 25 dB, and 24.4 dB, respectively, with minimum noise figures (NF) of 3.0 dB, 3.5 dB, and 4.2 dB, and DC power consumptions of 22.3 mW, 27.6 mW, and 34.4 mW. Moreover, the total silicon area of the LNA chip is 0.37 mm², including all test pads, while the core area is only 0.09 mm². Full article

This paper introduces a high-gain wideband power amplifier (PA) designed for V-band applications, operating across 52 to 65 GHz. The proposed PA design employs a combination of techniques, including pole-gain distribution, base-capacitive peaking, and the parallel configuration of multiple small-sized transistors. These strategies enable significant bandwidth extension while maintaining high gain, substantial output power, and a compact footprint. A two-stage PA using the combination technique was developed and fabricated in a 130 nm SiGe BiCMOS process. The PA prototype achieved a peak gain of 27.3 dB at 64 GHz, with a 3 dB bandwidth exceeding 13 GHz and a fractional bandwidth greater than 22.2%. It delivered a maximum saturated output power of 19.7 dBm and an output 1 dB compression point of 18 dBm. Moreover, the PA chip occupied a total silicon area of 0.57 mm², including all testing pads with a compact core size of 0.198 mm². Full article

This paper addresses the design of a CMOS modulator to control two quantum bits. The proposed architecture offers several advantages that are addressed and discussed in this paper. The proposed architecture is investigated through both mathematical modeling and Verilog simulations. Moreover, the circuit was designed using the cryogenic Design Kit of the 130 nm SiGe BiCMOS technology of the IHP foundry. The observed agreement between the modeling, Verilog, and transistor-level simulations proves the physical feasibility of the proposed architecture. Full article

The article presents the analysis, design, and low-cost implementation of application-specific AD converters for M-sequence-based UWB applications to minimize and integrate the whole UWB sensor system. Therefore, the main goal of this article is to integrate the AD converter’s own design with the UWB analog part into the system-in-package (SiP) or directly into the system-on-a-chip (SoC), which cannot be implemented with commercial AD converters, or which would be disproportionately expensive. Based on the current and used UWB sensor system requirements, to achieve the maximum possible bandwidth in the proposed semiconductor technology, a parallel converter structure is designed and presented in this article. Moreover, 5-bit and 4-bit parallel flash AD converters were initially designed as part of the research and design of UWB M-sequence radar systems for specific applications, and are briefly introduced in this article. The requirements of the newly proposed specific UWB M-sequence systems were established based on the knowledge gained from these initial designs. After thorough testing and evaluation of the concept of the early proposed AD converters for these specific UWB M-sequence systems, the design of a new AD converter was initiated. After confirming sufficient characteristics based on the requirements of UWB M-sequence systems for specific applications, a 7-bit AD converter in low-cost 0.35 µm SiGe BiCMOS technology from AMS was designed, fabricated, and presented in this article. The proposed 7-bit AD converter achieves the following parameters: ENOB = 6.4 bits, SINAD = 38 dB, SFDR = 42 dBc, INL = ±2-bit LSB, and DNL = ±1.5 LSB. The maximum sampling rate reaches 1.4 Gs/s, the power consumption at 20 Ms/s is 1050 mW, and at 1.4 Gs/s is 1290 mW, with a power supply of −3.3 V. Full article

This article proposes a chip antenna on millimeter-Waves. This antenna combined with TSMC 180 nm SiGe CMOS technology has the advantage of being small in size and is suitable for wireless communications. The multilayer architecture Horn antenna implemented on M4–M6 can meet both process reliability specifications and radiation performance. The results of the simulation show that the maximum gain is −4.2 dBi. The return loss measurement results are almost consistent with the simulation results, and the bandwidth range is 177.4–183 GHz. This article first describes the antenna production process and measurement results, analyses the impact of the parameters on the antenna, and further compares it with other designs. The excellence of this article is that it proposes a design that solves the problem of large millimeter wave loss and successfully reduces the area. At the same time, this article can contribute to readers’ future optimization and continued research directions, and at the same time contribute simulation and measurement trends to let readers understand the stability of CMOS chip antenna simulation and measurement. Full article