Search Results (19)

The development of low-temperature piezoresistive materials provides compatibility with standard silicon-based MEMS fabrication processes. Additionally, it enables the use of such material in flexible substrates, thereby expanding the potential for various device applications. This work demonstrates, for the first time, the fabrication of a 200 nm polycrystalline silicon thin film through a metal-induced crystallization process mediated by an AlSiCu alloy at temperatures as low as 450 °C on top of silicon and polyimide (PI) substrates. The resulting polycrystalline film structure exhibits crystallites with a size of approximately 58 nm, forming polysilicon (poly-Si) grains with diameters between 1–3 µm for Si substrates and 3–7 µm for flexible PI substrates. The mechanical and electrical properties of the poly-Si were experimentally conducted using microfabricated test structures containing piezoresistors formed by poly-Si with different dimensions. The poly-Si material reveals a longitudinal gauge factor (GF) of 12.31 and a transversal GF of −4.90, evaluated using a four-point bending setup. Additionally, the material has a linear temperature coefficient of resistance (TCR) of −2471 ppm/°C. These results illustrate the potential of using this low-temperature film for pressure, force, or temperature sensors. The developed film also demonstrated sensitivity to light, indicating that the developed material can also be explored in photo-sensitive applications. Full article

Crystalline silicon (c-Si) solar cells with passivation stacks consisting of a polycrystalline silicon (poly-Si) layer and a thin interfacial silicon dioxide (SiO₂) layer show high conversion efficiencies. Since the poly-Si layer in this structure acts as a carrier transport layer, high doping of the poly-Si layer is crucial for high conductivity and the efficient transport of charge carriers from the bulk to a metal contact. In this respect, conventional furnace-based high-temperature doping methods are limited by the solid solubility of the dopants in silicon. This limitation particularly affects p-type doping using boron. Previously, we showed that laser activation overcomes this limitation by melting the poly-Si layer, resulting in an active concentration beyond the solubility limit after crystallization. High electrically active boron concentrations ensure low contact resistivity at the (contact) metal/semiconductor interface and allow for the maskless patterning of the poly-Si layer by providing an etch-stop layer in an alkaline solution. However, the high doping concentration degrades during long high-temperature annealing steps. Here, we performed a test of the stability of such a high doping concentration under thermal stress. The active boron concentration shows only a minor reduction during SiN_x:H deposition at a moderate temperature and a fast-firing step at a high temperature and with a short exposure time. However, for an annealing time $t_{\mathrm{anneal}}$ = 30 min and an annealing temperature 600 °C ≤ $T_{\mathrm{anneal}}$≤ 1000 °C, the high conductivity is significantly reduced, whereas a high passivation quality requires annealing in this range. We resolve this dilemma by introducing a second, healing laser reactivation step, which re-establishes the original high conductivity of the boron-doped poly-Si and does not degrade the passivation. After a thermal annealing temperature $T_{\mathrm{anneal}}$ = 985 °C, the reactivated layers show high sheet conductance (G_sh) with G_sh = 24 mS sq and high passivation quality, with the implied open-circuit voltage (iV_OC) reaching iV_OC = 715 mV. Therefore, our novel three-step process consisting of laser activation, thermal annealing, and laser reactivation/healing is suitable for fabricating highly efficient solar cells with p⁺⁺-poly-Si/SiO₂ contact passivation layers. Full article

Passivated, selective contacts in silicon solar cells consist of a double layer of highly doped polycrystalline silicon (poly Si) and thin interfacial silicon dioxide (SiO₂). This design concept allows for the highest efficiencies. Here, we report on a selective laser activation process, resulting in highly doped p⁺⁺-type poly Si on top of the SiO₂. In this double-layer structure, the p⁺⁺-poly Si layer serves as a layer for transporting the generated holes from the bulk to a metal contact and, therefore, needs to be highly conductive for holes. High boron-doping of the poly Si layers is one approach to establish the desired high conductivity. In a laser activation step, a laser pulse melts the poly Si layer, and subsequent rapid cooling of the Si melt enables electrically active boron concentrations exceeding the solid solubility limit. In addition to the high conductivity, the high active boron concentration in the poly Si layer allows maskless patterning of p⁺⁺-poly Si/SiO₂ layers by providing an etch stop layer in the Si etchant solution, which results in a locally structured p⁺⁺-poly Si/SiO₂ after the etching process. The challenge in the laser activation technique is not to destroy the thin SiO₂, which necessitates fine tuning of the laser process. In order to find the optimal processing window, we test laser pulse energy densities (H_p) in a broad range of 0.7 J/cm² ≤ H_p ≤ 5 J/cm² on poly Si layers with two different thicknesses d_{poly Si,1} = 155 nm and d_{poly Si,2} = 264 nm. Finally, the processing window 2.8 J/cm²≤ H_p ≤ 4 J/cm² leads to the highest sheet conductance (G_sh) without destroying the SiO₂ for both poly Si layer thicknesses. For both tested poly Si layers, the majority of the symmetric lifetime samples processed using these H_p achieve a good passivation quality with a high implied open circuit voltage (iV_OC) and a low saturation current density (J₀). The best sample achieves iV_OC = 722 mV and J₀ = 6.7 fA/cm² per side. This low surface recombination current density, together with the accompanying measurements of the doping profiles, suggests that the SiO₂ is not damaged during the laser process. We also observe that the passivation quality is independent of the tested poly Si layer thicknesses. The findings of this study show that laser-activated p⁺⁺-poly Si/SiO₂ are not only suitable for integration into advanced passivated contact solar cells, but also offer the possibility of maskless patterning of these stacks, substantially simplifying such solar cell production. Full article

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM), based on polycrystalline silicon (poly-Si) nanotube structure with a grain boundary (GB), is designed and analyzed using technology computer-aided design (TCAD) simulation. In the proposed 1T-DRAM, the 1T-DRAM cell exhibited a sensing margin of 422 μA/μm and a retention time of 213 ms at T = 358 K with a single GB. To investigate the effect of random GBs, it was assumed that the number of GB is seven, and the memory characteristics depending on the location and number of GBs were analyzed. The memory performance rapidly degraded due to Shockley–Read–Hall recombination depending on the location and number of GBs. In the worst case, when the number of GB is 7, the mean of the sensing margin was 194 µA/µm, and the mean of the retention time was 50.4 ms. Compared to a single GB, the mean of the sensing margin and the retention time decreased by 59.7% and 77.4%, respectively. Full article

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on a polycrystalline silicon (Poly-Si) metal-oxide-semiconductor field-effect transistor (MOSFET) with a storage layer separated using a separation oxide was designed and analyzed using technology computer-aided design (TCAD). The channel and storage layers were separated using a separation oxide to improve the inferior retention time of the conventional 1T-DRAM, and we adopted the underlap structure to reduce Shockley-Read-Hall recombination. In addition, poly-Si, which has several advantages, including low manufacturing cost and availability of high-density three-dimensional (3D) memory arrays, is used to easily fabricate silicon-on-insulator (SOI)-like structures. Accordingly, we extracted memory performance by analyzing the effect of grain boundary (GB). The proposed 1T-DRAM achieved a sensing margin of 14.10 μA/μm and a retention time of 251 ms at T = 358 K, even in the existence of a GB. Full article

We propose an ambipolar chitosan synaptic transistor that effectively responds to binary neuroplasticity. We fabricated the synaptic transistors by applying a chitosan electric double layer (EDL) to the gate insulator of the excimer laser annealed polycrystalline silicon (poly-Si) thin-film transistor (TFT) with Ni-silicide (NiSi) Schottky-barrier source/drain (S/D) junction. The undoped poly-Si channel and the NiSi S/D contact allowed conduction by electrons and holes, resulting in artificial synaptic behavior in both p-type and n-type regions. A slow polarization reaction by the mobile ions such as anions (CH₃COO⁻ and OH⁻) and cations (H⁺) in the chitosan EDL induced hysteresis window in the transfer characteristics of the ambipolar TFTs. We demonstrated the excitatory post-synaptic current modulations and stable conductance modulation through repetitive potentiation and depression pulse. We expect the proposed ambipolar chitosan synaptic transistor that responds effectively to both positive and negative stimulation signals to provide more complex information process versatility for bio-inspired neuromorphic computing systems. Full article

Energy efficiency and ratio performance are two key parameters for the analysis of the performance of photovoltaic (PV) modules. The present paper focusses on the assessment of the efficiency of four different photovoltaic module technologies based on energy efficiency and ratio performance. These PV modules were installed at the Applied Research Unit in Renewable Energy (URAER) in Algeria and were used to provide experimental data to help local and international economical actors with performance enhancement and optimal choice of different technologies subject to arid outdoor conditions. The modules studied in this paper are: two thin-film modules of copper indium selenide (CIS), hetero-junction with intrinsic thin-layer silicon (HIT) and two crystalline silicon modules (polycrystalline (poly-Si), monocrystalline (mono-Si)). These technologies were initially characterized using a DC regulator based on their measured I-V characteristics under the same outdoor climate conditions as the location where the monitoring of the electrical energy produced from each PV module was carried out. The DC regulator allows for extracting the maximum electrical power. At the same time, the measurements of the solar radiation and temperature were obtained from a pyranometer type Kipp & ZonenTM CMP21 and a Pt-100 temperature sensor (Kipp & Zonen, Delft, Netherlands). These measurements were performed from July 2020 to June 2021. In this work, the monthly average performance parameters such as energy efficiency are given and analyzed. The average efficiency of the modules over 12 months was evaluated at 4.74%, 7.65%, 9.13% and 10.27% for the HIT, CIS, mono-Si and poly-Si modules, respectively. The calculated percentage deviations in the efficiency of the modules were 8.49%, 18.88%, 19.74% and 23.57% for the HIT, CIS, mono-Si and poly-Si modules, respectively. The low variation in the efficiency of the HIT module can be attributed to the better operation of this module under arid outdoor conditions, which makes it a promising module for adaptation to the region concerned. Full article

In this study, polycrystalline silicon (poly-Si) is applied to silicon-oxide-nitride-oxide-silicon (SONOS) flash memory as a channel material and the physical and electrical characteristics are analyzed. The results show that the surface roughness of silicon nitride as charge trapping layer (CTL) is enlarged with the number of interface traps and the data retention properties are deteriorated in the device with underlying poly-Si channel which can be serious problem in gate-last 3D NAND flash memory architecture. To improve the memory performance, high pressure deuterium (D₂) annealing is suggested as a low-temperature process and the program window and threshold voltage shift in data retention mode is compared before and after the D₂ annealing. The suggested curing is found to be effective in improving the device reliability. Full article

Flexible electronics enable various technologies to be integrated into daily life and fuel the quests to develop revolutionary applications, such as artificial skins, intelligent textiles, e-skin patches, and on-skin displays. Mechanical characteristics, including the total thickness and the bending radius, are of paramount importance for physically flexible electronics. However, the limitation regarding semiconductor fabrication challenges the mechanical flexibility of thin-film electronics. Thin-Film Transistors (TFTs) are a key component in thin-film electronics that restrict the flexibility of thin-film systems. Here, we provide a brief overview of the trends of the last three decades in the physical flexibility of various semiconducting technologies, including amorphous-silicon, polycrystalline silicon, oxides, carbon nanotubes, and organics. The study demonstrates the trends of the mechanical properties, including the total thickness and the bending radius, and provides a vision for the future of flexible TFTs. Full article

A low leakage poly-Si thin film transistor (TFT) is proposed featuring hydrogenated amorphous silicon (a-Si:H) buffer layer and source/drain extension (SDE) by using technology computer aided design (TCAD) simulation. This architecture reduces off-current effectively by suppressing two leakage current generation mechanisms with little on-current loss. The amorphous silicon buffer layer having large bandgap energy (E_g) suppresses both thermal generation and minimum leakage current, which leads to higher on/off current ratio. In addition, the formation of lightly doped region near the drain alleviates the field-enhanced generation in the off-state by reducing electric field. TCAD simulation results show that the proposed TFT shows more than three orders of magnitude lower off-current than low-temperature polycrystalline silicon (LTPS) TFTs, while maintaining on-current. Full article

The limited choice of materials for large area electronics limits the expansion of applications. Polycrystalline silicon (poly-Si) and indium gallium zinc oxide (IGZO) lead to thin-film transistors (TFTs) with high field-effect mobilities (>10 cm²/Vs) and high current ON/OFF ratios (I_On/I_Off > ~10⁷). But they both require vacuum processing that needs high investments and maintenance costs. Also, IGZO is prone to the scarcity and price of Ga and In. Other oxide semiconductors require the use of at least two cations (commonly chosen among Ga, Sn, Zn, and In) in order to obtain the amorphous phase. To solve these problems, we demonstrated an amorphous oxide material made using one earth-abundant metal: amorphous tin oxide (a-SnO_x). Through XPS, AFM, optical analysis, and Hall effect, we determined that a-SnO_x is a transparent n-type oxide semiconductor, where the SnO₂ phase is predominant over the SnO phase. Used as the active material in TFTs having a bottom-gate, top-contact structure, a high field-effect mobility of ~100 cm²/Vs and an I_On/I_Off ratio of ~10⁸ were achieved. The stability under 1 h of negative positive gate bias stress revealed a Vth shift smaller than 1 V. Full article

In this study, a novel low impact ionization rate (low-IIR) poly-Si thin film transistor featuring a current and electric field split (CES) structure with bottom field plate (BFP) and partial thicker channel raised source/drain (RSD) designs is proposed and demonstrated. The bottom field plate design can allure the electron and alter the electron current path to evade the high electric field area and therefore reduce the device IIR and suppress the kink effect. A two-dimensional device simulator was applied to describe and compare the current path, electric field magnitude distributions, and IIR of the proposed structure and conventional devices. In addition, the advantages of a partial thicker channel RSD design are present, and the leakage current of CES-thin-film transistor (TFT) can be reduced and the ON/OFF current ratio be improved, owing to a smaller drain electric field. Full article

We investigated the characteristics of excimer laser-annealed polycrystalline silicon–germanium (poly-Si_1−xGe_x) thin film and thin-film transistor (TFT). The Ge concentration was increased from 0% to 12.3% using a SiH₄ and GeH₄ gas mixture, and a Si_1−xGe_x thin film was crystallized using different excimer laser densities. We found that the optimum energy density to obtain maximum grain size depends on the Ge content in the poly-Si_1−xGe_x thin film; we also confirmed that the grain size of the poly-Si_1−xGe_x thin film is more sensitive to energy density than the poly-Si thin film. The maximum grain size of the poly-Si_1−xGe_x film was 387.3 nm for a Ge content of 5.1% at the energy density of 420 mJ/cm². Poly-Si_1−xGe_x TFT with different Ge concentrations was fabricated, and their structural characteristics were analyzed using Raman spectroscopy and atomic force microscopy. The results showed that, as the Ge concentration increased, the electrical characteristics, such as on current and sub-threshold swing, were deteriorated. The electrical characteristics were simulated by varying the density of states in the poly-Si_1−xGe_x. From this density of states (DOS), the defect state distribution connected with Ge concentration could be identified and used as the basic starting point for further analyses of the poly-Si_1−xGe_x TFTs. Full article

A current improved and electric field reduced double-gate (DG) polycrystalline silicon thin-film transistor with two-step source/drain (DGTSD-TFT) design is proposed and demonstrated in this study. The two-step source/drain (TSD) design, which consists of a raised source/drain (RSD) area together with a partial gate overlapped lightly doped drain (P-GOLDD) structure, can lower the device drain electric field (DEF) to reveal a better device performance. Comparisons have been made with respect to a traditional single top gate (STG) device. The operation current of the proposed DGTSD-TFT is almost twice as large as that of the STG structure. The OFF-state leakage current and kink effect, as well as the ON/OFF current ratio for this double-gate and two-step source/drain structure, are also improved simultaneously because of a reduced DEF. A hot carrier stress test reveals that that two-step source/drain structure can achieve more stable device characteristics than the traditional device. Full article

We report the effects of surface passivation by depositing a hydrogenated amorphous silicon (a-Si:H) layer on the electrical characteristics of low temperature polycrystalline silicon thin film transistors (LTPS TFTs). The intrinsic a-Si:H layer was optimized by hydrogen dilution and its structural and electrical characteristics were investigated. The a-Si:H layer in the transition region between a-Si:H and µc-Si:H resulted in superior device characteristics. Using a-Si:H passivation layer, the field-effect mobility of the LTPS TFT was increased by 78.4% compared with conventional LTPS TFT. Moreover, the leakage current measured at V_GS of 5 V was suppressed because the defect sites at the poly-Si grain boundaries were well passivated. Our passivation layer, which allows thorough control of the crystallinity and passivation-quality, should be considered as a candidate for high performance LTPS TFTs. Full article