Search Results (20)

In this work, a novel Schottky-gated p-channel GaN field-effect transistor (PFET) with a tunable n-GaN sub-gate layer is investigated. Terminal-current analysis under the actual drain-bias condition shows that the gate-current contribution remains limited within the defined effective operating range of V_GS ≥ −3.2 V, whereas gate-related current becomes significant at more negative gate biases. Carrier-resolved and spatial current analyses further confirm that, within this operating range, the drain current is predominantly carried by holes through an interfacial hole channel near the p-GaN/AlGaN heterointerface. Benefiting from the intentionally introduced p–n junction beneath the groove gate, the built-in electric field effectively depletes the p-GaN channel, enabling a robust transition from depletion-mode to enhancement-mode (E-mode) operation. By precisely scaling the n-GaN layer thickness (0–5 nm) and donor concentration (3.0 × 10¹⁷ cm⁻³ to 3.0 × 10¹⁹ cm⁻³), the buried p-n junction modulates the depletion condition and hole distribution beneath the gate. The optimized device exhibits a significantly improved subthreshold swing (SS) of 348 mV/dec, while maintaining a stable I_ON/I_OFF ratio on the order of 10². This tunable sub-gate architecture provides a highly flexible platform for optimizing E-mode GaN PFETs, showing great promise for high-performance complementary logic applications. Full article

Cryogenic CMOS technology provides a promising approach to surpass the Boltzmann limit and advance Moore’s Law, addressing the increasing demand for high-performance computing. However, at cryogenic temperatures, the subthreshold swing (SS) of the device saturates due to the band-tail effect. This study presents a 3-vertically stacked gate-all-around nanosheet (NS) transistor featuring room-temperature O radical interface passivation. This approach leverages the high reactivity of O radicals to minimize etch-induced damage, passivate interface defects, reduce thermal budget, and ensure uniformity in complex 3D structures. Structural characterization revealed a uniform 0.76-nm-thick interface layer, with a surface roughness of 0.103 nm and an interface trap density of 2.72 × 10¹¹ cm⁻²·eV⁻¹ at 300 K. Thereby, the band-tail-induced SS saturation at cryogenic temperatures is effectively mitigated. Experimental results confirm a lower characteristic temperature T_v for reaching the saturation plateau, and a saturated SS of 15.4 mV/dec at 4.5 K. Furthermore, reducing disorder-induced defects substantially suppresses the band tail state-assisted carrier emission, thereby minimizing subthreshold leakage. This enables the device to achieve an off-state current below 1 pA/μm at a temperature under 77 K, reaching 0.18 pA/μm at 4.5 K. Additionally, a reduction in 25.4% in drain-induced barrier lowering (DIBL), with a 9% boost in transconductance (G_m) peak is achieved at 4.5 K. The enhanced subthreshold switching, reduced leakage, and improved G_m in this interfacial-optimized NS FET strongly supports cryo-CMOS as a viable solution for energy-efficient computing. Full article

Bilayer transition metal dichalcogenides (TMDs) are promising materials for next-generation field-effect transistors (FETs) due to their atomically thin structure and favorable transport properties. In this study, we employ density functional theory (DFT) to compute the electronic band structures and phonon dispersions of bilayer WS₂, WSe₂, and MoS₂, and the electron-phonon scattering rates using the EPW (electron-phonon Wannier) method. Carrier transport is then investigated within a semiclassical full-band Monte Carlo framework, explicitly including intrinsic electron-phonon scattering, dielectric screening, scattering with hybrid plasmon–phonon interface excitations (IPPs), and scattering with ionized impurities. Freestanding bilayers exhibit the highest mobilities, with hole mobilities reaching 2300 cm²/V·s in WS₂ and 1300 cm²/V·s in WSe₂. Using hBN as the top gate dielectric preserves or slightly enhances mobility, whereas HfO₂ significantly reduces transport due to stronger IPP and remote phonon scattering. Device-level simulations of double-gate FETs indicate that series resistance strongly limits performance, with optimized WSe₂ pFETs achieving ON currents of 820 A/m, and a 10% enhancement when hBN replaces HfO₂. These results show the direct impact of first-principles electronic structure and scattering physics on device-level transport, underscoring the importance of material properties and the dielectric environment in bilayer TMDs. Full article

The paradigm shift from FinFET to gate-all-around nanosheet (GAA-NS) transistor architectures necessitates fundamental innovations in channel material engineering. This work addresses the critical challenge of pFET performance degradation in GAA-NS technologies through the development of an advanced selective etching process for strain-engineered SiGe channel formation. We present a systematic investigation of Si selective etching using CF₄/O₂/N₂ gas mixture in a remote plasma source reactor. It is demonstrated that the addition of N₂ to CF₄/O₂ plasmas significantly improves the selectivity of Si to SiGe (up to 58), by promoting NO* radical-induced passivation layer disruption on Si surfaces. Furthermore, an increase in the F:O ratio has been shown to mitigate stress-induced lateral micro-trenching (“Si-tip”), achieving near-zero tip length at high CF₄ flow (500 sccm) while retaining selectivity (>40). Transmission electron microscopy and energy-dispersive X-ray spectroscopy confirm the complete removal of the Si sacrificial layer with minimal SiGe channel loss, validating the process for high-performance SiGe GAA-NS FET integration. These findings provide critical insights into strain-engineered SiGe channel fabrication, enabling balanced NFET/PFET performance in next-generation semiconductor technologies. Full article

We systematically investigate the combined impact of process variation effects (PVEs), metal gate work function fluctuation (WKF), and random dopant fluctuation (RDF) on the key electrical characteristics of sub-1-nm technology node gate-all-around silicon nanosheet complementary field-effect transistors (GAA Si NS CFETs). Through comprehensive statistical analysis, we reveal that the interplay of these intrinsic and extrinsic sources of variability induces significant fluctuations in the off-state leakage current across both N-/P-FETs in GAA Si NS CFETs. The sensitivity to process-induced variability is found to be particularly pronounced in the P-FETs, primarily due to the enhanced parasitic conduction associated with the bottom nanosheet channel. Given the correlated nature of PVE, WKF, and RDF factors, the statistical sum (RSD) of the fluctuation for each factor is overestimated by less than 50% compared with the simultaneous fluctuations of PVE, WKF, and RDF factors. Furthermore, although the static power dissipation remains relatively small compared to dynamic and short-circuit power components, it exhibits the largest relative fluctuation (approximately 82.1%), posing critical challenges for low-power circuit applications. These findings provide valuable insights into the variability-aware design and optimization of GAA NS CFET device fabrication processes, as well as the development of robust and reliable CFET-based integrated circuits for next-generation technology nodes. Full article

Paper-based electronics have emerged as a sustainable, low-cost, and flexible alternative to traditional substrates for electronics, particularly for disposable and wearable applications. This review outlines recent developments in paper-based devices, focusing on sensors and paper-based field-effect transistors (PFETs). Key fabrication techniques such as laser-induced graphene, inkjet printing, and screen printing have enabled the creation of highly sensitive and selective devices on various paper substrates. Material innovations, especially the integration of graphene, carbon-based materials, conductive polymers, and other novel micro- and nano-enabled materials, have significantly enhanced device performance. This review discusses modern applications of paper-based electronics, with a particular emphasis on biosensors, electrochemical and physical sensors, and PFETs designed for flexibility, low power, and high sensitivity. Advances in PFET architectures have further enabled the development of logic gates and memory systems on paper, highlighting the potential for fully integrated circuits. Despite challenges in durability and performance consistency, the field is rapidly evolving, driven by the demand for green electronics and the need for decentralized, point-of-care diagnostic tools. This paper also identifies detection strategies used in paper-based sensors, reviews limitations in the current fabrication methods, and outlines opportunities for the scalable production of multifunctional paper-based systems. This review addresses a critical gap in the literature by linking device-level innovation with real-world sensor applications on paper substrates. Full article

Using novel SiO₂ surface passivation and ultraviolet (UV) light anneal, a 12 nm thick SnO p-type FET (pFET) shows hole effective mobilities (µ_eff) of more than 100 cm²/V·s and 31.1 cm²/V·s at hole densities (Q_h) of 1 × 10¹¹ and 5 × 10¹² cm⁻², respectively. To further improve the on-current/off-current (I_ON/I_OFF), an ultra-thin 7 nm thick SnO nanosheet pFET shows a record-breaking I_ON/I_OFF of 6.9 × 10⁶ and remarkable µ_eff values of ~70 cm²/V·s and 20.7 cm²/V·s at Q_h of 1 × 10¹¹ cm⁻² and 5 × 10¹² cm⁻², respectively. This is the first report of an oxide semiconductor transistor achieving a hole effective mobility µ_eff that reaches 20% of that in single-crystal Si pFETs at an ultra-thin body thickness of 7 nm. In sharp contrast, the control SnO nanosheet pFET without surface passivation or UV anneal exhibits a small I_ON/I_OFF of 1.8 × 10⁴ and a µ_eff of only 6.1 cm²/V·s at 5 × 10¹² cm⁻² Q_h. The enhanced SnO pFET performance is attributed to reduced defects and improved quality in the SnO channel, as confirmed by decreased charges related to sub-threshold swing (SS) and threshold voltage (Vth) shift. Such a large improvement is further supported by the increased Sn²⁺ after passivation and UV anneal, as evidenced by X-ray photoelectron spectroscopy (XPS) analysis. The I_ON/I_OFF ratio exceeding six orders of magnitude, remarkably high hole µ_eff, and excellent two-month stability demonstrate that this pFET is a strong candidate for integration with SnON nFETs in next-generation ultra-high-definition displays and monolithic three-dimensional integrated circuits (3D ICs). Full article

P-type polymer field-effect transistors (PFETs) achieve wide applications due to their environmental compatibility and inherent flexibility. However, the dielectric in PFETs presents a vulnerability that restricts the development of the advancement of p-type power devices and power integrated circuits with high voltage in power devices. In this work, we provide a novel method that employs p-type polymer DPPT-TT high-voltage PFETs with a stair gate dielectric structure (SGD) at both the source and drain sides. The breakdown voltage of this device is significantly increased, rising from 19 V to 80 V. This improvement is attributable to the SGD structure’s ability to reduce the electric field between the source and drain. Although the step gate length (L_SGD) is 50 μm, the on-state resistance only increases by 20% in comparison to conventional devices. The step region contributes an additional resistance of 2.5 × 10⁴ Ω/μm. The operational mechanism of the SGD PFET is demonstrated by TCAD simulations. Full article

Based on the minimum conduction band edge caused by the minimum channel potential resulting from the quasi-3D scaling theory and the 3D density of state (DOS) accompanied by the Fermi–Dirac distribution function on the source and drain sides, a unified semiconductor-device-physics-based ballistic model is developed for the threshold voltage of modern multiple-gate (MG) transistors, including FinFET, Ω-gate MOSFET, and nanosheet (NS) MOSFET. It is shown that the thin silicon, thin gate oxide, and high work function will alleviate ballistic effects and resist threshold voltage degradation. In addition, as the device dimension is further reduced to give rise to the 2D/1D DOS, the lowest conduction band edge is increased to resist threshold voltage degradation. The nanosheet MOSFET exhibits the largest threshold voltage among the three transistors due to the smallest minimum conduction band edge caused by the quasi-3D minimum channel potential. When the n-type MOSFET (N-FET) is compared to the P-type MOSFET (P-FET), the P-FET shows more threshold voltage because the hole has a more effective mass than the electron. Full article

This work demonstrates an enhancement mode heterojunction bipolar p-FET (HEB-PFET) structure with a AlGaN/GaN heterojunction bipolar transistor (HBT) integrated on the drain side. Such device design notably contributes to the ultra-high output current density, which is conventionally limited by the low hole mobility and concentration in the p-FETs. The HEB-PFET exhibits an output current density of 241 mA/mm, which is 134 times larger compared to the conventional p-FET (C-PFET) and 2.4 times of the homojunction bipolar p-FET (HOB-PFET). This can be attributed to a better current gain of HBT than homojunction bipolar transistor (BJT). An optimized HEB-PFET of 6 nm p-GaN layer beneath the gate is proposed, where I_ON/I_OFF is >10¹¹, and V_th is −0.44 V. Additionally, thermal stabilities are studied with temperature changes from 300 K to 425 K. Moreover, a semi-empirical compact model is presented to visually explain the working principle of the HEB-PFET. Full article

In recent decades, the rapid development of the global economy has led to a substantial increase in energy consumption, subsequently resulting in the emission of a significant quantity of toxic gases into the environment. So far, gas sensors based on polymer field-effect transistors (PFETs), a highly practical and cost-efficient strategy, have garnered considerable attention, primarily attributed to their inherent advantages of offering a plethora of material choices, robust flexibility, and cost-effectiveness. Notably, the development of functional organic semiconductors (OSCs), such as poly(3-hexylthiophene-2,5-diyl) (P3HT), has been the subject of extensive scholarly investigation in recent years due to its widespread availability and remarkable sensing characteristics. This paper provides an exhaustive overview encompassing the production, functionalization strategies, and practical applications of gas sensors incorporating P3HT as the OSC layer. The exceptional sensing attributes and wide-ranging utility of P3HT position it as a promising candidate for improving PFET-based gas sensors. Full article

The complementary field-effect transistor (CFET) with N-type FET (NFET) stacked on P-type FET (PFET) is a promising device structure based on gate-all-around FET (GAAFET). Because of the high-density stacked structure, the self-heating effect (SHE) becomes more and more severe. Buried thermal rail (BTR) technology on top of the buried power rail (BPR) process is proposed to improve heat dissipation. Through a systematical 3D Technology Computer Aided Design (TCAD) simulation, compared to traditional CFET and CFET with BPR only, the thermal resistance ($R_{th}$) of CFET can be significantly reduced with BTR technology, while the drive capability is also improved. Furthermore, based on the proposed BTR technology, different power delivery structures of top-VDD–top-VSS (TDTS), bottom-VDD–bottom-VSS (BDBS), and bottom-VDD–top-VSS (BDTS) were investigated in terms of electrothermal and parasitic characteristics. The $R_{th}$ of the BTR-BDTS structure is decreased by 5% for NFET and 9% for PFET, and the $I_{on}$ is increased by 2% for NFET and 7% for PFET. Full article

In this study, we present an intrinsic device parameter method based on a single device for disordered polymer field-effect transistors (PFETs). Charges in disordered polymer semiconductors transport through localized states via thermally activated hopping, of which field-effect mobility and contact resistance are gate-bias-dependent. By considering the parameters expressed as gate bias-dependent power laws, dividing drain current with transconductance (I_ds/g_m method) leads to the current–voltage relation decoupled from the contact effect. Following this derived relationship, the intrinsic field-effect mobility and the contact resistance of the PFETs are extracted and found to be consistent with those using the four-probe method. Thus, we can state that the proposed method offers practical benefits for extracting the intrinsic device parameters of disordered PFETs in terms of using a single transfer characteristic of the devices. Full article

This study proposed a novel source/drain (S/D) extension scheme to increase the stress in nanosheet (NS) field-effect transistors (NSFETs) and investigated the scheme by using technology-computer-aided-design simulations. In three-dimensional integrated circuits, transistors in the bottom tier were exposed to subsequent processes; therefore, selective annealing, such as laser-spike annealing (LSA), should be applied. However, the application of the LSA process to NSFETs significantly decreased the on-state current (I_on) owing to diffusionless S/D dopants. Furthermore, the barrier height below the inner spacer was not lowered even under on-state bias conditions because ultra-shallow junctions between the NS and S/D were formed far from the gate metal. However, the proposed S/D extension scheme overcame these I_on reduction issues by adding an NS-channel-etching process before S/D formation. A larger S/D volume induced a larger stress in the NS channels; thus, the stress was boosted by over 25%. Additionally, an increase in carrier concentrations in the NS channels improved I_on. Therefore, I_on increased by approximately 21.7% (37.4%) in NFETs (PFETs) compared with NSFETs without the proposed scheme. Additionally, the RC delay was improved by 2.03% (9.27%) in NFETs (PFETs) compared with NSFETs using rapid thermal annealing. Therefore, the S/D extension scheme overcame the I_on reduction issues encountered in LSA and significantly enhanced the AC/DC performance. Full article

Herein, we report the fabrications of high-performance polymer field-effect transistors (PFETs) with wire bar-coated semiconducting polymer film as an active layer. For an active semiconducting material of the PFETs, we employed cyclopentadithiophene-alt-benzothiadiazole (CDT-BTZ) that is a D-A-type-conjugated copolymer consisting of a repeated electron-donating unit and an electron-accepting unit, and the other two CDT-based D-A-type copolymer analogues are cyclopentadithiophene-alt-fluorinated-benzothiadiazole (CDT-FBTZ) and cyclopentadithiophene-alt-thiadiazolopyridine (CDT-PTZ). The linear field-effect mobility values obtained from the transfer curve of the PFETs fabricated with the spin-coating were 0.04 cm²/Vs, 0.16 cm²/Vs, and 0.31 cm²/Vs, for CDT-BTZ, CDT-FBTZ, and CDT-PTZ, respectively, while the mobility values measured from the PFETs with the wire bar-coated CDT-BTZ film, CDT-FBTZ film, and CDT-PTZ film were 0.16 cm²/Vs, 0.28 cm²/Vs, and 0.95 cm²/Vs, respectively, which are about 2 to 4 times higher values than those of the PFETs with spin-coated films. These results revealed that the aligned molecular chain is beneficial for the D-A-type semiconducting copolymer even though the charge transport in the D-A-type semiconducting copolymer is known to be less critical to the degree of disorder in film. Full article