Search Results (1,030)

Diamond has emerged as a promising ultrawide-bandgap semiconductor material for next-generation electronics because of its unique combination of a wide bandgap, high critical electric field, superior carrier transport properties, exceptionally high thermal conductivity, and strong chemical and radiation stability. Over the past two decades, progress in crystal growth, substrate engineering, surface control, dielectric integration, and device fabrication has advanced diamond electronics beyond early proof-of-concept demonstrations. The review connects material properties, growth, doping, defects, and figures of merit with reported performance in hydrogen-terminated field-effect transistors, MOSFETs, Schottky and p–i–n diodes, and related power-device architectures. Emerging opportunities in ultraviolet photodetectors, multifunctional electronics, and memory-oriented diamond devices are also briefly considered. Among the device classes reviewed, diamond diodes currently show the strongest evidence of high-voltage capability, whereas transistor development remains constrained by threshold-voltage control, normally off operation, contact resistance, interface stability, and reliability. Diamond is therefore more likely to complement than replace established SiC and GaN technologies, particularly in specialized high-field, high-temperature, radiation-rich, and chemically demanding applications. Broader deployment will require scalable low-defect wafers, reliable n-type doping, stable interfaces and contacts, and more cost-effective manufacturing. Full article

Optical MOS solid-state relays provide electrical isolation and favorable switching performance, making them suitable as isolated switching interfaces for optoelectronic sensors used in radiation monitoring systems, high-energy physics accelerator monitoring systems, and aerospace electronic equipment. However, to the best of our knowledge, the reliability of this device under atmospheric-like neutron irradiation has not been systematically investigated. In this study, the neutron-induced degradation characteristics and potential physical mechanisms of a commercial optical MOS solid-state relay were systematically investigated through electrical characterization, Sentaurus TCAD mixed-mode simulation, and post-irradiation annealing experiments. Particular attention was paid to the possible internal coupling relationship between degradation of the internal photoelectric conversion unit and the increase in the off-state leakage current of the output-side power MOSFET. Full article

This paper reviews and discusses the behavioural modelling techniques used to simulate the dynamic behaviour of switching metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs) employed in power electronic converters. It is necessary to develop efficient, accurate and computationally fast models for simulating the efficiency and power losses of power converters used in modern applications such as electric vehicles (EVs), solar photovoltaic (PV) systems, wind turbines (WTs) and other energy systems. In this context, the paper focuses on the approaches used to estimate the switching losses of these devices. The paper discusses the main differences, advantages, and drawbacks of the behavioural modelling methods presented in the literature including average models, charge-based models, and other physical models. The paper focuses on the Miller Plateau phenomenon in these devices, as it plays a major role in calculating the switching losses of power electronic converters. The paper provides a comprehensive review of the different modelling methods in terms of accuracy, computational effort, execution speed, and feasibility for hardware-in-the-Loop (HiL) systems. The paper also discusses the modern data-driven methods and their potential integration into future power electronic systems. At the end, the review identifies some research gaps and highlights promising directions for future behavioural modelling research. Full article

Owing to the stringent reliability requirements of silicon carbide (SiC) MOSFETs, conventional gate-driving methods with fixed parameters are no longer sufficient to ensure reliable operation under varying operating conditions. To address this issue, this study proposes an adaptive gate-driving method based on model prediction dealing with operating conditions. First, the influence of operating conditions on crosstalk is comprehensively analyzed, starting with an explanation of the crosstalk mechanism. Then, a two-variable behavioral model is established to estimate the amplitude of the crosstalk voltage under the specified operating condition. Based on this prediction model, a lightweight optimization algorithm is developed to select the negative gate turn-off voltage according to the operating conditions. Finally, a double-pulse test platform is built to validate the proposed dynamic gate-voltage selection strategy. The experimental results show that, compared with the fixed −3 V turn-off voltage scheme, the proposed method selects the optimal turn-off voltage of −2 V under specific operating conditions, which can reduce unnecessary negative gate-voltage stress while maintaining the gate-source voltage within the allowable range. Additionally, the measured turn-off loss of the proposed method is 172.7 μJ, lower than the 222.3 μJ loss of the parallel gate-source capacitance method, indicating a better trade-off between crosstalk suppression and switching loss. The proposed behavioral model requires only 69.5 microseconds to predict positive and negative crosstalk peaks, whereas the analytical model requires 46.6 milliseconds. The low computational burden makes the proposed method suitable for potential real-time implementation on resource-constrained microcontrollers. Full article

This paper proposes a single-stage common-ground series-capacitor-compensated buck–boost inverter (CG-SCC-BBI) for wide-input DC–AC applications. Featuring a common-ground neutral and a series-blocking film capacitor, the topology inherently suppresses high-frequency common-mode leakage-current excitation and blocks the structural DC offset. To counteract frequency-dependent voltage attenuation caused by the output network, a fundamental-frequency equivalent model is derived to pre-scale the modulation reference and fully restore output voltage amplitude. The four-switch power stage operates with single-active-leg PWM, confining high-frequency switching to a single half-bridge at any instant to significantly reduce the switching-loss budget. Furthermore, by eliminating the conventional line-frequency output filter choke and utilizing film capacitors exclusively, the topology completely avoids electrolytic capacitors, thereby enhancing long-term operational reliability and lifespan. The proposed inverter supports seamless transition between boost and buck operating modes across the entire input-voltage range. Its operating principles are validated through time-domain simulations, and these were experimentally verified on a 300 W SiC MOSFET standalone laboratory prototype. Experimental results confirm correct operation from 95 V to 400 V DC input, achieving maximum measured efficiencies of 96.79% at the rated 300 W under low-input operation and 97.66% at the rated 300 W under high-input operation, while maintaining an output-current total harmonic distortion (THD) below 2.5%. Full article

Remaining useful life (RUL) prediction of power semiconductor devices plays a crucial role in reliability design and predictive maintenance of power control system. This article introduces a data-driven methodology on predicting the RUL of the gate oxide layer in silicon carbide (SiC) MOSFETs. Firstly, a power cycling platform is established to collect the time-varying curves of threshold voltage and construct an aging dataset. Then, the successive variational mode decomposition (SVMD) algorithm is employed to adaptively decompose the signal of gate threshold voltage, helping suppress measurement noise and fluctuations caused by operating conditions while retaining degradation features. Subsequently, a Temporal Convolutional Network (TCN) is adopted to capture temporal dependencies in the degradation sequence, thereby improving the characterization of gate oxide health status assessment. Finally, the extended Kalman particle filter (EKPF) is employed to estimate the degradation state and quantify the associated uncertainty by recursively fusing model predictions with real-time measurements. The proposed method integrates the adaptive signal decomposition capability of SVMD, the temporal feature extraction capability of TCN, and the uncertainty quantification capability of EKPF. Their complementary integration improves prediction accuracy and robustness in gate oxide degradation evaluation for SiC MOSFET. Full article

Single-event burnout (SEB) remains a persistent threat to SiC power MOSFETs in space, yet rapid evaluation of SEB susceptibility without costly heavy-ion campaigns is challenging. This work demonstrates that femtosecond laser two-photon absorption (TPA) can fill that role for a commercial 1200 V SiC MOSFET—provided the laser energy is correctly mapped to heavy-ion linear energy transfer (LET). We derive an equivalent LET model that incorporates the thermal spike effect, giving LET_eq = Γ₁E₀² + Γ₂E₀⁴, which corrects the classical square law at high excitation intensities where it fails. Three ionization-driven failure signatures emerge: drain-to-gate and drain-to-source single-event leakage current (SELC), and SEB. The SEB threshold saturates near 500 V once LET exceeds 25 MeV·cm²/mg—roughly 42% of the device’s 1200 V rating. From these thresholds, we define a safe operating area: below 200 V is safe, 200–600 V risks SELC degradation, and above 600 V carries high SEB risk. Benchmarking against published heavy-ion data shows SEB threshold agreement within 15%, and within 5% at high LET. We stress that the TPA method captures ionization-driven effects only; it does not replicate displacement damage. These results support rapid, laser-based screening of SiC power devices for radiation hardness. Full article

High-output-current boron-doped diamond (B-diamond) metal–oxide–semiconductor field-effect transistors (MOSFETs) with a modulated boron-doped epitaxial layer were fabricated. An intrinsic diamond epitaxial layer was deposited on the single-crystal diamond substrate as a buffer layer, and plasma-enhanced chemical vapor deposition (PECVD) SiO₂ was employed as both the gate dielectric and passivation layer. The boron-doped epitaxial layer has a thickness of approximately 500 nm and a boron concentration in the range of 10¹⁷–10¹⁸ cm⁻³. The B-diamond MOSFETs showed clear p-channel operation, with a maximum output current of −0.18 mA/mm at room temperature. When the temperature was increased to 150 °C, the maximum output current increased to −1.05 mA/mm, while the on-resistance decreased from 413.91 to 12.13 kΩ·mm. The on/off ratio remains approximately 10⁵ over the measured temperature range. In addition, the device exhibited a breakdown voltage of −347 V at a gate-to-drain spacing of 12.5 μm, and the simulation results showed that the peak electric field was mainly concentrated near the drain-side gate edge of the passivation layer. These results indicated that, for the B-diamond MOSFETs, a balanced epitaxial layer thickness and boron concentration were essential for achieving sufficient channel conduction as well as effective gate control ability. Full article

Linear transformer drivers (LTDs) offer significant advantages for pulsed power applications, but solid-state implementations typically rely on MOSFETs or IGBTs that impose current handling limitations. Thyristors provide substantially higher current handling capability compared to other solid-state switches, making them highly attractive for high-current pulsed-power LTDs. However, because they cannot be turned off through gate control, conventional pulse-width modulation is not possible, limiting their use in applications that require tunable pulse durations. This paper presents a method for achieving pulse width control in thyristor-switched LTDs by exploiting controlled magnetic core saturation. By varying the magnetic reset applied to the cores prior to discharge, the available flux swing and the resulting output pulse duration can be precisely controlled. A 10-stage thyristor-switched LTD was designed and constructed to validate this approach, utilizing SP245-03 thyristors and nanocrystalline magnetic cores. The results demonstrate continuous pulse width control from 540 ns to 1.7 µs at nominal 10 kV output voltage, with the output pulse duration exhibiting a linear relationship with applied reset time up to core saturation. The measured maximum pulse width agrees well with theoretical predictions based on Faraday’s law. This work demonstrates that thyristor-based LTDs can achieve flexible pulse width modulation while benefiting from the higher current ratings these devices offer, enabling new design possibilities for high-current pulsed power systems. Full article

This paper presents the design and experimental investigation of an indirect regenerative evaporative cooling (IREC) system based on the M-cycle concept for electronic systems operating in high ambient temperature. The proposed heat exchanger consists of dry and wet vertical channels separated by thin copper walls and equipped with an open-water reservoir located at the bottom of the cooler. Airflow is introduced into the dry channels, where it is pre-cooled and directed toward a heat source. Next, it is redirected into the wet channels in a counter-flow arrangement. The heat source consists of power MOSFET transistors operating in current-source mode, with enhanced convective heat transfer achieved through attached heat sinks. Temperature and relative humidity sensors were installed at key measurement points to monitor thermodynamic conditions in the exchanger. The findings demonstrate the potential of the IREC approach as an effective and energy-efficient solution for cooling electronic systems in elevated temperature environments. Full article

Hafnium-zirconium oxide (HZO)-based ferroelectric field-effect transistors (FeFETs) are expected to become core devices for new embedded memory and compute-in-memory systems. However, existing simulations rely on finite-element-based TCAD tools, which are computationally intensive and time-consuming, and they struggle to account for the dynamic flipping of ferroelectric domains. This paper utilizes a time-domain simulation framework based on the nucleation-limited switching (NLS) model coupled with the surface potential of a MOSFET, enabling a self-consistent solution for polarization and electrical characteristics; a Monte Carlo method is employed to simulate device variability, and Shmoo plots are used to identify optimal programming and erasure process windows; an integrated solution is proposed for 22 nm FDSOI devices, addressing geometric scaling, modification of the Landau–Khalatnikov (L-K) dynamic model for ultrathin ferroelectric layers, and suppression of short-channel effects. Model validation is limited to selected operating metrics, and predictive accuracy outside the calibrated cases requires additional independent datasets. This method enables end-to-end simulation of FeFETs, from material polarization and device electrical characteristics to performance optimization, thereby providing model-based analytical and design support for the development of advanced, ultra-low-power FeFETs. Full article

The parameter degradation and failure mechanisms of 1200 V asymmetric trench-type (AT) silicon carbide (SiC) metal oxide semiconductor field-effect transistors (MOSFETs) under various single and repetitive surge currents, with various gate bias voltages (V_GS) of 0 V, −5 V, and −10 V, are systematically investigated in this work. It is indicated that V_GS has no impact on the single surge reliability, with the same maximum single surge current (SSC_max) under different V_GS. However, during repetitive surge stress (90% and 60% SSC_max), the maximum surge cycles have increased as V_GS increases from −10 V to 0 V. It may be caused by the enhancement of channel-assisted leakage conduction, allowing more surge current to flow through the channel. It is concluded from gate capacitance (Cg-Vg) and low-frequency noise (LFN) characterizations that lower V_GS increases SiC/SiO₂ interface defect density, accelerating parameter degradation during single and repetitive surge stress. Both chip and package failures are observed for single and repetitive surge stress. For single surge stress, the device failure has resulted from the melted source Al as the metal erodes and penetrates through the interlayer dielectric and the ohmic contact layer between the source metal and the SiC-doped region, respectively, leading to a three-terminal short circuit. For repetitive surge stress, the device failure has been caused by the penetration of Al metal into the interlayer dielectric, leading to a gate-source short circuit. This comprehensive research provides valuable guidance for enhancing the surge reliability of SiC MOSFETs. Full article

This work presents the design and characterization of a portable UV-B phototherapy system based on 308 nm LEDs, intended as a compact and mercury-free alternative for vitiligo treatment. Optical measurements showed a narrow emission centered at 308 nm, with stable spectral behavior and an optical power of approximately 1 mW at the treatment surface, comparable to conventional mercury and excimer lamps but without their associated environmental and thermal issues. A matrix of nine AlGaN UV-B LEDs was used to improve illumination uniformity and compensate for the lower output of individual devices. The electronic system includes an operational amplifier, a MOSFET driver, and a GaN photodiode-based transimpedance amplifier (TIA), allowing real-time UV-B monitoring and closed-loop intensity control. An FPGA-based interface enables precise adjustment of exposure time, duty cycle, and LED selection for localized treatment. Moreover, the system is inherently scalable, as the irradiation area and output power can be increased by adding more LEDs without major changes to the control system. The biological evaluation indicated that UV-B exposure did not affect fibroblast viability under recommended conditions, while signs of DNA damage appeared only at higher intensities and longer exposure times. These results suggest that the system can be used safely within controlled limits. Future work will focus on dose–response studies in clinically relevant models to assess therapeutic effectiveness. Full article

Parallel DC/DC converter modules provide a feasible approach for achieving power scalability in various power conversion systems. This paper investigates an MOSFET-based lagging leg series diodes phase-shift full-bridge (LLSD-PSFB) converter and proposes a three-loop current-sharing control strategy for coordinated parallel operation. The strategy incorporates a voltage loop, a current loop, and a current-sharing loop to mitigate load current imbalance caused by MOSFET parameter mismatches and module inconsistencies. The operating principle and parameter design of the single-module LLSD-PSFB converter are analyzed, and an averaged model is established. Based on this model, a small-signal model of the parallel system is derived to evaluate system stability and current-sharing performance. Simulation results demonstrate that the proposed control scheme effectively improves current-sharing accuracy and dynamic response. An experimental prototype is developed to validate the theoretical and simulation results. The experimental results confirm that the proposed three-loop control strategy achieves high current-sharing precision and stable operation, demonstrating its effectiveness for parallel DC/DC converter systems and its potential for scalable high-power applications. Full article

This paper proposes an Active Gate Driver (AGD) for a DC–DC boost converter based on Silicon Carbide (SiC) power devices, in which surge voltage and ringing arise from their fast-switching characteristics. In this work, a practical and simple 4-bit logic AGD was proposed to adjust the gate resistance during the Miller interval of the SiC MOSFET. This helps suppress these effects and lowers the surge voltage and ringing stress on the power device. Experimental results demonstrate that the voltage overshoot decreases from 52 V to 22 V, corresponding to a reduction from 52% to 22% under a 100 V output condition, while the peak drain–source voltage decreases from 152 V to 122 V. The turn-off energy increases from 60.2 µJ to 76.9 µJ due to the slightly reduced switching speed. This trade-off represents the improvement in the comparison between transient suppression and switching loss. In addition, the voltage ringing is significantly attenuated. Although the modified switching strategy slightly increases switching loss, it effectively improves waveform quality and reduces voltage stress. These results confirm that the proposed AGD provides a simple and effective solution for improving the switching robustness and reliability of SiC-based DC–DC boost converters. Full article