Core-Saturation Control for Tunable Pulse Widths in Thyristor-Switched Linear Transformer Drivers

Abstract

Linear transformer drivers (LTDs) offer significant advantages for pulsed power applications, but solid-state implementations typically rely on MOSFETs or IGBTs that impose current handling limitations. Thyristors provide substantially higher current handling capability compared to other solid-state switches, making them highly attractive for high-current pulsed-power LTDs. However, because they cannot be turned off through gate control, conventional pulse-width modulation is not possible, limiting their use in applications that require tunable pulse durations. This paper presents a method for achieving pulse width control in thyristor-switched LTDs by exploiting controlled magnetic core saturation. By varying the magnetic reset applied to the cores prior to discharge, the available flux swing and the resulting output pulse duration can be precisely controlled. A 10-stage thyristor-switched LTD was designed and constructed to validate this approach, utilizing SP245-03 thyristors and nanocrystalline magnetic cores. The results demonstrate continuous pulse width control from 540 ns to 1.7 µs at nominal 10 kV output voltage, with the output pulse duration exhibiting a linear relationship with applied reset time up to core saturation. The measured maximum pulse width agrees well with theoretical predictions based on Faraday’s law. This work demonstrates that thyristor-based LTDs can achieve flexible pulse width modulation while benefiting from the higher current ratings these devices offer, enabling new design possibilities for high-current pulsed power systems.

1. Introduction

Linear transformer drivers (LTDs) represent a relatively recent advancement in pulsed power technology. Originally developed in 1997 by a Russian research institution [1], LTDs have since undergone rapid evolution and are increasingly being explored as a promising solution to various challenges in pulsed power systems [2,3,4,5]. LTDs work by utilizing a central transmission line to add individual voltage waveforms linearly, creating an output pulse that is the combination of each individual stage’s contributions. For this voltage adding to occur, a magnetic core is utilized on each stage. The magnetic core functions as a high-impedance choke, effectively inhibiting current flow through the magnetizing path [6]. This behavior contrasts with the conventional transformer model, where energy transfer occurs primarily through coupled primary and secondary windings.

Solid-state LTDs (SSLTDs) commonly utilize MOSFETs and IGBTs as switching devices, mainly due to their controllable pulse width modulation [7,8,9]. However, these devices impose fundamental limitations on system performance, particularly in high-current applications where their current ratings require paralleling multiple devices or restricting the operation parameters [10]. A comparison of representative switching technologies reported in the literature, together with the number of devices required to achieve a given current rating, is summarized in

Table 1. LTD Switch Comparison.

Parameter	SP245-03 (This Work)	SiC MOSFET [11]	Representative IGBT [12]
Peak Voltage	1.4 kV	3.3 kV	5 kV
Peak Surge Current	3.5 kA	100 A	1.2 kA
Gate turn-off	No	Yes	Yes
Devices for 35 kA	10	350	30

.

Thyristors, despite offering higher current handling capabilities, are not commonly utilized. The primary reason for their limited integration in LTDs is due to their inability to be directly turned off through gate control, preventing straightforward pulse length modulation. Unlike MOSFETs and IGBTs that can be turned off directly, thyristors are required to remain in their conducting state until the current through the device falls below the device-specific holding current, making precise pulse width control challenging.

However, LTD topology provides an alternative means of pulse control that bypasses the inherent thyristor limitation. In LTDs, the maximum pulse duration is fundamentally limited by the magnetic flux swing of the cores. In this study, we deliberately exploit this flux-limited constraint as the primary means of pulse-width control, representing a novel use of LTD topology. In MOSFET-based designs, it is common to avoid saturating these cores, as the resulting current surge can damage components. As such, the switches are turned off before saturation is reached and the internal current path impedance collapses. This is not required for thyristor SSLTD operation. With careful design, the higher current-handling capability of the thyristor devices can be intentionally leveraged to accommodate the large currents that arise during magnetic core inductance collapse. This paper presents the design, implementation, and experimental validation of a 10-stage thyristor-switched LTD, demonstrating pulse width control from 540 ns to $1.7$ μs through controlled magnetic core saturation.

2. Pulse Width Control Methodology

Controlling the flux swing within a magnetic core’s operation is not a novel concept in LTD operation. Nearly all LTD systems operate with some form of magnetic reset between discharge pulses to optimize output performance. The fundamental purpose of reset in these systems is to establish the initial magnetic state of the cores prior to the pulse.

The magnetic state of a core can be described by its position on the B-H hysteresis curve, shown in Figure 1. Following a discharge pulse, the core settles at the remanent flux density, $B_r$. To achieve the desired flux swing $\mathsf{\Delta }B$, the reset is utilized to shift the core’s flux position on the B-H curve from $B_r$ to $B_{reset}$. When a pulse is subsequently applied, the resulting field drives the core’s flux upward along the curve. Once the applied magnetic field no longer produces a proportional increase in the core’s flux, at $B_{sat}$, the core saturates, effectively terminating the pulse output to the load. This results in the overall flux swing being:

$$\mathsf{\Delta }B=B_{sat}-(B_r-B_{reset})$$

(1)

Hence, the total achievable output pulse duration before core-saturation occurs follows from Faraday’s law:

$$\tau ={\displaystyle \frac{N·A_c·\mathsf{\Delta }B}{V_{core}}}$$

(2)

where N is the number of turns wound on the core ($N=1$ for the standard LTD), $A_c$ is the effective cross-sectional area of the core, and $V_{core}$ is the voltage across the core during discharge.

Pulse width control is achieved by varying $B_{reset}$ anywhere between $-B_{sat}$ and $B_{sat}$. A short reset pulse produces a small $\mathsf{\Delta }B$, resulting in a shorter output pulse. Longer reset pulses yield longer output pulses, with an approximately linear relationship over the usable operating range of the core. In this system, active reset is provided by a set of pulse-reset boards stacked in the same manner as the LTD stages themselves, although the same function could alternatively be integrated by including the reset circuitry directly into each stage. The reset voltage $V_{reset}$ is applied for a duration $t_{reset}$, driving the core flux to the desired $B_{reset}$:

$$B_{reset}={\displaystyle \frac{V_{reset}·t_{reset}}{N·A_c}}$$

(3)

While this technique provides effective pulse width control, fundamental limitations exist to the overall length of the output pulse. The maximum pulse width is constrained by the magnetic core’s saturation characteristics. Because the core cannot be driven below $-B_{sat}$, the maximum achievable flux swing is:

$$\mathsf{\Delta }{B}_{max}=2·B_{sat}$$

(4)

The minimum pulse width depends on both timing considerations and the specific magnetic core utilized. Under normal conditions, the lower limit for the pulse length is the flux swing from $B_r$ to $B_{sat}$, or the swing that occurs when no reset is applied. If the inter-pulse spacing between the reset pulse and the LTD output pulse becomes too large, the core relaxes back toward $B_r$, establishing an effective minimum as the core will remain at $B_r$ unless further manipulated. By positioning $B_{reset}$ between $B_r$ and $B_{sat}$, followed by a shorter delay before the LTD output pulse, the core has no time to relax to $B_r$, and the pulse can effectively be shortened beyond the current minimum. However, this approach was not explored in the presented work due to limitations with the reset boards. During LTD operation, the reset board is triggered first, followed by a 15 μs delay. Following this delay the main board is triggered, as illustrated in Figure 2.

One of the limiting factors in this approach is the required current capability of the switching device. Once saturation occurs, the individual stage sees a very small impedance, essentially short-circuiting the on-board capacitors. This discharges the remaining energy within the storage capacitors as a very high current pulse. In MOSFET-based systems, switches are actively turned off before saturation occurs, preventing damage from the resulting current surge. Thyristor-based and gas-switched LTDs cannot be actively switched off, so the system must be designed to handle the entire current surge.

3. System Design and Implementation

A 10-stage LTD was constructed to validate the magnetic reset control methodology. Each stage contains 10 parallel bricks, arranged radially around a central transmission line. The complete assembly for this device is shown in Figure 3.

The brick schematic is shown in Figure 4. Each brick utilizes the Solidtron/Teledyne SP245-03 thyristor as its main switching device [13], with key ratings summarized in

Table 2. SP245-03 Datasheet Ratings [13].

Parameter	Rating
Peak Voltage	1.4 kV
Off-State Rate of Voltage Change Immunity (dv/dt)	1 kV/µs
Peak Surge Current	3.5 kA
Rate of Change of Current (di/dt)	100 kA/µs

. These switches are capable of $1.4$ kV with a surge current capability of $3.5$ kA. Each switch discharges a 692 nF ceramic capacitor bank into the central transmission line. The stage design uses 10 bricks in parallel, allowing it to handle a theoretical maximum peak surge current of 35 kA.

The capacitors utilized are 220 nF ceramic capacitors, with 14 placed in parallel on each brick. The capacitors use a class II dielectric material with a voltage coefficient of capacitance that causes over $90\%$ capacitance reduction at the full charge voltage of $1.2$ kV. Based on the total energy of the system, as a result of the capacitance reduction, the brick has an effective capacitance of 692 nF. A current limiting resistor, $R1$, was added in series with the main current path. During testing, the combination of capacitance and board design resulted in saturation currents that exceeded the switches’ $I^{2}t$ threshold. Through simulation, the resistor values were chosen as the minimum resistance required to reduce the saturation current below this threshold. $R1$ consists of six $4.7$ $\mathsf{\Omega }$ resistors, resulting in a total resistance of $0.78$ Ω for each brick and an equivalent stage resistance of 78 mΩ. For an X-stage generator, the total equivalent series resistance is X times the stage resistance. This series resistance reduces the output voltage seen by the load. However, high-impedance loads are less affected by this voltage drop than lower-impedance loads. It should be noted that if a greater amount of capacitive energy is initially available, a higher resistance value may be required to keep the saturation current within safe operating levels.

The energy penalty introduced by $R1$ can be quantified in two phases of operation. During the flat-top portion of the pulse, the total equivalent series resistance for all stages forms a voltage divider with the load, dissipating a fraction of the output power in the resistors. For the 10 $\mathsf{\Omega }$ load, this amounts to approximately 7% of the total output power, decreasing to 1.5% for the 50 $\mathsf{\Omega }$ load. By comparison, losses introduced by parasitic resistances in the circuit board are relatively minor. Once the stage impedance collapses, the energy remaining in the storage capacitors is deposited primarily in $R1$, rather than in the switch. This dissipation is the purpose of resistor $R1$, which is sized to keep the post-saturation current below the switch’s $I^{2}t$ rating. Further energy analysis can be found in Section 4.2.

The magnetic cores are MK Magnetics nanocrystalline cores utilizing the FT-3W-M Metglas material [14]. These cores have a saturation flux density of 1.18 T. The core utilized in this LTD design had the following dimensions: OD = 118.7 mm, ID = 33.7 mm, and a height of 28 mm. The total cross-sectional area of this core is $9.53$ cm². These cores have an effective packing factor of 0.78, resulting in the effective area being $7.43$ cm² [11]. These cores were selected for their square B-H loop characteristics, which provide sharp saturation transitions and minimize core related losses.

The circuit shown in Figure 5 provides reset control for this LTD. Once triggered via $V_{trig}$, the circuit applies a pulse to the magnetic core through a single-turn winding. This pulse amplitude is determined by the voltage set by $V_{reset}$. The current reset board, with a 20 V reset voltage applied to the capacitor, will deliver $0.84$ V to the core for the allotted time. This requires longer reset times than would be needed if the full voltage were delivered. This will be further discussed in Section 4.4. The reset board is triggered first, driving the core’s operating point to the desired location. After a 15 μs pulse delay, the main board is triggered. Further details on reset control implementation and timing effects may be found elsewhere [11].

With the maximum operating voltage of $1.2$ kV, the theoretical maximum pulse width is $1.44$ μs when operating from the maximum reset. The minimum pulse width for this core, assuming relaxed to $B_r$, would be 365 ns. The majority of data were taken at a charging voltage of 1 kV. When driving a low impedance load, e.g., 10 $\mathsf{\Omega }$, with the LTD, the voltage drop across the limiting resistors amounts to about 100 V at 1 kV charging, leaving 900 V to drive each core. At this voltage the pulse width would provide a maximum and minimum of ∼2 μs and 487 ns, respectively. When utilizing a 50 $\mathsf{\Omega }$ load, the core experiences a 975 V potential, resulting in a maximum and minimum pulse width of $1.8$ μs and 495 ns.

4. Results

4.1. LTD Design Verification

The 10-stage LTD was operated with charging voltages ranging from 100 V to $1.2$ kV and with the reset voltage set to 20 V. Output voltage diagnostics were collected using an in-house built voltage probe for voltages below 8 kV and a Northstar PVM-4 (North Star High Voltage, Bainbridge Island, WA, USA) for higher voltages. Current diagnostics were collected via a Pearson Model 2879 (Pearson Electronics, Palo Alto, CA, USA). All waveforms were recorded on a RIGOL DS7024 (RIGOL Technologies, Suzhou, China) with 2 GSa/s. Reset timing and initial triggers were generated with a Berkeley Nucleonics Corporation Model 575 trigger generator (Berkeley Nucleonics Corp., San Rafael, CA, USA). The reset pulse was applied, followed by a 15 μs delay before the main discharge trigger. All experiments were performed at room temperature. Core heating resulting from magnetic losses was not observed to be significant during testing, which is attributed to the low duty-cycle operating conditions employed.

Using magnetic core saturation to control pulse width causes the switch to conduct a very high current once the stage impedance collapses. Figure 6 shows a representative waveform acquired during testing, showing both the output current and the current through the switches. As the core saturates and the stage impedance collapses, the current through the switch spikes rapidly, in this experiment peaking at 12 kA, while this peak current does not exceed the switch’s absolute maximum rating, the spike duration results in an $I^{2}t$ value higher than the switch’s rated limit. This current spike is the primary reason MOSFET switches are turned off before saturation occurs, as current at this level would destroy most other semiconductor switches utilized in LTD designs.

4.2. High Current Operation

One of the defining points of using thyristors is the ability to withstand high currents, enabling the ability for the LTD to drive lower impedance loads. To demonstrate the high-current capabilities of the thyristor-switched LTD, the system was operated without the current-limiting resistors by reducing the stage capacitance to an effective capacitance of $1.32$ μF. This reduced capacitance allowed the thyristors to operate below the $I^{2}t$ threshold without requiring series resistance. Figure 7 shows the output voltage and current waveforms for a 3-stage configuration driving a 3 $\mathsf{\Omega }$ load at 1 kV charging voltage. The device delivers a peak current of approximately 925 A to the load, corresponding to a peak power of $2.56$ MW. This current level exceeds the per-stage current ratings typical of MOSFET-based LTD designs of comparable stage count [11].

Further testing utilized a shorted load, roughly 23 nH, to demonstrate the peak current capability of the three-stage lower capacitance configuration. Figure 8 shows the resulting output current waveform at $1.2$ kV charging voltage. Under these conditions, the device delivered a peak current of approximately $19.75$ kA. This corresponds to each switch experiencing a surge current of $1.98$ kA. This per-switch current at the time applied is below the $I^{2}t$ threshold and resulted in no visible degradation to the switches when operated at this level.

With the full effective stage capacitance of 692 nF, the stored energy per stage reaches $4.95$ J at $1.2$ kV charging, producing post-saturation currents that greatly exceed the switch $I^{2}t$ rating, as shown in Figure 6. In simulation, the inclusion of $R1$ reduces the peak saturation current from 12 kA to $7.68$ kA, bringing the deposited $I^{2}t$ below the device rating. This is at the cost of the majority of the post-saturation energy dropping across the resistors rather than the switches and slightly lowering the amplitude of the output pulse. Reducing the stage capacitance to the values shown in Figure 7 and Figure 8 allows for the saturation current to remain within the $I^{2}t$ rating without the use of any series resistance. One should note, however, that a reduced capacitance will cause a considerable droop in the output voltage waveform at longer pulse durations for low-impedance loads. Alternatively, more switches could be paralleled per stage, which would allow further reduction of the series resistance. Ultimately, the design involves a trade-off between capacitance, switch count, circuit complexity, and desired pulse performance.

4.3. LTD Thyristor Pulse Width Modulation

Figure 9 demonstrates the linear voltage addition as multiple stages are added to the device at 1 kV charging voltage. During this operation, a 500 μs reset pulse width was applied to the cores. Within this figure, waveforms are shown for various stage numbers, indicating that the LTD works as intended. The 10-stage output achieves approximately 8.9 kV peak voltage with a rise time of 15 ns. The current design of the board utilizes on-board resistors to limit peak current, extending the lifetime of the switches. These resistors introduce losses, resulting in a lower than expected voltage at the load.

By shifting the total reset time applied to each core at a constant charging voltage, the relationship between pulse width and reset time can be shown. Figure 10 shows this relationship, with listed reset times next to each respective output signal. These were acquired using 10 stages, 1 kV charging voltage, and a 15 μs reset time to trigger pulse delay.

The shortest pulse width achieved is 538 ns at a reset time of 25 μs. The longest pulse width nears $1.71$ μs, achieved with a reset time greater than $1.5$ ms. This approaches our theoretical maximum of $1.798$ μs calculated using Equation (2). The slight discrepancy can be mainly attributed to unmodeled parasitics and the fact that the full voltage does not appear across the core. The pulse width, recorded as a function of applied reset time and analyzed in Section 4.4, exhibits two regions that are expected. The first region is the linear region, existing from $t=0$ s to $t\approx 1.5$ ms. In this region an increase in applied reset time results in an equally linear increase in the output pulse width. In the saturation/non-linear region longer pulses result in no increased pulse width. This relationship is expected and matches the behavior of magnetization in magnetic cores and Equation (2).

Across the full reset-time sweep shown in Figure 10, the peak output amplitude remained stable at approximately $9.7$ kV with a standard deviation of $50.5$ V across all reset settings. This indicates that the reset state of the magnetic cores controls the pulse duration without significantly affecting the delivered voltage amplitude.

As discussed in Section 2, the minimum pulse length depends not only on the saturation point but also on the reset-to-trigger delay. As the inter-pulse spacing decreases, the core has less time to relax back to the remanent point. As such the linear portion of this region continues until reset times smaller than 25 μs, and will continue in linear fashion until $t=0$. Pulses shorter than $t=0$ require that the core is biased to a point between $B_r$ and $B_{sat}$. This requires a reset pulse of inverted amplitude compared to the reset pulses utilized to drive the core to below $B_r$ normally.

While experimental verification of sub-500 ns operation was not performed, the achievable range can be estimated from Equation (2). In principle, as $B_{reset}$ approaches $B_{sat}$, the available flux swing $\mathsf{\Delta }B$ approaches zero, and the pulse width is bounded only by the output rise time. Using the parameters of Figure 10 fit ($V_{core}$ = 975 V, $A_c$ = $7.43$ cm²), biasing the core to $0.8$ T would yield a predicted width of 289 ns, and biasing to 1 T would yield 140 ns. In practice, three main factors establish a floor much greater than the LTD rise time of 15 ns. The first is the quality of the pulse; as $\mathsf{\Delta }B$ decreases, the saturated portion of the falling edge occupies a larger fraction of the total pulse. This will degrade the flat top before a true square pulse is formed. The second limitation is timing precision. There is a finite delay between the reset pulse and the LTD output pulse. To implement this technique effectively, that delay must be both short and highly repeatable to ensure that the core does not relax back toward $B_r$ before the main pulse arrives. The final requirement is an inverted-polarity reset drive, while the unipolar reset boards used in this work cannot bias the core beyond $B_r$ in the required direction; extension of the tunable pulse-duration range into the 100–500 ns regime is readily achievable through the use of a bipolar reset supply combined with tighter trigger-timing control.

4.4. Pulse Width Fitting

Matching the magnetic core’s response to the relationship between output pulse width and reset time requires consideration of several factors. During testing, it was found that a reset pulse of $0.84$ V was physically applied to the core. The reduction from the 20 V capacitor charge voltage to the measured $0.84$ V is a consequence of the board’s output impedance. The current-limiting resistor, $R_{lim}$, is the dominant impedance on the discharge path with a value of 4 $\mathsf{\Omega }$. With the added 1 $\mathsf{\Omega }$ switch resistance, the unsaturated core presents a relatively low impedance at the timescale of interest. As a result, most of the source voltage is dropped across $R_{lim}$ and the switch, leaving approximately $0.84$ V across the winding. This divider behavior is stable over the entire reset duration, as indicated by the flat top present in Figure 11, so the volt-second product delivered to the core remains linear with $t_{reset}$ and Equation (3) remains valid. The energy cost of the reset process can be found to be 104 mJ, with the core needing $4.37$ mJ to reach $-B_{sat}$. The resistance of $R_{lim}$ was set such that the core current would be 4 A; lowering this resistance would apply a higher voltage to the core and increase the speed at which the core reset would take place. For a voltage of $0.84$ V, it was found that if a reset pulse was applied for longer than $1.3$ ms, the core would reach $-B_{sat}$, as shown in Figure 11. Within this figure, saturation can be seen to occur at approximately $t=$ $-750$ μs. As a result, any increase in reset pulse width beyond $1.3$ ms would result in no increase in overall pulse width.

During testing and analysis of experimental results, it was found that the remanent flux density did not match the expected levels from the manufacturer datasheet. After saturation, the collapsing field induces a negative voltage transient that forward-biases the diode, shunting the remaining capacitor energy while providing a small reverse current that resets the core’s operating point to below the remanent flux density. As a result, the post-pulse operating point becomes:

$$B_{r_{pulse}}=B_r-B_{reverse}$$

(5)

where $B_r$ is $0.7$ T according to the manufacturer datasheet for the magnetic material [14]. The value of $B_{reverse}$ can be determined by integrating the reverse voltage experienced by the core. Figure 12 displays both the output pulse and the voltage across the magnetic core. As the output voltage collapses, the core experiences a voltage transient, resulting in a shift in the core’s operating point. For the 10 $\mathsf{\Omega }$ load case, integration of the post-pulse voltage reversal across the core yields a reverse flux density change of 0.113 T, resulting in an effective pulse operating point of $0.59$ T using Equation (5). When operating with the 50 $\mathsf{\Omega }$ load, the higher load impedance results in a greater fraction of the supply voltage appearing across the core during the voltage reversal, producing a correspondingly greater reverse flux swing. Direct measurement of the 50 $\mathsf{\Omega }$ reversal transient was not performed in this configuration. However, fitting Equation (2) to the experimentally measured pulse widths shown in Figure 13 yielded an effective post-pulse operating point of $0.53$ T, corresponding to a reverse flux change of 0.17 T. This value is consistent with the expected increase in reverse swing and shows good agreement with the experimental pulse width data across the full linear region. The deviation of the post-pulse operating point is consistent with the permeability behavior observed during excitation reversals in magnetic cores. Wan et al. demonstrates this effect through a Preisach-based hysteresis model of LTD, in which the core’s permeability decreases sharply when the excitation direction reverses, causing the flux to follow a first-order reversal curve rather than the main B-H loop [15]. This behavior results in the post-transient operating point differing from the specified datasheet values. Additionally, recent work by Kelp et al. on modeling pulsed magnetic core behavior has shown that traditional circuit models fail to capture the magnetization-rate-dependent response of nanocrystalline cores under pulsed operation, further supporting the need for empirical parameter extraction in situations such as these [16].

Figure 13 plots the measured pulse widths from Figure 10 and compares them against the theoretical predictions from Equation (2). Two distinct regions are evident in this graph: a linear region before saturation occurs on the reset and a region post-saturation. The linear section allows for direct increases in reset duration to result in an equal increase in pulse width, determined by Equation (2). This region shows good matching with results from Equation (2). Beyond this point the LTD reaches its maximum possible pulse length due to reaching the maximum flux swing found in Equation (4). Shorter pulses are also possible but require biasing the core in the opposite direction prior to the output pulse, but that was unexplored in this work.

Although the pulse-width sweep of Figure 10 was acquired with the 50 $\mathsf{\Omega }$ load, the voltage scaling predicted by Equation (2) can be validated against the 10 $\mathsf{\Omega }$ data of Figure 9, where approximately 900 V appear, across each core. For the 500 μs reset applied during the experiment, Equation (3) yields $B_{reset}=$ $0.565$ T. Together with the measured operating point of $0.59$ T, this corresponds to a flux swing of $\mathsf{\Delta }B=$ $1.155$ T, equivalent to a volt-second capacity of 858 V · μs. Integrating the measured ten-stage output waveform from turn-on to saturation results in 723 V · μs per stage, corresponding to a flux swing of $0.974$ T. The discrepancy is largely attributable to the pronounced voltage droop observed with the 10 $\mathsf{\Omega }$ load. Unlike the nearly flat-topped pulses obtained with the 50 $\mathsf{\Omega }$ load, the 10 $\mathsf{\Omega }$ waveform does not maintain a constant voltage throughout the pulse, making the measured FWHM of 852 ns a conservative estimate of the actual saturation-limited pulse duration.

5. Conclusions

This paper demonstrated a practical method for achieving pulse width control in thyristor-switched linear transformer drivers through the utilization of controlled magnetic core saturation. Unlike MOSFET and IGBT-based systems that rely on active switch turn-off for pulse termination, the presented approach exploits the inherent flux-limited behavior of LTD magnetic cores, allowing thyristors to be used as the switching device despite the switch’s lack of gate-controlled turn-off capabilities.

A 10-stage LTD was designed and characterized to validate the proposed methodology. Each stage incorporated 10 parallel bricks utilizing SP245-03 thyristors as the main switching device. The system achieved pulse width modulation experimentally from 540 ns to $1.7$ μs at 1 kV charging voltage by varying the reset pulse duration applied to the magnetic core prior to discharge. This range corresponds closely with theoretical limits imposed by the core’s magnetic properties and the system limitations. Two distinct operating regions were identified: a linear region in which the pulse width increases proportionally with reset time and a saturation region where additional reset duration produces no further increases in pulse width. Within this saturation region, additional reset duration produces no further increase in the output pulse width. Within the linear region, good agreement was shown between experimental results and Faraday’s law.

The primary design consideration for this control methodology is managing the high saturation current that occurs when the stage’s impedance collapses. The current design addresses this through the addition of resistors added in-line with the main current path of the LTD, trading a slightly reduced output voltage for improved switch lifetime. Additionally, high current operation was demonstrated using a reduced capacitance 3-stage configuration without current limiting resistors. This arrangement delivered 925 A into a 3 $\mathsf{\Omega }$ load and $19.75$ kA into a shorted load. These results confirm that the thyristor-switched LTD can reliably operate into very low impedance loads, a regime where MOSFET-based designs would require extensive device paralleling to avoid exceeding switch ratings. Long-term reliability under repeated saturation-current stress, including the effects of extended cycling on thyristor performance and core remanence, remains an area for future investigation. Nevertheless, all thyristors were operated within their manufacturer-specified operating limits, suggesting substantial margin with respect to device stress. Scaling the present approach to output voltages well beyond 10 kV is expected to be limited primarily by the larger number of series stages required, which effectively reduces the output capacitance and increases flat-top droop for low-impedance loads, and secondarily by the dielectric strength of the compact output transmission line. Beyond thyristor-based systems, this pulse width control approach could apply directly to gas-switched LTDs, which similarly lack direct pulse-width control. This work establishes that thyristor-switched LTDs with magnetic reset control offer a viable path towards high-current pulsed power systems with flexible pulse width modulation, combining the current handling advantages of thyristors with the control flexibility previously only found with MOSFET and IGBT-based LTD designs.