Search Results (180)

High-density (HD) quasi-cyclic low-density parity-check (QC-LDPC) codes are widely adopted in high-speed, high-reliability optical communication systems. However, the high density of the quasi-cyclic parity-check matrix prevents the direct derivation of a corresponding quasi-cyclic generator matrix, leading to computationally prohibitive encoding complexity. To address this limitation, based on the established polynomial-ring representation of QC-LDPC codes, this paper develops a structure-preserving polynomial-domain transformation for the high-density 50G-PON QC-LDPC parity-check matrix. The proposed method transforms the dense quasi-cyclic parity-check matrix into a compact systematic encoding form over $R={\mathbb{F}}_2\left[x\right]/(x^{256}-1)$. As a result, parity generation is reduced to the inversion of a small $3\times 3$ polynomial submatrix and a sequence of cyclic-shift-and-XOR operations. Based on this construction, an optimized HD-QC-LDPC encoding algorithm and its corresponding FPGA architecture are developed. The resulting hardware encoder achieves a throughput of 58.9 Gbps at a 200 MHz clock frequency on a Xilinx Kintex-7 FPGA, satisfying the throughput and latency requirements of 50G-PON systems. Full article

To obtain efficient channel codes with high power efficiency at moderate signal-to-noise ratios (SNRs), an efficient high-rate protograph quasi-cyclic (QC) low-density parity-check (LDPC) codes is optimally constructed. By an optimized protograph template, the code framework is firstly produced by the extensions of the variable nodes. By enlarging the dimension of the sub-matrices related to the protograph framework, the base QC matrix template is generated with required code rate and length by the extrinsic information transfer (EXIT) chart for better decoding threshold. Then, the elements in the base matrix are split with even smaller square sub-matrices of the same row and column weights. In this procedure, a progressive-edge-growth (PEG) algorithm is employed to find the optimized positions of the QC sub-matrices to obtain larger girth for better error floor performance. Moreover, an asymptotic weight distribution (AWD) is employed to keep a low-code-error floor for the code. Also the circulant offsets in all QC sub-matrices are optimally searched by a QC oriented nested loop approximated cycle extrinsic message degree (QC-NLACE) algorithm, which improves the relationship of the unavoidable loops in the code’s Tanner graph to cut the error floor. Simulation results show that the codes produced by the proposed method show quite good bit-error-rate (BER) performance. In addition, they exhibit good properties of high spectrum efficiency brought by the high code rate, and the low complexity by the short code length. Moreover, a series of different rate-compatible LDPC codes can be generated from the same protograph framework with some variable node extensions, which significantly eases the code design. Therefore, the proposed code construction can be efficiently applied in the optimal construction of high-rate and short-length rate-compatible QC-LDPC codes with a high data rate and rational complexity, which makes the codes extremely suited for use in new-generation power-constrained wireless communications. Full article

Tanner quasi-cyclic low-density parity-check (QC-LDPC) codes form an important family of structured LDPC codes with favorable girth properties. This paper studies the girth of Tanner $(2, L)$-regular QC-LDPC codes (referred to as Tanner QC-LDPC cycle codes) for arbitrary integers $L>2$ and develops a novel algebraic number theoretic method to determine the girth for all sufficiently large primes p with $p\equiv 1\left(\mathrm{mod}2L\right)$. We first analyze the case $L=3$ and prove that the girth is 12 for every prime $p\equiv 1\left(\mathrm{mod}6\right)$ through exhaustive resultant computations. We then extend the method to arbitrary L and obtain a clear classification: when L is even, the girth is exactly 8 for all admissible primes; when L is odd, the girth attains the maximum value 12 for all sufficiently large admissible primes. The proof transforms cycle existence conditions into polynomial equations and applies resultant theory. This approach converts the infinite task of checking all primes into a finite set of algebraic checks. Numerical simulations show that the Tanner $(2, 5)$-regular non-binary code over $\mathrm{GF}\left(64\right)$ achieves a coding gain of approximately $0.2$ dB over the 5G LDPC code of equivalent binary length. Full article

Four-edge type low-density parity-check (FET-LDPC) codes, as an important subclass of multi-edge type LDPC codes, offer greater design flexibility and performance potential due to their heterogeneous edge type structure. However, their multi-dimensional degree distribution significantly increases the complexity of optimization. This paper proposes a joint optimization framework for FET-LDPC codes leveraging the symmetric decoding structure inherent in their dual-branch architecture. The main contributions are as follows. First, an improved decoding model is established to analyze the mutual information transmission among the four edge types during iterative decoding, where the symmetry between the accumulator (ACC) and single parity-check (SPC) branches facilitates balanced information exchange. Second, a full-dimensional extrinsic information transfer (FEXIT) chart suitable for FET-LDPC codes is constructed, capturing the mutual information flow across branches. Third, a collaborative optimization model is designed by integrating the FEXIT chart with multi-constraint linear programming (LP) to perform asymmetric optimization for different edge types. The simulation results show that the proposed method achieves significant performance improvement over unoptimized codes in additive white Gaussian noise (AWGN) channels, particularly at a bit error rate (BER) of 10⁻⁶. Full article

A proper vertex coloring is equitable if the sizes of any two color classes differ by at most one. Any graph G with maximum degree $\Delta \left(G\right)$ admits an equitable $\left(\Delta \left(G\right)+1\right)$-coloring, computable in $O(\Delta \left(G\right)n^2)$ time for n vertices. A circulant graph $G(n;D)$ is the graph with vertex set ${\mathbb{Z}}_n$ and two vertices $x,y$ are adjacent if $|x-y|\in \pm Dmodn$. The partitioning problem in parallel decoding of multi-edge QC-LDPC codes can be interpreted as an equitable coloring problem. We prove some upper bounds for ${\chi }_{=}\left(G(n;D)\right)$ and develop equitable coloring algorithms, including pattern-based periodic coloring and step-based coloring. The proposed methods typically use fewer than $\Delta \left(G\right)+1$ colors and have computational complexity lower than $O(\Delta \left(G\right)n^2)$ for circulant graphs $G(n;D)$ with small $\left|D\right|$. Full article

To improve the decoding performance of multi-edge type low-density parity-check (MET-LDPC) codes, this paper proposes an edge-type differentiated parameter coupling offset min-sum (EDPC-OMS) decoding algorithm. The contributions are threefold. First, we replace the traditional uniform compensation with edge-type differentiated compensation, resolving the mismatch between the decoding model and code structure. Second, we introduce a parameter coupling mechanism that enables joint optimization of multiple edge types while maintaining differentiated configurations. Third, a practically feasible design combining precomputation and look-up tables enables dynamic parameter adjustment with moderate additional overhead, achieving a favorable performance–complexity trade-off. Simulation results over additive white Gaussian noise (AWGN) channels and Rayleigh fading channels demonstrate that the proposed algorithm adaptively selects offset factors according to channel conditions and edge types without introducing significant computational complexity, effectively lowering the bit error rate and enhancing decoding capability. Full article

Driven by the development of next-generation wireless networks and the widespread adoption of sensing, communication is shifting from traditional bit-level transmission to intelligent, rich interactions within our digital social system. However, existing speech semantic communication frameworks predominantly focus on textual accuracy, neglecting the critical affective information (e.g., tone and emotion) that is essential for natural human-centric interactions in the real world. To address this limitation, we propose the Heterogeneous Affective Speech Semantic Communication (HASCom) framework, designed for the robust transmission of highly expressive speech over complex wireless channels. Specifically, we design a heterogeneous dual-stream transmission architecture that decouples discrete phoneme-level linguistic content from continuous emotional embeddings. For discrete semantic information, we use reliable digital coding protected by Low-Density Parity-Check (LDPC) to guarantee strict recoverability. Conversely, for emotional features, we employ Deep Joint Source-Channel Coding (JSCC) analog transmission to prevent irreversible quantization errors and the cliff effect. Additionally, we develop a prior-guided diffusion reconstruction module at the receiving end. This module leverages a structural prior network to align the decoded semantics, which then steers the reverse diffusion process conditioned on the recovered affective features. Extensive experiments under both AWGN and Rayleigh fading channels demonstrate that HASCom significantly outperforms state-of-the-art baselines. Specifically, it achieves superior objective semantic similarity and subjective Mean Opinion Score (MOS) at low Signal-to-Noise Ratios (SNRs), while the JSCC transmission modules maintain an ultra-low inference latency of less than 0.1 ms, validating its high efficiency and robustness for practical deployments. Full article

In the realm of high-speed Ethernet networks, alien crosstalk (AXT) significantly undermines the integrity and efficiency of data transmission. While existing works mostly focus on modeling and physical-layer mitigation techniques such as PAM16/DSQ128 modulation and LDPC coding, there is a lack of experimental evidence on how severe AXT affects commodity 10GBASE-T equipment in realistic, densely cabled installations. In this study, we assemble and evaluate the experimental testbed that emulates a highly adverse AXT environment by tightly bundling up to seven 60 m twisted-pair Ethernet cables and using only off-the-shelf 10GBASE-T network cards. We quantitatively characterize how increasing cable density leads to automatic speed downgrades, connection failures, and non-linear saturation of the aggregate throughput, and relate these effects to the observed link quality on individual ports. Our results demonstrate that, even in the presence of standard crosstalk mitigation and error-correction mechanisms, severe AXT can force commodity 10GBASE-T links to fall back from 10 Gbit/s to 1 Gbit/s or below. Based on these findings, we derive practical guidelines for dense-cabling deployments and identify key requirements for experimental testbeds that can more reliably quantify AXT severity and its impact on commodity 10GBASE-T link stability (rate fallback and link loss) under realistic conditions. Full article

To offer multi-edge type low-density parity-check (MET-LDPC) codes with better performance, this paper proposes a regional message scaling min-sum (RMS) decoding algorithm which improves the performance of the traditional min-sum (MS) decoding algorithm and its modified versions. The contributions of this study are as follows. First, based on the edge-type topology of MET-LDPC codes, we fully exploit their inherent structural information to develop a cross-region decoding architecture by dynamically partitioning the edges of the Tanner graph into three functional regions. Second, we introduce cross-region message scaling (CMS) factors to establish an asymmetric information flow control mechanism, which adaptively regulates the intensity of information exchange across regions. Third, by integrating the multi-edge structure, the cross-region decoding architecture, and the asymmetric information flow control mechanism into a unified framework, we propose the RMS decoding algorithm tailored for MET-LDPC codes. For various code lengths, simulation results demonstrate that the proposed algorithm achieves a significantly lower error floor compared to the traditional MS decoding algorithm and its modified versions over the additive white Gaussian noise (AWGN) channel. Full article

This paper addresses the design and performance analysis of nonorthogonal multiple access (NOMA) for ultra-dense networking of the Internet of Things (IoT) based on low-power sensors. The proposed NOMA schemes consist of an $N_r$-antenna access point and K single antenna sensors given $K\gg N_r$. A power allocation technique and forward error correction (FEC) are combined to enable concurrent uplink transmission and the successful separation of all K sensors at the access point. In scenarios where $K\gg N_r$, large dimensional analysis is employed to derive a deterministic expression for the received signal-to-interference-plus-noise ratio (SINR) within the finite blocklength regime. Three distinct Forward Error Correction (FEC) codes—convolutional codes (CCs), polar codes, and low-density parity-check codes (LDPCs)—are assessed. These evaluations indicate that all three codes achieve near-capacity performance while supporting massive connectivity in the finite-blocklength context. Notably, convolutional codes demonstrate comparable performance with reduced complexity, a desirable attribute for prolonging the life cycle of wireless sensor network-based IoT applications. Full article

To address the limitations of static message aggregation and training instability in the existing Shared Neural Normalized Min-Sum (SNNMS) algorithm, this paper proposes A-SNNMS, an attentive deep LDPC decoding network with adaptive training. First, an attention mechanism is introduced into the variable node update phase to dynamically weight incoming messages based on their reliability, effectively suppressing noise interference. Second, a collaborative training scheme incorporating an exponential decay adaptive learning rate and L2 regularization is designed to mitigate convergence oscillation and overfitting in long-code training. Simulation results for IEEE 802.16e standard codes demonstrate that A-SNNMS achieves a net coding gain of approximately 0.4 dB over the baseline SNNMS at a Bit Error Rate (BER) of 10⁻³. Furthermore, it achieves comparable performance with only 50% of the iterations required by the baseline. In conclusion, the A-SNNMS decoder significantly improves both decoding efficiency and system robustness, offering a promising solution for high-reliability communications. Full article

We propose a reinforcement learning (RL)-based decoding framework for high-throughput parallel decoding of low-density parity-check (LDPC) codes using clustered scheduling. Parallel LDPC decoders must balance error-correction performance and decoding latency while avoiding memory conflicts. To address this trade-off, we construct clusters of check nodes that satisfy a two-edge independence property, which enables conflict-free row-parallel belief propagation. An RL agent is trained offline to assign Q-values to clusters and to prioritize their update order during decoding. To overcome the exponential storage requirements of existing RL-based scheduling methods, we introduce the Q-Sum method, which approximates cluster-level Q-values as the sum of Q-values of individual check nodes, reducing storage complexity from exponential to linear in the number of check nodes. We further propose an On-the-Fly clustering strategy that enforces two-edge independence dynamically during decoding and provides additional flexibility when static clustering is not feasible. Simulation results for array-based LDPC codes over additive white Gaussian noise (AWGN) channels show that the proposed methods improve the latency-versus-performance trade-off of parallel LDPC decoders, achieving lower decoding latency and higher throughput while maintaining error rates comparable to state-of-the-art decoding methods. Full article

This paper presents a hardware-efficient field-programmable gate array (FPGA) implementation of a layered two-dimensional corrected normalized min-sum (2D-CNMS) decoder for quasi-cyclic low-density parity-check (QC-LDPC) codes in very small aperture terminal (VSAT) satellite communication systems. The decoder is described in C++ and synthesized using the Xilinx Vitis high-level synthesis (HLS) 2025 (AMD Xilinx, San Jose, CA, USA) tool, and then packaged and integrated as an intellectual property (IP) core within the Vivado Design Suite 2024 (AMD Xilinx, San Jose, CA, USA), enabling rapid prototyping and portability across FPGA platforms. Unlike conventional normalized min-sum (NMS) and two-dimensional normalized min-sum (2D-NMS) architectures, the proposed 2D-CNMS scheme employs dyadic, multiplier-free normalization combined with two-level magnitude correction, achieving near sum-product performance with reduced complexity and latency. The design is implemented on a Zynq UltraScale+ multiprocessor system-on-chip (MPSoC) (AMD Xilinx, San Jose, CA, USA) and supports real-time operation with a throughput of 29–41 Mbps at 100 MHz, while using only 9.6–22.4 k look-up tables (LUTs), 2.1–5.9 k flip-flops (FFs), and no digital signal processing (DSP) slices or block random-access memories (BRAMs). Bit-error-rate (BER) simulations over an additive white Gaussian noise (AWGN) channel show no error floor down to ${10}^{-8}$. These results demonstrate that the proposed HLS-based 2D-CNMS IP core provides a resource-efficient, high-performance LDPC decoding solution as compared with existing LDPC implementation approaches. This LDPC solution targets performance enhancement in wireless communication systems and has been deployed on a multi-frequency time-division multiple-access (MF-TDMA) satellite link to assess its overall behavior, demonstrating improved performance with reduced resource usage. Full article

The development and use of large-scale quantum computers relies on integrating quantum error-correcting (QEC) schemes into the quantum computing pipeline. A fundamental part of the QEC protocol is the decoding of the syndrome to identify a recovery operation with a high success rate. In this work, we implement a decoder that finds the recovery operation with the highest success probability by mapping the decoding problem to a spin system and using Population Annealing to estimate the free energy of the different error classes. We study the decoder performance on a 4.8.8 color code lattice under different noise models, including code capacity with bit-flip and depolarizing noise, and phenomenological noise, which considers noisy measurements, with performance reaching near-optimal thresholds for bit-flip and depolarizing noise, and the highest reported threshold for phenomenological noise. This decoding algorithm can be applied to a wide variety of stabilizer codes, including surface codes and quantum Low-Density Parity Check (qLDPC) codes. Full article

This paper proposes a symmetrized extrinsic information transfer (S-EXIT) chart analysis for probabilistic shaped (PS) systems to optimize the joint decoding of low-density parity-check (LDPC) codes and constant composition distribution matchers (CCDMs). A major challenge in analyzing PS systems is the non-uniform channel input caused by shaping, which invalidates the all-zero assumption of traditional EXIT charts, coupled with the three-node structure of the joint decoder (variable nodes, check nodes, and shaping nodes) that exceeds the two-decoder framework of conventional EXIT analysis. To resolve these issues, we first prove the symmetry of the joint decoder and introduce a “symmetrized density” transformation to render the channel output symmetric, thereby enabling the extension of EXIT chart analysis to PS systems. We then approximate the EXIT function of the shaping node decoder via polynomial fitting and integrate it with the variable node decoder into a unified model (VSND) for threshold analysis. On one hand, the proposed S-EXIT chart provides a theoretical threshold for the joint decoder, which is crucial for guiding system design. On the other hand, it enables the joint optimization of LDPC code rates and CCDM rates, unlocking additional performance gains. Simulations over additive white Gaussian noise (AWGN) channels demonstrate that short-blocklength CCDMs (e.g., blocklength 20) achieve up to 1.2 dB gain over uniform systems via S-EXIT-based rate optimization. This work addresses the performance limitations of short-blocklength CCDMs in high-speed optical transmissions, offering a practical and efficient analytical tool for PS system design. Full article