Search Results (14)

Improving financial time series forecasting presents challenges because models often struggle to identify diverse fault patterns in unseen data. This issue is critical in fintech, where accurate and reliable forecasting of financial data is essential for effective risk management and informed investment strategies. This work addresses these challenges by initializing the weights and biases of two proposed models, Gated Recurrent Units (GRUs) and the Echo State Network (ESN), with different chaotic sequences to enhance prediction accuracy and capabilities. We compare reservoir computing (RC) and recurrent neural network (RNN) models with and without the integration of chaotic systems, utilizing standard initialization. The models are validated on six different datasets, including the 500 largest publicly traded companies in the US (S&P500), the Irish Stock Exchange Quotient (ISEQ) dataset, the XAU and USD forex pair (XAU/USD), the USD and JPY forex pair with respect to the currency exchange rate (USD/JPY), Chinese daily stock prices, and the top 100 index of UK companies (FTSE 100). The ESN model, combined with the Lorenz system, achieves the lowest error among other models, reinforcing the effectiveness of chaos-trained models for prediction. The proposed ESN model, accelerated by the Kintex-Ultrascale KCU105 FPGA board, achieves a maximum frequency of $83.5$ MHz and a power consumption of $0.677$ W. The results of the hardware simulation align with MATLAB R2025b fixed-point analysis. Full article

The increasing interest shared by academia and industry in the development of RISC-V cores, extensions and accelerators becomes fructified by collaborative efforts, like the EU’s ChipsJU, which leverages the design of building blocks, IPs and cores based on RISC-V architecture. A domain capable of benefiting from the RISC-V extensibility is the control of external DACs and ADCs. The proposed solution is an open-source RISC-V extension for optimized control of external DACs and ADCs called RiscADA. The extension supports a parametrizable number of DACs and ADCs, is integrated as a coprocessor beside CVA6 in a SoC by using the CV-X-IF interface, deployed on a Kintex UltraScale+ FPGA and implements ISA extension instructions. After benchmarks with commercial solutions, the results show that CVA6 using RiscADA extension configures external DACs 38.6× and 10.9× times faster than MicroBlaze V and simple CVA6, both using AXI SPI peripherals. The proposed extension achieves 5.35× and 3.05× times higher sample rates of external ADCs than the two configurations mentioned above. RiscADA extension performs digital signal conditioning 4.52× and 3.1× times faster than the MicroBlaze V and CVA6, both using AXI SPI peripherals. It computes statistics for external ADC readings (minimum, maximum, simple-moving average and over-threshold duration). Full article

The paper presents an application of the ASMD-FSMD technique for designing high-performance digital circuits on the example of an implementation of sequential multipliers in reconfigurable FPGA devices. The method primarily enables multiple operations on the same variable within a single clock cycle. The experiments were conducted using the QuartusPrime tool and Cyclone 10 LP devices, as well as Vivado tools and the Kintex UltraScale family device. The bit size of multiplicands varied from 4 to 128. A comparison of the ASMD-FSMD technique with the traditional approach using datapath with the controller has shown that the performance of the sequential multipliers increases by a factor of 2 and, for some examples, by a factor of 3. Practical recommendations for using the ASMD-FSMD technique to improve the performance of digital devices, as well as directions for further studies, are given in the conclusion. Full article

This study investigated implementation strategies to optimize the precision of Tapped Delay Line (TDL) Time-to-Digital Converters (TDCs) designed for Xilinx 20 nm UltraScale Field-Programmable Gate Arrays (FPGAs). This optimization process aims to bridge the performance gap between FPGA-based TDCs, which are more flexible and suitable for fast prototyping, and the better-performing Application-Specific Integrated Circuit (ASIC) solutions, making FPGA-based TDCs viable for cutting-edge applications. Our key areas of focus included the optimal design of the decoder, the degree of sub-interpolation, and the placement of TDLs, with particular emphasis on the clocking distribution scheme within the Configurable Logic Block (CLB) to minimize the effects of Bubble Errors (BEs) and quantization error. The research led to the development and comparison of multiple TDL TDC solutions implemented on a Kintex UltraScale device (i.e., XCKU040-2FFVA1156E) housed on a KCU105 general-purpose Evaluation Board (EVB). From these, two main solutions emerged: one with high precision and one with low area. The first one was characterized by a Single-Shot Precision (SSP) of 2.64 ps r.m.s., and by Differential and Integral Non-Linearity (DNL/INL) Errors of 0.523 ps and 16.939 ps, respectively, occupying 883 CLBs and 126 kb of Block RAM (BRAM). The second one had an SSP of 3.75 ps r.m.s., a DNL of 0.599 ps, and an INL of 7.151 ps, and it occupies only 259 CLBs and 72 kb of BRAM. Full article

Data acquisition systems that receive analog signals, convert them to digital, and perform signal processing are used in a variety of systems that use acoustics, radar, sonar, indoor localization, and navigation. The previous systems, such as NI USRP-RIO, are expensive to build, and the number of signals a single device can receive is limited to between two and four. In order to receive more channels of signals, multi-channel data acquisition systems using ADCs operating at tens of MSPS have been proposed. However, these systems require additional processing time because data acquisition and signal processing are performed on different devices. In this paper, we propose a multi-channel data acquisition system using a 16-channel ADC that can support up to 100 MSPS. In particular, to reduce unnecessary signal transmission time, we propose a one-chip structure where all processes are performed on a single chip. Also, we propose a data acquisition system that applies pipelining techniques to enable real-time processing. To verify the proposed system, we used TI ADS52J90 and a Kintex UltraScale KCU105 evaluation board, and confirmed that it is possible to receive and process all channels simultaneously. Furthermore, it is possible to configure a real-time system by adjusting the speed of the signal-processing operation and the speed of the communication interface. Therefore, the proposed system is expected to reduce the cost of system construction by performing signal reception and processing with a single chip, and to reduce the time required for overall signal processing. Full article

Designs of timer function blocks (FBs) are presented in the article. The developed modules are IEC 61131-3. An analysis of IEC 61131-3 in terms of timer functionality and implementation options is presented. Three types are presented, timer-on, timer-off, and timer-pulse, with each type designed to be fully hardware or software-like. Both designs, hardware or software-like, can operate as multi-channel timers. Particularly noteworthy is the software-like design, for which a solution without edge detectors was achieved. Such a feature was obtained by reversing the method of time determination by counting the difference between the start and end times and by using specific features of the D flip-flops, that is, clock-enable inputs. The presented timers were written in Verilog language and implemented in an FPGA chip. Thanks to the universal design of the interface, the proposed FBs can be used for the hardware support of existing programmable logic controllers (PLCs) or as an integral part of newly built PLC CPUs. The idea of a CPU architecture with hardware support is proposed. The paper presents the results of the implementation in an FPGA of the Kintex UltraScale+ family from AMD-Xilinx. Full article

A hardware-efficient implementation of a Low-Density Parity-Check (LDPC) decoder is presented in this paper. The proposed decoder design is based on the Hybrid Offset Min-Sum (HOMS) algorithm. In the check node processing of this decoder, only the first minimum is computed instead of the first two minimum values among all the variable-to-check message inputs as in the conventional approach. Additionally, taking advantage of the unique structure of 5G LDPC codes, layered scheduling and partially parallel structures are employed to minimize hardware costs. Implementation results on the Xilinx Kintex UltraScale+ FPGA platform show that the proposed decoder can achieve a throughput of 2.82 Gbps for 10 decoding iterations with a 5G LDPC codelength of 8832 bits and a code rate of 1/2. Moreover, it yields a check node memory reduction of 10% with respect to the baseline and provides a hardware usage efficiency of 4.96 hardware resources/layer/Mbps, while providing a decoding performance of 0.15 dB better than some of the existing decoders. Full article

The increment in the use of high-resolution imaging sensors on-board satellites motivates the use of on-board image compression, mainly due to restrictions in terms of both hardware (computational and storage resources) and downlink bandwidth with the ground. This work presents a compression solution based on the CCSDS 123.0-B-2 near-lossless compression standard for multi- and hyperspectral images, which deals with the high amount of data acquired by these next-generation sensors. The proposed approach has been developed following an HLS design methodology, accelerating design time and obtaining good system performance. The compressor is comprised by two main stages, a predictor and a hybrid encoder, designed in Band-Interleaved by Line (BIL) order and optimized to achieve a trade-off between throughput and logic resources utilization. This solution has been mapped on a Xilinx Kintex UltraScale XCKU040 FPGA and targeting AVIRIS images, reaching a throughput of 12.5 MSamples/s and consuming only the 7% of LUTs and around the 14% of dedicated memory blocks available in the device. To the best of our knowledge, this is the first fully-compliant hardware implementation of the CCSDS 123.0-B-2 near-lossless compression standard available in the state of the art. Full article

The histogram of oriented gradients is a commonly used feature extraction algorithm in many applications. Hardware acceleration can boost the speed of this algorithm due to its large number of computations. We propose a hardware–software co-design of the histogram of oriented gradients and the subsequent support vector machine classifier, which can be used to process data from digital image sensors. Our main focus is to minimize the resource usage of the algorithm while maintaining its accuracy and speed. This design and implementation make four contributions. First, we allocate the computationally expensive steps of the algorithm, including gradient calculation, magnitude computation, bin assignment, normalization and classification, to hardware, and the less complex windowing step to software. Second, we introduce a logarithm-based bin assignment. Third, we use parallel computation and a time-sharing protocol to create a histogram in order to achieve the processing of one pixel per clock cycle after the initialization (setup time) of the pipeline, and produce valid results at each clock cycle afterwards. Finally, we use a simplified block normalization logic to reduce hardware resource usage while maintaining accuracy. Our design attains a frame rate of 115 frames per second on a Xilinx^® Kintex^® Ultrascale^™ FPGA while using less hardware resources, and only losing accuracy marginally, in comparison with other existing work. Full article

Remote sensing is recognized as a cornerstone monitoring technology. The latest high-resolution and high-speed spaceborne imagers provide an explosive growth in data volume and instrument data rates in the range of several Gbps. This competes with the limited on-board storage resources and downlink bandwidth, making image data compression a mission-critical on-board processing task. The Consultative Committee for Space Data Systems (CCSDS) Image Data Compression (IDC) standard CCSDS-122.0-B-1 is a transform-based 2D image compression algorithm designed specifically for use on-board a space platform. In this paper, we introduce a high-performance architecture for a key-part of the CCSDS-IDC algorithm, the 9/7M Integer Discrete Wavelet Transform (DWT). The proposed parallel architecture achieves 2 samples/cycle while the very deep pipeline enables very high clock frequencies. Moreover, it exploits elastic pipeline principles to provide modularity, latency insensitivity and distributed control. The implementation of the proposed architecture on a Xilinx Kintex Ultrascale XQRKU060 space-grade SRAM FPGA achieves state-of-the-art throughput performance of 831 MSamples/s (13.3 Gbps @ 16bpp) allowing seamless integration with next-generation high-speed imagers and on-board data handling networking technology. To the best of our knowledge, this is the fastest implementation of the 9/7M Integer DWT on a space-grade FPGA, outperforming previous implementations. Full article

This paper reports a field-programmable gate array (FPGA) design of compressed sensing (CS) using the orthogonal matching pursuit (OMP) algorithm. While solving the least-squares (LS) problem in the OMP algorithm, the complexity of the matrix inversion operation at every loop is reduced by the proposed partitioned inversion that utilizes the inversion result in the previous iteration. By the proposed matrix (n × n) inversion method inside the OMP, the number of operations is reduced down from O(n³) to O(n²). The OMP algorithm is implemented with a Xilinx Kintex UltraScale. The architecture with the proposed partitioned inversion involves 722 less DSP48E compared with the conventional method. It operates with a sample period of 4 ns, signal reconstruction time of 27 μs, and peak signal to noise ratio (PSNR) of 30.26 dB. Full article

This paper proposes a method for phase difference measurement based on the principle of progressive phase shift (PPS). A phase difference measurement system based on PPS and implemented in the FPGA chip is proposed and tested. In the realized system, a fully programmable delay line (PDL) is constructed, which provides accurate and stable delay, benefitting from the feed-back structure of the control module. The control module calibrates the delay according to process, voltage and temperature (PVT) variations. Furthermore, a modified method based on double PPS is incorporated to improve the resolution. The obtained resolution is 25 ps. Moreover, to improve the resolution, the proposed method is implemented on the 20 nm Xilinx Kintex Ultrascale platform, and test results indicate that the obtained measurement error and clock synchronization error is within the range of ±5 ps. Full article

Many researchers have explored the relationship between recurrent neural networks and finite state machines. Finite state machines constitute the best-characterized computational model, whereas artificial neural networks have become a very successful tool for modeling and problem solving. The neurally-inspired lateral inhibition method, and its application to motion detection tasks, have been successfully implemented in recent years. In this paper, control knowledge of the algorithmic lateral inhibition (ALI) method is described and applied by means of finite state machines, in which the state space is constituted from the set of distinguishable cases of accumulated charge in a local memory. The article describes an ALI implementation for a motion detection task. For the implementation, we have chosen to use one of the members of the 16-nm Kintex UltraScale+ family of Xilinx FPGAs. FPGAs provide the necessary accuracy, resolution, and precision to run neural algorithms alongside current sensor technologies. The results offered in this paper demonstrate that this implementation provides accurate object tracking performance on several datasets, obtaining a high F-score value (0.86) for the most complex sequence used. Moreover, it outperforms implementations of a complete ALI algorithm and a simplified version of the ALI algorithm—named “accumulative computation”—which was run about ten years ago, now reaching real-time processing times that were simply not achievable at that time for ALI. Full article

Digital cross-correlation is central to many applications including but not limited to Digital Image Processing, Satellite Navigation and Remote Sensing. With recent advancements in digital technology, the computational demands of such applications have increased enormously. In this paper we are presenting a high throughput digital cross correlator, capable of processing 1-bit digitized stream, at the rate of up to 2 GHz, simultaneously on 64 channels i.e., approximately 4 Trillion correlation and accumulation operations per second. In order to achieve higher throughput, we have focused on frequency based partitioning of our design and tried to minimize and localize high frequency operations. This correlator is designed for a Passive Millimeter Wave Imager intended for the detection of contraband items concealed on human body. The goals are to increase the system bandwidth, achieve video rate imaging, improve sensitivity and reduce the size. Design methodology is detailed in subsequent sections, elaborating the techniques enabling high throughput. The design is verified for Xilinx Kintex UltraScale device in simulation and the implementation results are given in terms of device utilization and power consumption estimates. Our results show considerable improvements in throughput as compared to our baseline design, while the correlator successfully meets the functional requirements. Full article