Search Results (34)

When connecting a renewable energy source to a medium-voltage grid, it has to fulfil grid codes and be able to work in a medium-voltage range (>10 kV). Multilevel converters (MLCs) are recognized for their low total harmonic distortion (THD) and ability to work at high voltage compared to other converter types, making them ideal for applications connected to medium-voltage grids whilst being compliant with grid codes and voltage ratings. Cascaded H-bridge multilevel converters (CHBs-MLC) are a type of MLC topology, and they does not need any capacitors or diodes for clamping like other MLC topologies. One of the problems in these types of converters involves the double-frequency harmonics in the DC linking voltage and power, which can increase the size of the capacitors and converters. The use of line frequency transformers for isolation is another factor that increases the system’s size. This paper proposes an isolated CHBs-MLC topology that effectively overcomes double-line frequency harmonics and offers isolation. In the proposed topology, each DC source (renewable energy source) supplies a three-phase load rather than a single-phase load that is seen in conventional MLCs. This is achieved by employing a multi-winding high-frequency transformer (HFT). The primary winding consists of a winding connected to the DC sources. The secondary windings consist of three windings, each supplying one phase of the load. This configuration reduces the DC voltage link ripples, thus improving the power quality. Photovoltaic (PV) renewable energy sources are considered as the DC sources. A case study of a 1.0 MW and 13.8 kV photovoltaic (PV) system is presented, considering two scenarios: variations in solar irradiation and 25% partial panel shedding. The simulations and design results show the benefits of the proposed topology, including a seven-fold reduction in capacitor volume, a 2.7-fold reduction in transformer core volume, a 50% decrease in the current THD, and a 30% reduction in the voltage THD compared to conventional MLCs. The main challenge of the proposed topology is the use of more switches compared to conventional MLCs. However, with advancing technology, the cost is expected to decrease over time. Full article

This study examines the impact of midpoint voltage fluctuations on the performance of multilevel converters and proposes an advanced control strategy to reduce the required DC bus capacitance while maintaining system stability. The research demonstrates that active voltage imbalance control in active neutral-point-clamped (ANPC) topologies allows for stable operation with significantly reduced capacitor values. A hybrid control approach, combining fuzzy logic control and third-harmonic injection PWM (THIPWM), is developed to enhance voltage balancing, and modulation techniques are systematically optimized. Both simulation and experimental analyses confirm the efficacy of the proposed method, which achieves superior voltage regulation compared to conventional PI-based control schemes. Specifically, experimental results show a reduction in peak-to-peak DC-link voltage fluctuation from 116 V to just 4 V, and the phase current THD is reduced from 3.6% to 0.8%. The results indicate a substantial reduction in voltage fluctuations, contributing to a total harmonic distortion (THD) as low as 0.8%. Furthermore, the proposed strategy facilitates an approximate 26-fold decrease in DC bus capacitor size without compromising system stability. The reduction in capacitance not only lowers the overall system costs and hardware complexity but also improves reliability. The inverter was tested at a rated power of 62.5 kW using 0.3 mF capacitors instead of the theoretically required 7.8 mF. This work advances power electronics by presenting an efficient voltage balancing methodology, offering a cost-effective and robust solution for multilevel converter applications. The findings are validated through comprehensive simulations and experimental tests, ensuring practical applicability. Full article

Modular multilevel converter (MMC)-based power electronic transformers (PETs) present a promising solution for connecting AC/DC microgrids to facilitate renewable energy access. However, the capacitor ripple voltage in MMC-based PET submodules hinders volume optimization and power density enhancement, significantly limiting their application in distribution networks. To address this issue, this study introduces an optimized method for suppressing the submodule capacitor ripple voltage in MMC-based PET systems under normal and grid fault conditions. First, an MMC–PET topology featuring upper and lower arm coupling is proposed. Subsequently, a double-frequency circulating current injection strategy is incorporated on the MMC side to eliminate the double-frequency ripple voltage of the submodule capacitor. Furthermore, a phase-shifting control strategy is applied in the isolation stage of the dual-active bridge (DAB) to transfer the submodule capacitor selective ripple voltages to the isolation stage coupling link, effectively eliminating the fundamental frequency ripple voltage. The optimized approach successfully suppresses capacitor ripples without increasing current stress on the isolated-stage DAB switches, even under grid fault conditions, which are not addressed by existing ripple suppression methods, thereby reducing device size and cost while ensuring reliable operation. Specifically, the peak-to-peak submodule capacitor ripple voltage is reduced from 232 V to 10 V, and the peak current of the isolation-stage secondary-side switch is limited to ±90 A. The second harmonic ripple voltage on the LVDC bus can be decreased from ±5 V to ±1 V with the proposed method under the asymmetric grid voltage condition. Subsequently, a system simulation model is developed in MATLAB/Simulink. The simulation results validated the accuracy of the theoretical analysis and demonstrated the effectiveness of the proposed method. Full article

This paper presents a carrier waves phase shifting method to reduce the dc-link capacitor current for a dual three-phase permanent magnet synchronous motor drive system. Dc-link capacitors absorb the ripple current generated at the input due to the harmonics of the pulse width modulation (PWM). The size, cost, reliability, and lifetime of the dc-link capacitor are negatively affected by this ripple current flowing through it. The proposed method is especially appropriate for common dc-link capacitors for a dual inverter system driving two PMSMs. In this paper, the input current of each inverter is analyzed using Double Fourier Analysis, and the harmonic components of the dc-link capacitor current are determined. The carrier wave phase shifting method is proposed to reduce the magnitude of the harmonics and thus reduce the dc-link capacitor current. Furthermore, the optimum angle between the carrier waves for the maximum reduction in the dc-link capacitor current is analyzed and simulated for different scenarios considering the speed and load torque of the PMSMs. The proposed method is verified through experiments and PMSMs are driven by three-phase voltage source inverters (VSIs) modulated with Space Vector Pulse Width Modulation (SVPWM), which is the most common PWM strategy. The proposed method reduces the dc-link capacitor current by 60%, thereby significantly decreasing the required dc-link capacitance, the volume of the drive system, and its cost. Full article

A matrix converter (MC) converts an AC source voltage into a variable-voltage variable-frequency AC output voltage (direct AC-AC) without an intermediate DC-link capacitance. By eliminating the traditional DC-link capacitor, MCs can achieve higher power densities and reliability when compared to conventional AC-DC-AC converters. MCs also offer the following characteristics: total semiconductor solution, sinusoidal input and output currents, bidirectional power flow and controllable input power factor. This paper reviews the history, recent developments and commercialization of MCs and discusses several technical requirements and challenges, including bidirectional switches, wide bandgap (WBG) opportunities using GaN and SiC, overvoltage protection, electromagnetic interference (EMI) and ride-through in motor drive applications. MC design solutions and operation are discussed, including a comparison of control and modulation techniques as well as the detailed development of space vector modulation (SVM) to provide a deep insight into the control implementation and results. The paper concludes with compelling motor drive innovation opportunities made possible by advanced MCs including fully integrated and multiphase systems. For conventional MCs, size reductions of 30% are reported, as well as efficiencies of 98% and low input current total harmonic distortion of 3–5%. Full article

The large size of the sub-module (SM) capacitor is a typical problem in traditional modular multilevel converter-type solid-state transformers (MMC-SSTs). The MMC-SST based on high-frequency link interconnection is an effective solution for achieving lightweight capacitance. This structure can help to eliminate the symmetric SM fluctuating power, thereby reducing the SM capacitance. In a three-phase interconnected MMC-SST with low capacitance, potential risks may arise during transient processes, especially in cases of three-phase voltage asymmetry, such as large fluctuations in the SM voltage and unstable DC bus voltage. Aiming to solve this problem, this article re-analyzes the internal power characteristics of the MMC-SST under asymmetric operation and re-derives the SM capacitance constraint suitable for different degrees of three-phase voltage asymmetry. The new SM capacitance constraint enhances the asymmetric voltage ride-through capability of the MMC-SST. The new capacitance constraint is higher than that in symmetric operation, but it still has significant advantages in capacitance compared with the traditional MMC-SST. Full article

This paper presents a case study in which the influence of the 6-pulse thyristor-bridge input reactor size on the shunt active power filter (SAPF)’s work performance is investigated. The purpose of using an SAPF in the power system is in most cases for fundamental harmonic reactive power compensation, harmonics and asymmetry mitigation. The work efficiency of such a filter depends not only on the designed control system, interface filter and dc-link capacitor parameters, but also on the parameters of the electrical system in which it is connected. Therefore, it is necessary to study and know the power system (supplier and consumer sides) before its installation. For instance, in the electrical system with diode or thyristor-bridge as loads, the SAPF performance efficiency may not be satisfied due to the high rate of current change (di/dt) at the points of commutation notches. In this paper, the performed simulation and laboratory experiments show that for a better operating efficiency of the SAPF, the input reactor parameters should be selected based not only on the effective reduction in the inverter switching ripple or the control system demand, but also on the parameters of the load, such as the parameters of the diode or thyristor-bridge input reactor. Apart from the experimental demonstrations on how the input reactor size influences the SAPF work efficiency, the novelties in this paper are: the formulated recommendations on how to choose the SAPF input reactor parameters (the SAPF is more efficient in terms of harmonics, asymmetry and reactive power mitigation when the inductance of its input reactor (L-filter) is smaller than the one of the diode or thyristor-bridge input reactor); the proposed SAPF control system; the proposed expressions to compute the SAPF input reactor inductance, DC voltage and capacitor. Full article

This paper presents a mathematical analysis of how energy return in grid-connected single-phase photovoltaic systems affects the sizing of passive components. Energy return affects the size of the link capacitor, making it larger than reported in the literature. One of the main points of this article is that an inverter connected to the grid using a DC–DC converter with an appropriate link capacitor is analyzed. The energy return is caused by the value (in Henry units) of the L-filter, which is also analyzed in this paper. The analysis shows that there is a link between the value of the L-filter and the voltage of the DC bus. The analysis assumes two conditions: (1) the DC bus voltage is always higher than the peak value of the grid sinusoidal voltage, and (2) there is a unity power factor at the connection point between the grid and the L-filter. To operate in an open loop, a compensation phase angle is calculated and introduced in the single-phase inverter modulation; this phase angle compensates the phase shift caused by the L-filter, avoiding the use of a phase-locked-loop (PLL) control system. The L-filter ripple current is evaluated by Fourier analysis, and the DC bus ripple voltage is evaluated by considering the energy returned to the link capacitor. The results of the analyses are compared with existing methods reported in the literature. The results also show that, to minimize the value of the L-filter, the DC voltage must be almost equal to the maximum voltage of the grid. Equations to assess the value of the DC-link capacitor and the L-filter in function of their ripples are developed. The results were verified with simulations in Simulink and experimentally. Full article

Cascaded H-bridge drives require using a significant-size capacitor on each cell to deal with the oscillatory power generated by the H-bridge inverter in the DC-link. This results in a bulky cell with reduced reliability due to the circulating second harmonic current through the DC-link capacitors. In this article, a control strategy based on a finite control set model predictive control and a proportional-resonant controller is proposed to compensate for the oscillatory power required by the H-bridge inverter through the cell’s input rectifier. With the proposed strategy, a DC-link second harmonic free operation is achieved, allowing for the possibility of reducing the capacitor size and, in consequence, the cell dimensions. The feasibility of the proposed control scheme is verified by experimental results in one cell of a cascade H-bridge inverter achieving an operation with a capacitance 141 times smaller than required by conventional control approaches for the same voltage ripple. Full article

This paper proposes an analytical formulation-based minimization of DC link current ripples for interleaved parallel inverter systems. Parallel inverter systems find applications in multiple fields. The interleaved superposition of the DC link currents in these systems can potentially be adjusted to mitigate the overall harmonics consequently reducing the DC link capacitor size. To this end, a widely used approach in the literature is the Fourier analysis based on interleaving focusing on dominant harmonic mitigation. However, it leaves room for a generic analytical mechanism to provide time shifts leading to an optimal reduction in DC-link ripples. The goal of this work is to target this optimal reduction by utilizing an analytical mechanism. The paper presents an alternate way of DC-link formulation in terms of the piece-wise sinusoids of inverter output currents for space vector modulation-based systems. The formulation is then used to numerically optimize the interleaved shifts for minimum ripples. Moreover, in addition to the traditional concept of fixed time interleaving, a contemporary concept of sequence-based interleaving is utilized, which is anticipated to have more flexibility in the implementation and additional switching synchronism with PWM rectifiers for back–back converters. Therefore, the sequence interleaving has also been utilized in conjunction with the proposed ripple reduction methodology. Further, an underexplored area of using the combined impact of sequence and time interleaving has also been applied in this work. These interleaving methods are shown to provide significantly improved DC-link ripple mitigation, as compared to existing methods, using numerical assessment followed by simulations and experimental evaluation. Full article

The DC-Link capacitor plays a crucial role as far as power density and reliability are concerned: it occupies approximately 40% of the inverter, and causes approximately 30% of its failures. Asymmetrical dual three-phase (ADTP) multiphase arrangements are gaining relevance in the automotive sector for powertrain applications. This work focuses on reducing the impact that the widely used double zero sequence injection (DZSI) family of PWM techniques have on such a bulky and failure-prone component in an ADTP arrangement by means of interleaving techniques. By using the double Fourier integral formalism, the input current spectra and the overall performance of these PWM techniques have been derived, in terms of current rms value and voltage ripple in the DC-Link capacitor. Simulations have shown that choosing an adequate interleaving scheme and angle considerably relieves both current and voltage stresses on the DC-Link capacitor compared to noninterleaved operation. Reductions of 84% current rms and 86% voltage ripple have been achieved at static operating points. Finally, by averaging the rms current over WLTP standard driving cycle, reductions up to 26% have been obtained under more realistic conditions. All this would enhance the reliability and reduce the size of the onboard capacitors in future electric vehicles. Full article

Traditional three-phase rectifier DC-link inverters have been used in industry for more than 40 years. However, electrolytic capacitors, which are widely used in traditional inverters, have very large volumes and can only be used for five years. To solve this problem, a three-phase small-film DC-link capacitor interior permanent-magnet synchronous motor drive system is investigated in this paper. This small-film capacitor not only has a longer life and smaller size than an electrolytic capacitor, but it can also improve the input harmonic currents and power factor on the grid side. A high-order band-pass filter active damping control is proposed here. In addition, a constrained predictive speed controller is designed to enhance the transient, load disturbance, and tracking speed performance. Furthermore, a constrained predictive current controller is implemented to reduce the three-phase harmonic currents of the motor. A digital signal processor, type TMS-320F-28035, manufactured by Texas Instruments, is employed as a control center to conduct the whole control algorithms. Several simulated and measured results are compared to demonstrate the practicability and correctness of the proposed control algorithms. Full article

Adjustable-speed drives with single-phase input require a power factor correction front-end, usually implemented by a boost converter, to reduce the current distortion from the uncontrolled rectifier; this stage is then followed by a three-phase inverter. Bulky electrolytic capacitors are used to limit the direct current voltage ripple resulting from the rectification of the single-phase input. This leads to increased system size and shorter lifetime. In this work, the usual boost front-end is exploited to actively control the DC link voltage ripple while limiting the input current distortion and, hence, the power factor, even if not reaching unity. However, Power Factor is greatly improved with respect to the uncontrolled rectifier alone. This approach permits one to reduce the required capacitance, allowing the substitution of the electrolytic capacitor with a long-life low-equivalent-series-resistance film one. A control targeting capacitor voltage level, ripple, and boost inductor peak current is presented, together with practical design models. The synergic control of the boost front-end and of the machine drive is presented as well. The resulting converter is tested with resistive load and permanent-magnet synchronous machine drive, highlighting the advantages and limits of the proposed solution. Full article

E-mobility is an emerging means of transportation, mainly due to the environmental impact of petroleum-based fuel vehicles and oil prices’ peak. However, electric vehicles face several challenges by the nature of technology. Consequently, electric vehicles have a limited travel range and are extremely heavy. In this research, an investigation is carried out on different measures to reduce the DC-link capacitor size in the drive train of an electric vehicle. The investigation is based on software simulations. The DC-link capacitor must be dimensioned with regards to relevant points of operation, which are defined by the rotation speed and torque of the motor as well as the available DC-link voltage. This also includes the field-oriented control (FOC). In order to optimally operate a three-phase inverter in the electric drive train, a suitable type and sizing of the capacitor was studied based on mathematical equations and simulations. Two measures were examined in this study: firstly, an auxiliary passive notch filter introduced in the electric drive train circuit is explored. Based on this measure, an advanced modulation scheme exploiting the control of individual currents within segmented windings of the PMSM is investigated in detail. It was seen that saw-tooth carrier modulation used in the parallel three-phase inverter is found to reduce DC-link capacitor size in the electric drive train circuit by 70%. Full article

A three-phase three-wire voltage source converter (VSC) can produce third harmonics when it is operated under an unbalanced condition. It is essential to understand the mechanism of the production of this third harmonic and to assess its impact on power systems. Therefore, this paper presents an analytical model of the VSC under the unbalanced condition through mathematical derivations, and the final model is a coupled Thevenin circuit. The proposed model allows for direct computation of the non-characteristic third harmonics through harmonic power flow studies. The results show that VSC under unbalanced conditions emits both positive-sequence and negative-sequence third harmonics, and that the positive-sequence third harmonic is much larger than the negative-sequence third harmonic. It also shows that the unbalanced level and the size of the dc-link capacitor are critical to the level of non-characteristic third harmonics. The correctness of the proposed model and its application on noncharacteristic third harmonic evaluations have been verified using EMT simulations. Full article