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13 pages, 1729 KiB

Open AccessArticle

Reducing Avalanche Build-Up Time by Integrating a Single-Photon Avalanche Diode with a BiCMOS Gating Circuit

by Bernhard Goll, Mehran Saadi Nejad, Kerstin Schneider-Hornstein and Horst Zimmermann

Sensors 2024, 24(23), 7598; https://doi.org/10.3390/s24237598 - 28 Nov 2024

Viewed by 844

It is shown that the integration of a single-photon avalanche diode (SPAD) together with a BiCMOS gating circuit on one chip reduces the parasitic capacitance a lot and therefore reduces the avalanche build-up time. The capacitance of two bondpads, which are necessary for [...] Read more.

It is shown that the integration of a single-photon avalanche diode (SPAD) together with a BiCMOS gating circuit on one chip reduces the parasitic capacitance a lot and therefore reduces the avalanche build-up time. The capacitance of two bondpads, which are necessary for the connection of an SPAD chip and a gating chip, are eliminated by the integration. The gating voltage transients of the SPAD are measured using an integrated mini-pad and a picoprobe. Furthermore, the gating voltage transients of a CMOS gating circuit and of the BiCMOS gating circuit are compared for the same integrated SPAD. The extension of the 0.35

μ

m CMOS process by an NPN transistor process module enabled the BiCMOS gating circuit. The avalanche build-up time of the SPAD is reduced to 1.6 ns due to the integration compared to about 3 ns for a wire-bonded off-chip SPAD using the same

n^{+}

and p-well as well as the same 0.35

μ

m technology. Full article

(This article belongs to the Special Issue Advanced CMOS Integrated Circuit Design and Application III)

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14 pages, 5297 KiB

Open AccessArticle

Area-Efficient Mixed-Signal Time-to-Digital Converter Integration for Time-Resolved Photon Counting

by Sergio Moreno, Victor Moro, Joan Canals and Angel Diéguez

Sensors 2024, 24(17), 5763; https://doi.org/10.3390/s24175763 - 4 Sep 2024

Viewed by 1352

Abstract

Digital histogram generation for time-resolved measurements with single-photon avalanche diode (SPAD) sensors requires the storage of many timestamp signals. This work presents a mixed-signal time-to-digital converter (TDC) that uses analog storage to achieve an area-efficient design that can be integrated in large SPAD [...] Read more.

Digital histogram generation for time-resolved measurements with single-photon avalanche diode (SPAD) sensors requires the storage of many timestamp signals. This work presents a mixed-signal time-to-digital converter (TDC) that uses analog storage to achieve an area-efficient design that can be integrated in large SPAD arrays. Fabricated using a 150 nm CMOS process, the prototype occupies an area of only 18.3 µm × 36.5 µm, a notable size reduction compared to conventional designs. The experimental results demonstrated high performance, with an integral nonlinearity (INL) of 0.35/0.14 least significant bit (LSB) and a differential nonlinearity (DNL) of 0.14/−0.12 LSB. In addition, the proposed TDC can support the construction of histograms comprising up to 512 bins, making it an effective solution to accommodate a wide range of resolution requirements. Validated in a point-of-care (PoC) device for fluorescence lifetime measurements, it distinguished between lifetimes of approximately 4.1 ns, 3.6 ns and 80 ns with the Alexa Fluor (AF) 546 and 568 dyes and Quantum Dot (QD) 705, respectively. The analog storage design and area-efficient architecture offer a novel approach to integrating TDCs in SPAD-based systems, with potential applications in medical diagnostics and beyond. Full article

(This article belongs to the Section Intelligent Sensors)

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20 pages, 5507 KiB

Open AccessArticle

Robust Pixel Design Methodologies for a Vertical Avalanche Photodiode (VAPD)-Based CMOS Image Sensor

by Akito Inoue, Naoki Torazawa, Shota Yamada, Yuki Sugiura, Motonori Ishii, Yusuke Sakata, Taiki Kunikyo, Masaki Tamaru, Shigetaka Kasuga, Yusuke Yuasa, Hiromu Kitajima, Hiroshi Koshida, Tatsuya Kabe, Manabu Usuda, Masato Takemoto, Yugo Nose, Toru Okino, Takashi Shirono, Kentaro Nakanishi, Yutaka Hirose, Shinzo Koyama, Mitsuyoshi Mori, Masayuki Sawada, Akihiro Odagawa and Tsuyoshi Tanaka Show full author list Hide full author list

Sensors 2024, 24(16), 5414; https://doi.org/10.3390/s24165414 - 21 Aug 2024

Viewed by 1786

Abstract

We present robust pixel design methodologies for a vertical avalanche photodiode-based CMOS image sensor, taking account of three critical practical factors: (i) “guard-ring-free” pixel isolation layout, (ii) device characteristics “insensitive” to applied voltage and temperature, and (iii) stable operation subject to intense light [...] Read more.

We present robust pixel design methodologies for a vertical avalanche photodiode-based CMOS image sensor, taking account of three critical practical factors: (i) “guard-ring-free” pixel isolation layout, (ii) device characteristics “insensitive” to applied voltage and temperature, and (iii) stable operation subject to intense light exposure. The “guard-ring-free” pixel design is established by resolving the tradeoff relationship between electric field concentration and pixel isolation. The effectiveness of the optimization strategy is validated both by simulation and experiment. To realize insensitivity to voltage and temperature variations, a global feedback resistor is shown to effectively suppress variations in device characteristics such as photon detection efficiency and dark count rate. An in-pixel overflow transistor is also introduced to enhance the resistance to strong illumination. The robustness of the fabricated VAPD-CIS is verified by characterization of 122 different chips and through a high-temperature and intense-light-illumination operation test with 5 chips, conducted at 125 °C for 1000 h subject to 940 nm light exposure equivalent to 10 kLux. Full article

(This article belongs to the Special Issue Optoelectronic Functional Devices for Sensing Applications)

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18 pages, 12883 KiB

Open AccessArticle

Comparative Analysis of Free-Running and Gating Imaging Modes of SPAD Sensors

by Xin Sun, Hu Yan, Hongcun He, Xiangshun Kong, Chen Mao and Feng Yan

Photonics 2024, 11(8), 721; https://doi.org/10.3390/photonics11080721 - 31 Jul 2024

Viewed by 2065

Abstract

A single-photon avalanche diode (SPAD) is a photon-counting sensor renowned for its exceptional single-photon sensitivity. One significant feature of SPADs is their non-linear response to light, making them ideal for high-dynamic range imaging applications. In SPAD imaging, the photon detection mode, which depends [...] Read more.

A single-photon avalanche diode (SPAD) is a photon-counting sensor renowned for its exceptional single-photon sensitivity. One significant feature of SPADs is their non-linear response to light, making them ideal for high-dynamic range imaging applications. In SPAD imaging, the photon detection mode, which depends on the quenching method employed, is crucial for optimizing image quality and dynamic range. This paper examines the free-running and gating imaging modes, evaluating their impacts on photon capture and saturation limits. Given that the number of incident photons follows a Poisson distribution, we introduce an innovative imaging-quenching model based on statistical mathematics. We designed and fabricated two SPAD imaging sensors using 180 nm CMOS technology. Image processing and evaluation were conducted using a mapping method. Our results show that in low-light conditions, the gating mode surpasses the free-running mode in the signal-to-noise ratio (SNR). However, the free-running mode exhibits a saturation limit of more than an order of magnitude higher than that of the gating mode, demonstrating its superior capability to handle a broader range of light intensities. This paper provides a thorough analysis of the differences between the two imaging methods, incorporating the theoretical mathematical model, circuit characteristics, and computed imaging quality. Full article

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12 pages, 5319 KiB

Open AccessArticle

Shallow Trench Isolation Patterning to Improve Photon Detection Probability of Single-Photon Avalanche Diodes Integrated in FD-SOI CMOS Technology

by Shaochen Gao, Duc-Tung Vu, Thibauld Cazimajou, Patrick Pittet, Martine Le Berre, Mohammadreza Dolatpoor Lakeh, Fabien Mandorlo, Régis Orobtchouk, Jean-Baptiste Schell, Jean-Baptiste Kammerer, Andreia Cathelin, Dominique Golanski, Wilfried Uhring and Francis Calmon

Photonics 2024, 11(6), 526; https://doi.org/10.3390/photonics11060526 - 1 Jun 2024

Viewed by 1780

Abstract

The integration of Single-Photon Avalanche Diodes (SPADs) in CMOS Fully Depleted Silicon-On-Insulator (FD-SOI) technology under a buried oxide (BOX) layer and a silicon film containing transistors makes it possible to realize a 3D SPAD at the chip level. In our study, a nanostructurated [...] Read more.

The integration of Single-Photon Avalanche Diodes (SPADs) in CMOS Fully Depleted Silicon-On-Insulator (FD-SOI) technology under a buried oxide (BOX) layer and a silicon film containing transistors makes it possible to realize a 3D SPAD at the chip level. In our study, a nanostructurated layer created by an optimized arrangement of Shallow Trench Isolation (STI) above the photosensitive zone generates constructive interferences and consequently an increase in the light sensitivity in the frontside illumination. A simulation methodology is presented that couples electrical and optical data in order to optimize the STI trenches (size and period) and to estimate the Photon Detection Probability (PDP) gain. Then, a test chip was designed, manufactured, and characterized, demonstrating the PDP improvement due to the STI nanostructuring while maintaining a comparable Dark Count Rate (DCR). Full article

(This article belongs to the Special Issue Emerging Topics in Single-Photon Detectors)

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17 pages, 4503 KiB

Open AccessArticle

Fluorescence Multi-Detection Device Using a Lensless Matrix Addressable microLED Array

by Victor Moro, Joan Canals, Sergio Moreno, Steffen Higgins-Wood, Oscar Alonso, Andreas Waag, J. Daniel Prades and Angel Dieguez

Biosensors 2024, 14(6), 264; https://doi.org/10.3390/bios14060264 - 22 May 2024

Viewed by 2176

Abstract

A Point-of-Care system for molecular diagnosis (PoC-MD) is described, combining GaN and CMOS chips. The device is a micro-system for fluorescence measurements, capable of analyzing both intensity and lifetime. It consists of a hybrid micro-structure based on a 32 × 32 matrix addressable [...] Read more.

A Point-of-Care system for molecular diagnosis (PoC-MD) is described, combining GaN and CMOS chips. The device is a micro-system for fluorescence measurements, capable of analyzing both intensity and lifetime. It consists of a hybrid micro-structure based on a 32 × 32 matrix addressable GaN microLED array, with square LEDs of 50 µm edge length and 100 µm pitch, with an underneath wire bonded custom chip integrating their drivers and placed face-to-face to an array of 16 × 16 single-photon avalanche diodes (SPADs) CMOS. This approach replaces instrumentation based on lasers, bulky optical components, and discrete electronics with a full hybrid micro-system, enabling measurements on 32 × 32 spots. The reported system is suitable for long lifetime (>10 ns) fluorophores with a limit of detection ~1/4 µM. Proof-of-concept measurements of streptavidin conjugate Qdot™ 605 and Amino PEG Qdot™ 705 are demonstrated, along with the device ability to detect both fluorophores in the same measurement. Full article

(This article belongs to the Special Issue Advanced Fluorescence Biosensors)

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11 pages, 3062 KiB

Open AccessArticle

Hot-Carrier Damage in N-Channel EDMOS Used in Single Photon Avalanche Diode Cell through Quasi-Static Modeling

by Alain Bravaix, Hugo Pitard, Xavier Federspiel and Florian Cacho

Micromachines 2024, 15(2), 205; https://doi.org/10.3390/mi15020205 - 30 Jan 2024

Cited by 1 | Viewed by 1636

Abstract

A single photon avalanche diode (SPAD) cell using N-channel extended-drain metal oxide semiconductor (N-EDMOS) is tested for its hot-carrier damage (HCD) resistance. The stressing gate-voltage (V_GS) dependence is compared to hot-hole (HH) injection, positive bias temperature (PBT) instability and off-mode (V [...] Read more.

A single photon avalanche diode (SPAD) cell using N-channel extended-drain metal oxide semiconductor (N-EDMOS) is tested for its hot-carrier damage (HCD) resistance. The stressing gate-voltage (V_GS) dependence is compared to hot-hole (HH) injection, positive bias temperature (PBT) instability and off-mode (V_GS = 0). The goal was to check an accurate device lifetime extraction using accelerated DC to AC stressing by applying the quasi-static (QS) lifetime technique. N-EDMOS device is devoted to 3D bonding with CMOS imagers obtained by an optimized process with an effective gate-length L_eff = 0.25 µm and a SiO₂ gate-oxide thickness T_ox = 5 nm. The operating frequency is 10 MHz at maximum supply voltage V_DDmax = 5.5 V. TCAD simulations are used to determine the real voltage and timing configurations for the device in a mixed structure of the SPAD cell. AC device lifetime is obtained using worst-case DC accelerating degradation, which is transferred by QS technique to the AC waveforms applied to N-EDMOS device. This allows us to accurately obtain the AC device lifetime as a function of the delay and load for a fixed pulse shape. It shows the predominance of the high energy hot-carriers involved in the first substrate current peak during transients. Full article

(This article belongs to the Special Issue Reliability Issues in Advanced Transistor Nodes)

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12 pages, 2309 KiB

Open AccessArticle

Effect of Proton Irradiation on Complementary Metal Oxide Semiconductor (CMOS) Single-Photon Avalanche Diodes

by Mingzhu Xun, Yudong Li, Jie Feng, Chengfa He, Mingyu Liu and Qi Guo

Electronics 2024, 13(1), 224; https://doi.org/10.3390/electronics13010224 - 4 Jan 2024

Cited by 2 | Viewed by 2032

Abstract

The effects of proton irradiation on CMOS Single-Photon Avalanche Diodes (SPADs) are investigated in this article. The I–V characteristics, dark count rate (DCR), and photon detection probability (PDP) of the CMOS SPADs were measured under 30 MeV and 52 MeV proton irradiations. Two [...] Read more.

The effects of proton irradiation on CMOS Single-Photon Avalanche Diodes (SPADs) are investigated in this article. The I–V characteristics, dark count rate (DCR), and photon detection probability (PDP) of the CMOS SPADs were measured under 30 MeV and 52 MeV proton irradiations. Two types of SPAD, with and without shallow trench isolation (STI), were designed. According to the experimental results, the leakage current, breakdown voltage, and PDP did not change after irradiation at a DDD of 2.82 × 10⁸ MeV/g, but the DCR increased significantly at five different higher voltages. The DCR increased by 506 cps at an excess voltage of 2 V and 10,846 cps at 10 V after 30 MeV proton irradiation. A γ irradiation was conducted with a TID of 10 krad (Si). The DCR after the γ irradiation increased from 256 cps to 336 cps at an excess voltage of 10 V. The comparison of the DCR after proton and γ-ray irradiation with two structures of SPAD indicates that the major increase in the DCR was due to the depletion region defects caused by proton displacement damage rather than the Si-SiO₂ interface trap generated by ionization. Full article

(This article belongs to the Special Issue Radiation Effects of Advanced Electronic Devices and Circuits)

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14 pages, 7553 KiB

Open AccessArticle

Multi-Channel Gating Chip in 0.18 µm High-Voltage CMOS for Quantum Applications

by Christoph Ribisch, Michael Hofbauer, Seyed Saman Kohneh Poushi, Alexander Zimmer, Kerstin Schneider-Hornstein, Bernhard Goll and Horst Zimmermann

Sensors 2023, 23(24), 9644; https://doi.org/10.3390/s23249644 - 6 Dec 2023

Cited by 2 | Viewed by 1424

Abstract

A gating circuit for a photonic quantum simulator is introduced. The gating circuit uses a large excess bias voltage of up to 9.9 V and an integrated single-photon avalanche diode (SPAD). Nine channels are monolithically implemented in an application-specific integrated circuit (ASIC) including [...] Read more.

A gating circuit for a photonic quantum simulator is introduced. The gating circuit uses a large excess bias voltage of up to 9.9 V and an integrated single-photon avalanche diode (SPAD). Nine channels are monolithically implemented in an application-specific integrated circuit (ASIC) including nine SPADs using 0.18 µm high-voltage CMOS technology. The gating circuit achieves rise and fall times of 480 ps and 280 ps, respectively, and a minimum full-width-at-half-maximum pulse width of 1.26 ns. Thanks to a fast and sensitive comparator, a detection threshold for avalanche events of less than 100 mV is possible. The power consumption of all nine channels is about 250 mW in total. This gating chip is used to characterize the integrated SPADs. A photon detection probability of around 50% at 9.9 V excess bias and for a wavelength of 635 nm is found. Full article

(This article belongs to the Special Issue Integrated Circuits and CMOS Sensors)

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7 pages, 2120 KiB

Open AccessCommunication

N-Channel MOSFET Reliability Issue Induced by Visible/Near-Infrared Photons in Image Sensors

by Chun-Hsien Liu and Sheng-Di Lin

Sensors 2023, 23(23), 9586; https://doi.org/10.3390/s23239586 - 3 Dec 2023

Viewed by 1502

Abstract

Image sensors such as single-photon avalanched diode (SPAD) arrays typically adopt in-pixel quenching and readout circuits, and the under-illumination first-stage readout circuits often employs high-threshold input/output (I/O) or thick-oxide metal-oxide-semiconductor field-effect transistors (MOSFETs). We have observed reliability issues with high-threshold n-channel MOSFETs when [...] Read more.

Image sensors such as single-photon avalanched diode (SPAD) arrays typically adopt in-pixel quenching and readout circuits, and the under-illumination first-stage readout circuits often employs high-threshold input/output (I/O) or thick-oxide metal-oxide-semiconductor field-effect transistors (MOSFETs). We have observed reliability issues with high-threshold n-channel MOSFETs when they are exposed to strong visible light. The specific stress conditions have been applied to observe the drain current (I_d) variations as a function of gate voltage. The experimental results indicate that photo-induced hot electrons generate interface trap states, leading to I_d degradation including increased off-state current (I_off) and decreased on-state current (I_on). The increased I_off further activates parasitic bipolar junction transistors (BJT). This reliability issue can be avoided by forming an inversion layer in the channel under appropriate bias conditions or by reducing the incident photon energy. Full article

(This article belongs to the Special Issue Recent Advances in CMOS Image Sensor)

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18 pages, 5265 KiB

Open AccessArticle

Pion Detection Using Single Photon Avalanche Diodes

by Anthony Frederick Bulling and Ian Underwood

Sensors 2023, 23(21), 8759; https://doi.org/10.3390/s23218759 - 27 Oct 2023

Cited by 1 | Viewed by 1886

Abstract

We present the first reported use of a CMOS-compatible single photon avalanche diode (SPAD) array for the detection of high-energy charged particles, specifically pions, using the Super Proton Synchrotron at CERN, the European Organization for Nuclear Research. The results confirm the detection of [...] Read more.

We present the first reported use of a CMOS-compatible single photon avalanche diode (SPAD) array for the detection of high-energy charged particles, specifically pions, using the Super Proton Synchrotron at CERN, the European Organization for Nuclear Research. The results confirm the detection of incident high-energy pions at 120 GeV, minimally ionizing, which complements the variety of ionizing radiation that can be detected with CMOS SPADs. Full article

(This article belongs to the Special Issue Optical Sensors Technology and Applications: Volume II)

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31 pages, 7519 KiB

Open AccessReview

Modeling for Single-Photon Avalanche Diodes: State-of-the-Art and Research Challenges

by Xuanyu Qian, Wei Jiang, Ahmed Elsharabasy and M. Jamal Deen

Sensors 2023, 23(7), 3412; https://doi.org/10.3390/s23073412 - 24 Mar 2023

Cited by 14 | Viewed by 9829

Abstract

With the growing importance of single-photon-counting (SPC) techniques, researchers are now designing high-performance systems based on single-photon avalanche diodes (SPADs). SPADs with high performances and low cost allow the popularity of SPC-based systems for medical and industrial applications. However, few efforts were put [...] Read more.

With the growing importance of single-photon-counting (SPC) techniques, researchers are now designing high-performance systems based on single-photon avalanche diodes (SPADs). SPADs with high performances and low cost allow the popularity of SPC-based systems for medical and industrial applications. However, few efforts were put into the design optimization of SPADs due to limited calibrated models of the SPAD itself and its related circuits. This paper provides a perspective on improving SPAD-based system design by reviewing the development of SPAD models. First, important SPAD principles such as photon detection probability (PDP), dark count rate (DCR), afterpulsing probability (AP), and timing jitter (TJ) are discussed. Then a comprehensive discussion of various SPAD models focusing on each of the parameters is provided. Finally, important research challenges regarding the development of more advanced SPAD models are summarized, followed by the outlook for the future development of SPAD models and emerging SPAD modeling methods. Full article

(This article belongs to the Special Issue Recent Advances in CMOS Image Sensor)

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17 pages, 5888 KiB

Open AccessArticle

Towards a Multi-Pixel Photon-to-Digital Converter for Time-Bin Quantum Key Distribution

by Simon Carrier, Michel Labrecque-Dias, Ramy Tannous, Pascal Gendron, Frédéric Nolet, Nicolas Roy, Tommy Rossignol, Frédéric Vachon, Samuel Parent, Thomas Jennewein, Serge Charlebois and Jean-François Pratte

Sensors 2023, 23(7), 3376; https://doi.org/10.3390/s23073376 - 23 Mar 2023

Cited by 1 | Viewed by 3201

Abstract

We present an integrated single-photon detection device custom designed for quantum key distribution (QKD) with time-bin encoded single photons. We implemented and demonstrated a prototype photon-to-digital converter (PDC) that integrates an 8 × 8 single-photon avalanche diode (SPAD) array with on-chip digital signal [...] Read more.

We present an integrated single-photon detection device custom designed for quantum key distribution (QKD) with time-bin encoded single photons. We implemented and demonstrated a prototype photon-to-digital converter (PDC) that integrates an 8 × 8 single-photon avalanche diode (SPAD) array with on-chip digital signal processing built in TSMC 65 nm CMOS. The prototype SPADs are used to validate the QKD functionalities with an array of time-to-digital converters (TDCs) to timestamp and process the photon detection events. The PDC uses window gating to reject noise counts and on-chip processing to sort the photon detections into respective time-bins. The PDC prototype achieved a 22.7 ps RMS timing resolution and demonstrated operation in a time-bin setup with 158 ps time-bins at an optical wavelength of 410 nm. This PDC can therefore be an important building block for a QKD receiver and enables compact and robust time-bin QKD systems with imaging detectors. Full article

(This article belongs to the Special Issue Time-Resolved Single Photon Imagers and Their Applications)

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14 pages, 3289 KiB

Open AccessArticle

Indirect Time-of-Flight with GHz Correlation Frequency and Integrated SPAD Reaching Sub-100 µm Precision in 0.35 µm CMOS

by Michael Hauser, Horst Zimmermann and Michael Hofbauer

Sensors 2023, 23(5), 2733; https://doi.org/10.3390/s23052733 - 2 Mar 2023

Cited by 2 | Viewed by 2528

Abstract

The purpose of this work is to prove the suitability of integrated single-photon avalanche diode (SPAD)-based indirect time-of-flight (iTOF) for sub-100 µm precision depth sensing using a correlation approach with GHz modulation frequencies. For this purpose, a prototype containing a single pixel consisting [...] Read more.

The purpose of this work is to prove the suitability of integrated single-photon avalanche diode (SPAD)-based indirect time-of-flight (iTOF) for sub-100 µm precision depth sensing using a correlation approach with GHz modulation frequencies. For this purpose, a prototype containing a single pixel consisting of an integrated SPAD, quenching circuit, and two independent correlator circuits was fabricated in a 0.35 µm CMOS process and characterized. It achieved a precision of 70 µm and a nonlinearity of less than 200 µm at a received signal power of less than 100 pW. Sub-mm precision was achieved with a signal power of less than 200 fW. These results and the simplicity of our correlation approach underline the great potential of SPAD-based iTOF for future depth sensing applications. Full article

(This article belongs to the Special Issue Time-Resolved Single Photon Imagers and Their Applications)

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15 pages, 2885 KiB

Open AccessArticle

A Multi-Time-Gated SPAD Array with Integrated Coarse TDCs

by Ryan Scott, Wei Jiang, Xuanyu Qian and M. Jamal Deen

Electronics 2022, 11(13), 2015; https://doi.org/10.3390/electronics11132015 - 27 Jun 2022

Cited by 4 | Viewed by 3668

Abstract

Time-gating of single-photon avalanche diodes (SPADs) was commonly used as a method to reduce dark noise in biomedical imaging applications where photon events are correlated with a reference clock. Time-gating was also used to obtain timing information of photon events by shifting the [...] Read more.

Time-gating of single-photon avalanche diodes (SPADs) was commonly used as a method to reduce dark noise in biomedical imaging applications where photon events are correlated with a reference clock. Time-gating was also used to obtain timing information of photon events by shifting the gate windows applied to a SPAD array. However, in this approach, fine timing resolution comes at the cost of a lengthened measurement time due to the large number of counts required for each shift. As a solution, we present a multi-time-gated SPAD array that simultaneously applies shifted gate windows to an array of SPADs, which has the potential to reduce the measurement time compared to a single time gate window. Compared to similar works, this design has fully integrated the multi-gate generation using shared circuitry which also functions as a coarse time-to-digital converter. The proposed array, fabricated in the TSMC 65 nm standard CMOS process, achieved a median dark count rate (DCR) of 37 kHz, 4.37 ns gate widths, 550 ps timing resolution, and a peak photon detection probability (PDP) of 42.9% at 420 nm, all at a 0.8 V excess bias. Full article

(This article belongs to the Special Issue New Technologies for Biomedical Circuits and Systems)

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