1. Introduction
Quantum key distribution (QKD) is a key generation and sharing protocol where the security relies on quantum properties instead of computational complexity of certain mathematical problems such as in classical cryptography [
1,
2]. Typically in QKD, the qubits are photons sent from the sender to the receiver via fiber-optical networks, free-space links of space-to-ground links. Multiple methods of encoding information in single optical qubits (photons) have been developed [
3,
4,
5,
6]. One of these is called “time-bin” in which the information is encoded in the time of arrival and phase of the photon, which necessitates high-precision single-photon detectors at the receiver [
7].
Time-bin encoding is achieved with unbalanced Mach–Zehnder interferometers (MZI) at both the sender and receiver. These must be as identical and stable as possible to avoid any phase drifts. The sender MZI prepares the qubit in one of four states from the time and phase bases: early (E), late (L), early and late with a constructive phase difference (), and early and late with a destructive phase difference (). The MZI receiver will detect one of four photon states: early–early (EE), late–late (LL), early–late (EL), or late–early (LE), which are temporally separated according to MZI path asymmetry.
Time-bin encoding offers advantages over polarization encoding in that it is relatively immune to depolarization and polarization mode-dispersion [
8,
9] of the channel and does not require polarization frame alignment of the sender and receiver. It is important to note that reducing the time separation between time-bins offers closer E and L time-bins, which allows for a more compact and stable MZI. This is, in particular, attractive for free-space applications where the distortion of the spatial mode requires elaborate imaging interferometers [
9], particularly challenging for applications under stringent volume and mass restrictions such as satellite or handheld QKD. Typically, the outputs of the single-photon detectors, such as a single-photon avalanche diode (SPAD) [
10,
11] or a superconducting nanowire single-photon detector (SNSPD) [
12,
13], are connected to a time-tagger, a specialized chronometer often implemented in an FPGA. However, these configurations present two challenges: they can be bulky due to cooling or device size and suffer from signal degradation, because the connection circuitry and cables could reduce timing resolution. Furthermore, a conventional QKD system is based on single-pixel single-photon detectors. However, array detectors could be very beneficial for the system performance as they can enhance the photon count rate, perform quantum signal tracking tasks, and improve resilience against blinding attacks [
14].
To address these challenges, a photon-to-digital converter (PDC) prototype is developed, comprising a single-photon detector array coupled to tailored digital electronics to process information such as the timestamp of each photon using embedded time-to-digital converters (TDC). This configuration can be realized in a very compact form (a few square millimeters for the PDC chip), and the distance between the detector and time-tagger is very short (<1 mm).
The PDC has an 8 × 8 SPAD [
15,
16] array in addition to the electronics on-chip (see
Figure 1). This implementation is suboptimal because the 65 nm SPADs, although having a good timing resolution (7.8 ps FWHM SPTR at 410 nm wavelength [
17]), suffer from low photon detection efficiency (7% at 410 nm in this work) and high noise (680 kcps average per SPAD). A more optimized solution would be to use another specialized technology for the SPADs and integrate them in 3D (on top) of the 65 nm CMOS electronics [
18], which is the goal of future iterations. Although the shortcomings of 2D integration and the 65 nm SPADs were acceptable to demonstrate the QKD functionalities in this prototype, this PDC was designed to allow a future 3D integration and already includes top-side bond pads.
In the QKD post-processing, the key exchange requires a comparison of the absolute timestamps of all received photon detections with the corresponding emission times, via communication over a classical channel. Our custom PDC design directly supports this exchange. Iterating on previous work [
19], the proposed PDC includes three features specifically targeted at QKD: timing window generation, TDC gating, and custom on-chip post-processing. The timing window generation allows the PDC to create variable-length gating signals on-chip when an external trigger is raised. It also allows the TDC to timestamp events relative to the end of the window signal. TDC gating uses the window signal to reject events outside of a window of interest. The custom on-chip processing converts the TDC code to picosecond timestamps directly and categorizes the timestamp into its time-bin value (EE, LE/EL, or LL). These added features allow the receiver’s detector to directly output the time-bin value, which reduces the data-volume substantially, thereby simplifying the entire QKD post-processing. These three components will be explained in further details in the
Section 2.1. This is followed by a presentation of the testing and data acquisition setups in the
Section 2.2. The electronic and optical performance results are then presented in the
Section 3. Finally, a discussion of the results with a comparison to previous publications.
3. Results
This results section is divided into two main sections (electronic and optical) and presents the cumulative jitter from TDCs to time-bin optical measurements. This is to illustrate how the array integration and component design choices impacted the final time-bin measurements. The electronics section presents the results using only the trigger signals from the testing boards presented in
Section 2.2.1. The optical section presents the time-bin results done with the setup presented in
Section 2.2.2.
3.1. Electronic TDC Performance
The TDC architecture used is similar to previous work. More details on the timestamping conversion from TDC raw data can be found in [
19,
22].
As an example,
Figure 13 shows for TDC #0 (head #7) a jitter of 7.48 ps RMS when measured using the system clock as stop signal and a correlated trigger signal generated on the adapter board with a time-delay between these two signals swept from 0 to 4000 ps with steps of 1 ps. We can define the total jitter of the TDC system as Equation (
1). Because the start and stop signals are correlated, it is not possible to separate the contributions of the start and stop jitter. This is why both are considered together and the measured jitter was <4.2 ps RMS (start is an external trigger and stop is the system clock). This means that the jitter of the TDC can be calculated to be ∼6.2 ps RMS. However, because in a real setting, the jitter of the system (
) does impact the total performance (
), the total jitter will be used in results and comparisons. The jitter breakdown of Equations (
1)–(
3) is to understand which components have the most impact and if there are any bottlenecks. Note that in Equations (
1)–(
3),
,
, and
are all the same.
External is the more generic case, which is essentially the
start and stop signals, which, in turn, are the
external trigger and clock in this case.
Thus, from
measured at 7.48 ps and
measured at 4.2 ps, this gives a
of ∼6.2 ps. Using the window’s end as the stop signal adds jitter to the measurement, as shown in
Figure 14. In fact, the measured
changes to <5.2 ps since the stop signal is now the window signal.
The total jitter is a sum of the contributions of the TDC, the start trigger, and the stop trigger. Equation (2) now can be changed as follows:
Thus, from
measured at 10.48 ps and
measured at 5.2 ps, this gives a
of ∼9.1 ps. The difference in performance for
between
Figure 13 and
Figure 14 corresponds to 6.2 ps and 9.1 ps, respectively. This indicates that the window circuit on-chip adds roughly
ps RMS to the jitter. As 6.2 ps and 6.7 ps are so close, the jitter is essentially doubled when using the window circuit.
Figure 15 illustrates the performance uniformity of the TDC array. Although much care was taken to make the TDCs identical and the arrays as uniform as possible, variations in the fabrication process, temperature fluctuations, circuit mismatch, and voltage fluctuations will influence the performance between TDCs. The resolution of the TDCs are tuned with a digital-to-analog converter (DAC). However, as each TDC is slightly different, and the applied voltage is the same for every TDC, some performance variations will occur. The average jitter is 8.4 ps RMS with a 2 ps standard deviation.
3.2. Time-Bin Measurements
We now report on the operation of the PDC in the “QKD Time-bin” mode using the setup of
Figure 10. The following results are from the optical tests in which the three time-bins are measured with the MZI shown in
Figure 10 at 410 nm wavelength.
In
Figure 16, the three time-bins (late–late, early–late/late–early, and early–early) are categorized on-chip. They correspond to bins 1, 2, and 3 respectively. Because a late event gets a smaller timestamp measured with respect to the end of the gating window, late–late corresponds to bin 1 (refer to
Figure 4). Bins 0 and 4 correspond to events that are outside the bounds and are filled with noise triggered events. The bounds between each bins are programmable on-chip. This processing reduces the timestamp information (22 bits) to bin value (3 bits), which maximizes the potential throughput.
3.3. Jitter Estimation for the SPAD and Quenching Circuit Chain
For all time-bin measurements, the start signal of the TDC was the photon arrival and the stop signal was the end of the window signal. The window trigger signal is generated either from another photodiode or from a signal from the laser. Thus, the jitter equation from Equation (2) changes to:
The
was measured to be 3 ps FWHM with the same setup (laser, photodiode, and oscilloscope) as [
17], thus the jitter of the reference photodiode is approximated to <1 ps RMS. From the electrical tests, the jitter of the TDC + window is 10.48 ps RMS when including the jitter of the setup. Therefore, given the
= 22.7 ps RMS from
Figure 16, that leaves a jitter of ~20.1 ps RMS for the SPAD + quenching circuit (Equation (
6)).
This is significantly higher than the 7.8 ps FWHM of our previous publication [
17]. There are four factors that could explain this difference: (1) this PDC has an array of SPADs instead of a single SPAD channel, (2) the end of the generated window is used as the TDC stop signal, (3) low power 65 nm CMOS (LP) is used instead of general purpose 65 nm CMOS (GP), or (4) design changes to the SPAD layout.
In this PDC, there are 64 SPADs that trigger at an average rate of 680 kcps that generate electrical crosstalk and noise into the power rails or the substrate. Each TDC has two ring oscillators that also generate common-mode noise. In turn, this noise couples to the TDCs and increases their jitter. Jitter measurements were taken while one SPAD channel was activated (others disabled) to compare to when all SPAD channels are active. The jitter did degrade by 1–2 ps RMS in the latter case. Although this does not explain the large difference, it is a contributing factor.
During experiments, it was noticed that some TDC timestamp values would suffer from more jitter when using the window as the stop signal. Although
Figure 14 shows the impact across all codes, the window might negatively impact certain timestamps that would affect measurements such as those in
Figure 16, which do not average the jitter across the whole dynamic range.
Due to a higher threshold and less leakage, LP offers lower power consumption at the expense of speed. Although measures were taken to account for these differences, the impact of the slower speed (compared to GP) might have been bigger than anticipated through simulation.
In this PDC, the quenching circuits read the cathode of each SPAD (as opposed to the anode in [
17]). Although the SPAD’s architecture was not modified significantly with respect to [
17], the connection to the cathode of the SPAD changes the parasitic capacitance at the quenching circuit readout node. For example, one could expect the cathode-to-substrate capacitance to be higher than that of the anode. Such changes would certainly degrade the jitter of the SPAD + quenching circuit.
Because in this PDC we do not have access to the window end signal or the SPAD cathode, it is difficult to give a definitive answer on the source of the added jitter of the SPADs. Although this is still under investigation, the next revision of the PDC will include new unitary test structures in the hope of clearly identifying the cause.
4. Discussion
The performances of the TDC array are an improvement over previous iterations [
19] from our team and offers additional functionalities such as TDC gating. In [
19], TDC jitter performance degradation had been observed when many TDCs were operating simultaneously, injecting noise in the substrate and the power rail. To address this, this iteration made three modifications based on the recommendations of [
19]. First, to reduce the common-mode noise, in this integrated circuit there is one TDC for four SPADs. Second, to decrease the mismatch between each TDC, in this version the size of the oscillators’ transistors were increased. Third, to equally control the oscillators of the TDCs, we implemented the control voltages of the current starved elements from the ring oscillators in a mesh configuration. These changes proved beneficial, as
Figure 17 shows that even in an array configuration with all elements active, the performance of the jitter and resolution (LSB) variations are improved with respect to [
19].
The new window gating functionality, however, adds more jitter to the system. This can be seen when comparing
Figure 13 with
Figure 14 where the jitter increases from 7.48 ps RMS to 10.48 ps RMS just by using the window as the stop signal instead of the system clock. Because the measured jitter of the external signals (the “event trigger” and “window trigger”) going into the PDC is ∼4 ps RMS, the PDC is nearing the limits set by the test bench. However, as bigger arrays (such as 64 × 64) are an objective, ways to reduce the jitter and width variations of the gating window will be explored. The window generator is programmed on-chip to add or remove standard cells delay blocks to control the width of the window. As these delay blocks are susceptible to variations due to temperature and fabrication, the final width of the window can vary. The window size fluctuations and the routing of the window signal could explain the increase jitter from
Figure 13 and
Figure 14 and the increased jitter of SPAD+QC compared to the previous publication [
17].
The SPAD array heats the device when activated and that heat is not properly distributed across the device. As seen in
Figure 1, there is a SPAD array (B) next to the top side of the integrated read out (C). As they are noisy SPADs, good for electronics and functionality testing, they will generate a hot spot above the read out array (C). This impacts thermal noise and mismatch among electronics pixels. In addition, the routing capacitance between each SPAD and quenching circuit is not equal, which has an impact on the signal slope (
), which has a direct impact on the timing jitter.
More investigation is ongoing to understand the extra jitter observed in the measurement and better design techniques. A solution is to use the rising edge of the window instead of the falling edge as the time reference. This could reduce jitter, as the rising edge comes from the signal, compared to the falling edge, which is decided by a series of delay blocks in the window generator.
With the window gating, time-bins with 158 ps difference at 410 nm was achieved. This time difference represents a roughly 5 cm difference between each arm of the MZI and opens doors to explore compact MZI setups. In terms of time-bin separation, this result is similar to other publications [
23,
24], but this PDC offers the timestamping done on-chip. This means that no bulky external timestamping equipment is required. These elements, in addition to operating at room temperature, makes this detector a promising candidate for QKD in situations that require small size and low power consumption, such as hand-held or satellite free-space for a QKD network [
25,
26].
As noted previously, the SPADs used in this PDC were implemented to provide realistic input to the quenching circuits and TDCs and validate the new QKD functionalities. They are a stopgap solution before the future 3D integrated SPADs that will offer better dark count and photon detection efficiency (PDE). The 65 nm SPADs used in this PDC have a high noise (680 kcps average per SPAD across the 8 × 8 array) and low PDE (7% at 410 nm). Thankfully, the gating window could be used to reduce their impact. However, the noise restricted how low the laser power could go before losing the signal in the noise floor. This meant that the laser was not operating at a single-photon regime when measuring the time-bins. Because the objective was to demonstrate the functionalities of the PDC and not the security, operating at the single photon level was not an objective of this study but can be implemented in future work. In addition, the measured outgoing event rate coming out of the PDC was around ∼360 KHz (2800 ns period) in the experiment of
Figure 16. This is much lower than the limit set by the serial communication noted previously (3.9 MHz). We estimate that with the high noise count of the 64 SPAD array, low PDE, and the window gating of 2.5 ns width, the majority of events are rejected by the window gating, and the SPADs are too often in their deadtime. Thus, we are not reaching the upper bound of the event rate.
5. Conclusions
The photon-to-digital converter concept allows us to integrate the full detection chain and some signal processing within a single device. In this work, the PDC was designed and implemented as a QKD receiver. The good timing resolution and jitter allows for around 158 ps separation between time-bins while maintaining photon detection rates of several MHz. This translates to more compact MZIs that can be implemented in space-restricted systems and offer easier calibration between the sender and receiver MZI. In addition, TDC gating allows us to reduce noise by only processing events that occur within the window of time the qubit is expected to arrive at the receiver. Finally, custom processing on-chip (such as on-chip time-binning) offers the possibility to filter unwanted events and extract only the essential data, thus increasing throughput.
These very unique QKD capabilities were demonstrated for this PDC prototype. The 8 × 8 array of 65 nm SPADs was used to provide realistic input to the system and validate the QKD functionalities of the PDC. Future work includes implementing 3D integrated SPAD design with the PDC to enhance the SPAD performance and adding further on-chip processing capability such as image analysis.