Search Results (32)

Background/Objectives: Cushing’s syndrome (CS) is a rare endocrine disorder caused by chronic glucocorticoid excess. With the increasing recognition of mild autonomous cortisol secretion (MACS), clinical and biochemical differentiation between overt and mild forms has become more challenging. This study evaluated the clinical significance of the hemoglobin–albumin–lymphocyte–platelet (HALP) score in patients with Cushing’s disease (CD), adrenal Cushing’s syndrome (ACS), MACS, and nonfunctioning adrenal adenoma (NFA), focusing on its potential role in the preoperative evaluation and postoperative follow-up of hypercortisolism. Methods: We retrospectively analyzed 361 patients evaluated for cortisol excess between February 2019 and June 2025. Patients were categorized into four groups: CD, ACS, MACS, and NFA. Demographic, clinical, and hormonal parameters, as well as surgical outcomes, were recorded, and the HALP score was compared between the four groups. The diagnostic performance of the HALP score in differentiating overt Cushing’s syndrome (CD + ACS) from MACS/NFA was assessed using receiver operating characteristic (ROC) curve analysis. Postoperative changes in the HALP score were analyzed in surgically treated patients. Results: HALP scores were significantly lower in overt CS than in MACS and NFA. Using a threshold value of 40, the HALP score demonstrated 51.9% sensitivity and 90.4% specificity in differentiating CD/ACS from MACS/NFA. Among 68 operated patients, postoperative HALP data were available for 49 patients, for whom HALP scores significantly increased in both CD and ACS groups (p = 0.001 for each). Conclusions: The HALP score serves as a simple, cost-effective biomarker that reflects the combined hematologic and metabolic impact of cortisol excess. Significant postoperative improvement in the HALP score suggests its potential utility as a complementary tool in the preoperative assessment of hypercortisolism. Full article

Phase and band gap engineering of (CdS)_x(CuInS₂)_1−x nanomaterials is critical for their potential applications in photovoltaics and photocatalysis, yet it remains a challenge. Here, we report a precursor-mediated colloidal method for phase-control synthesis of alloyed (CdS)_x(CuInS₂)_1−x nanocrystals with tunable band gap. When CuCl, InCl₃, and Cd(AC)₂·2H₂O are used as the respective cation sources, wurtzite-structured alloyed (CdS)_x(CuInS₂)_1−x nanocrystals can be synthesized with a tunable optical band gap ranging from 1.56 to 2.45 eV by directly controlling the molar ratio of the Cd precursor. Moreover, using Cu(S₂CNEt₂)₂, In(S₂CNEt₂)₃, and Cd(S₂CNEt₂)₂ as cation sources results in alloyed (CdS)_x(CuInS₂)_1−x nanocrystals with a zinc-blende structure, demonstrating that the optical band gap of these nanocrystals can be compositionally tuned from 1.50 to 1.84 eV through precisely adjusting the molar ratio of Cd precursor. The results were validated through a comprehensive characterization approach employing XRD, TEM, HRTEM, STEM-EDS, XPS, UV-vis-NIR absorption spectroscopy, and Mott–Schottky analysis. Full article

Data privacy is a crucial concern for individuals using cloud storage services, and cloud service providers are increasingly focused on meeting this demand. However, privacy breaches in the ever-evolving cyber landscape remain a significant threat to cloud storage infrastructures. Previous studies have aimed to address this issue but have often lacked comprehensive coverage of privacy attributes. In response to the identified gap in privacy-preserving techniques for cloud computing, this research paper presents a novel and adaptable framework. This approach introduces a multi-layer encoding storage arrangement combined with the implementation of a one-time password authorization approach. By integrating these elements, the proposed approach aims to enhance both the flexibility and efficiency of data protection in cloud environments. The findings of this study are anticipated to have significant implications, contributing to the advancement of existing techniques and inspiring the development of innovative research-driven solutions. Continuous research efforts are required to validate the effectiveness of the proposed framework across diverse contexts and assess its performance against evolving privacy vulnerabilities in cloud computing. Full article

As wireless communication systems continue to demand higher data transmission rates, the need for analog-to-digital converters (ADCs) with a higher sampling rate becomes increasingly critical. However, traditional successive approximation register (SAR) ADCs operating at 1 bit/cycle often face speed limitations due to the fixed bit intervals and comparator regeneration delays, which constrain their scalability in advanced technology nodes. To address these challenges, this paper presents a high-speed 8-bit single-channel SAR ADC featuring a novel delay generation circuit that enables tailored bit intervals (TBIs) to reduce conversion latency. A split capacitive digital-to-analog converter (CDAC) is employed to suppress input common-mode voltage shifts, while inverted dynamic latch pairs and early capacitor reset techniques are introduced to improve conversion speed. The proposed ADC is implemented in a 16 nm CMOS process, occupying only 0.0012 mm². Post-layout simulations across extreme process and temperature corners validate the robustness of the design. The TBI-ADC achieves an effective number of bits (ENOB) of 7.20 bits at Typical–Typical (TT) 25 °C with a power consumption of 6.94 mW. Furthermore, it reaches a sampling rate of 1.6 GS/s at Fast–Fast (FF) −40 °C, representing a 33% improvement over the fastest previously reported single-channel, 1 bit/cycle, 8-bit SAR ADC. Full article

This paper presents a successive approximation register analog-to-digital converter (SAR ADC) specifically optimized for brain–computer interface (BCI) applications. Designed and post-layout-simulated using 180 nm CMOS technology, the proposed SAR ADC achieves a 13.44-bit effective number of bits (ENOB) and 27.9 μW of power consumption at a supply voltage of 1.8 V, enabled by a piecewise monotonic switching scheme and dynamic logic architecture. The ADC supports a high input range of ±500 mV, making it suitable for neural signal acquisition. Through an optimized capacitive digital-to-analog converter (CDAC) array and a high-speed dynamic comparator, the ADC demonstrates a signal-to-noise-and-distortion ratio (SINAD) of 81.94 dB and a spurious-free dynamic range (SFDR) of 91.69 dBc at a sampling rate of 320 kS/s. Experimental results validate the design’s superior performance in terms of low-power operation, high resolution, and moderate sampling rate, positioning it as a competitive solution for high-density integration and precision neural signal processing in next-generation BCI systems. Full article

Lung diseases, including chronic obstructive pulmonary disease (COPD) and pulmonary fibrosis, pose significant health challenges due to their high morbidity and mortality rates. Computed tomography (CT) scans play a critical role in early diagnosis and disease management, yet traditional segmentation methods often falter in addressing anatomical variability and pathological complexity. To overcome these limitations, this study introduces the context-driven active contour (CDAC), a new segmentation method that combines active contour models (ACMs) with contextual analysis. CDAC leverages contextual information from image embeddings and expert annotations to refine segmentation precision. The algorithm employs contextual attention force (CAF) as an external energy term and contextual balloon force (CBF) as an internal energy term, enabling robust contour adaptation. Evaluations were conducted on CT images of healthy lungs, as well as those affected by COPD and pulmonary fibrosis. CDAC achieved notable performance metrics, including a Dice coefficient of 96.8% for healthy lungs, an Accuracy of 94.5% for COPD, and a Jaccard Index of 92.3% for pulmonary fibrosis. These results demonstrate the method’s effectiveness and adaptability. By integrating contextual insights, CDAC offers a promising solution for enhancing computer-aided diagnostic (CAD) systems in the management of lung diseases. Full article

This article introduces a novel digital-to-analog converter (DAC), which addresses a few weaknesses that a traditional capacitive DAC (CDAC) has, such as matching and parasitic capacitance-induced code dependency and a challenging bridge capacitor design. Our novel idea is a hybrid DAC of a CDAC and a current-steering DAC (CSDAC) and is named the CSCDAC. In this paper, a 12-bit CSCDAC is designed, and the post-layout simulation is provided. The Nyquist 12-bit CSCDAC exhibits a spurious free dynamic range (SFDR) of 67.62 dB under an operating frequency of 2 GS/s, with an expected average power of 54 mW. The 12-bit CSCDAC occupies a 0.154 mm² die area, whereas the core area is 0.044 mm². Full article

This paper presents a highly efficient, low-power, compact mixed-signal sinusoidal current generator (CG) integrated circuit (IC) designed for bioelectrical impedance spectroscopy (BIS) with low total harmonic distortion (THD). The proposed system employs a 9-bit sine wave lookup table (LUT) which is simplified to a 4-bit data stream through a third-order digital delta–sigma modulator (ΔΣM). Unlike conventional analog low-pass filters (LPF), which statically limit bandwidth, the finite impulse response (FIR) filter attenuates high-frequency noise according to the operating frequency, allowing the frequency range of the sinusoidal signal to vary. Additionally, the output of the FIR filter is applied to a 6-bit capacitive digital-to-analog converter (CDAC) with data-weighted averaging (DWA), enabling dynamic capacitor matching and seamless interfacing. The sinusoidal CG IC, fabricated using a 65 nm CMOS process, produces a 5 μA amplitude and operates over a wide frequency range of 0.6 to 20 kHz. This highly synthesizable CG achieves a THD of 0.04%, consumes 19.2 μW of power, and occupies an area of 0.0798 mm². These attributes make the CG IC highly suitable for compact, low-power bio-impedance applications. Full article

This paper presents a first-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, (supply) voltage, and temperature (PVT)-insensitive closed-loop integrator and data-weighted averaging (DWA). The use of a cascode floating inverter amplifier (FIA)-type dynamic amplifier with high gain enables an aggressive noise transfer function while minimizing the power consumption associated with the use of an active filter. In the proposed ADC, the residue is generated by a capacitive digital-to-analog converter (CDAC) employing DWA, which is made possible by employing a second CDAC, which operates after the SAR operation is completed. The proposed ADC is designed with a 28 nm CMOS process with 1 V power supply. The simulation results show that the ADC achieves the SNDR of 71.2 dB and power consumption of 228 μW when operated with a sampling rate of 80 MS/s and oversampling ratio (OSR) of 10. The Schreier figure-of-merit (FoM) is 173.6 dB, and Walden FoM is 9.6 fJ/conversion-step. Full article

The video camera is essential for reliable activity monitoring, and a robust analysis helps in efficient interpretation. The systematic assessment of classroom activity through videos can help understand engagement levels from the perspective of both students and teachers. This practice can also help in robot-assistive classroom monitoring in the context of human–robot interaction. Therefore, we propose a novel algorithm for student–teacher activity recognition using 3D CNN (STAR-3D). The experiment is carried out using India’s indigenously developed supercomputer PARAM Shivay by the Centre for Development of Advanced Computing (C-DAC), Pune, India, under the National Supercomputing Mission (NSM), with a peak performance of 837 TeraFlops. The EduNet dataset (registered under the trademark of the DRSTA^TM dataset), a self-developed video dataset for classroom activities with 20 action classes, is used to train the model. Due to the unavailability of similar datasets containing both students’ and teachers’ actions, training, testing, and validation are only carried out on the EduNet dataset with 83.5% accuracy. To the best of our knowledge, this is the first attempt to develop an end-to-end algorithm that recognises both the students’ and teachers’ activities in the classroom environment, and it mainly focuses on school levels (K-12). In addition, a comparison with other approaches in the same domain shows our work’s novelty. This novel algorithm will also influence the researcher in exploring research on the “Convergence of High-Performance Computing and Artificial Intelligence”. We also present future research directions to integrate the STAR-3D algorithm with robots for classroom monitoring. Full article

The capacitor mismatch among diverse defects caused by variations in the manufacturing process significantly affects the linearity of the capacitor array used to implement the capacitive digital-to-analog converter (CDAC) in the successive-approximation register (SAR) analog-to-digital converter (ADC). Accordingly, the linearity of the SAR ADC is limited by that of capacitor array, resulting in serious yield loss. This paper proposes an efficient foreground self-calibration technique to enhance the linearity of the SAR ADCs by mitigating the capacitor mismatch based on the split ADC architecture along with variable capacitors. In this work, two ADC channels (i.e., ADC1 and ADC2) for the split ADC architecture include their capacitive DACs (CDACs) whose binary-weighted capacitor arrays consist of variable capacitors. A charge-sharing SAR ADC is used for each ADC channel. In the normal operation mode, their digital outputs are averaged to be the final ADC output, as in a conventional split ADC. In the calibration mode, every single binary-weighted capacitor for the two ADCs is sequentially calibrated by making parallel or/and antiparallel connection among two or thee capacitors from the two channels. For instance, because the capacitors of the CDACs ideally exhibit the binary-weighted relation as $C_n=2\times C_{n-1}$, the variable capacitor $C_n$ of ADC1 can be updated to be closest to the sum of $C_{n-1}$ of ADC1 and $C_{n-1}$ of ADC2 for the calibration. For the process, the two capacitor arrays of the two ADCs can be reconfigured to be connected to each other, so that the $C_n$ of ADC1 can be connected with two of the $C_{n-1}$ of ADC1 and ADC2 in antiparallel. The two voltages at the top and the bottom plates of the CDAC are compared by a comparator of ADC1, and the comparison results are used to update $C_n$. This process is iterated, until $C_n$ is in agreement with the sum of two of $C_{n-1}$. Finally, all the capacitors can be calibrated in this way to have the binary-weighted relation. The simulation results based on the proposed work with a split SAR ADC model verified that the proposed technique can be practically used, by showing that the total harmonic distortion and the signal-to-noise-and-distortion ratio were enhanced by $21.8$ dB and $6.4$ dB, respectively. Full article

This paper presents an implementation of a 14-bit 2.5 MS/s differential Successive-Approximation-Register (SAR) analog-to-digital converter (ADC) to be used for sensing multiple analog input signals. A differential binary-weighted with split capacitance charge-redistribution capacitive digital-to-analog converter (CDAC) utilizing the conventional switching technique is designed, without using any calibration mechanism for fast power-on operation. The CDAC capacitor unit has been optimized for improved linearity without calibration technique. The SAR ADC has a differential input range 3.6 V_pp, with a SNDR of 80.45 dB, ENOB of 13.07, SFDR of 87.16 dB and dissipates an average power of 0.8 mW, while operating at 2.5 V/1 V for analog/digital power supply. The INL and DNL is +0.22/−0.34 LSB and +0.42/−0.3 LSB, respectively. A prototype ADC has been fabricated in a conventional CMOS 65 nm technology process. Full article

This article describes the design and performance analysis of a charge domain mixed-signal multiply-accumulator (MAC) using RDAC, CDAC, and SAR-ADC with an 8-bit resolution for input, weight, and output. The arithmetic accuracy is mainly determined by the ADC, and the gain error has a significant impact. The mismatches and thermal noises of the RDAC and the CDAC are averaged by the number of multiply-accumulate units m connected to one ADC. As a result, if m is large enough, mismatches and thermal noises have a limited impact on the computation accuracy. Most of the computational energy is determined by the energy consumed by the SAR-ADC, and the computational energy per operation can be reduced by increasing m. This last metric is mainly determined by the charge and discharge energy of the CDAC for sufficiently large m values. Furthermore, since RDAC consumes energy unnecessarily, the turn-off timing of RDAC should be optimized. These MAC units have been designed and prototyped using 28 nm CMOS technology, integrating 12,288 arithmetic units while operating at 180 MHz, resulting in an arithmetic speed of 4.4 TOPS. The r-MVM accuracy is about 1% and a high energy efficiency of 240 TOPS/W as a MAC macro and 64.4 TOPS/W as a system has been achieved. Full article

CDAC (coulometrically determined antioxidant capacity) involves the determination of the antioxidant capacity of individual compounds or their mixtures using constant-current coulometry, with electrogenerated Br₂ as the titrant, and biamperometric detection of the endpoint via Br₂ excess. CDAC is an accurate, sensitive, rapid, and cheap measurement of the mol electrons (mol e⁻) transferred in a redox process. In this study, the CDAC of 48 individual antioxidants commonly found in foods has been determined. The molar ratio CDAC (CDACχ, mol e⁻ mol⁻¹) of representative antioxidants is ranked as follows: tannic acid > malvidin-3-O-glucoside ≃ curcumin > quercetin > catechin ≃ ellagic acid > gallic acid > tyrosol > BHT ≃ hydroxytyrosol > chlorogenic acid ≃ ascorbic acid ≃ Trolox^®. In many cases, the CDACχ ranking of the flavonoids did not comply with the structural motifs that promote electron or hydrogen atom transfers, known as the Bors criteria. As an accurate esteem of the stoichiometric coefficients for reactions of antioxidants with Br₂, the CDACχ provides insights into the structure–activity relationships underlying (electro)chemical reactions. The electrochemical ratio (ER), defined as the antioxidant capacity of individual compounds relative to ascorbic acid, represents a dimensionless nutritional index that can be used to estimate the antioxidant power of any foods on an additive basis. Full article

This paper proposes a 10-bit 400 MS/s dual-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) immune to offset mismatch between channels. A novel comparator multiplexing structure is proposed in our design to mitigate comparator offset mismatch between channels and improve ADC dynamic performance. Compared to traditional TI-SAR ADC utilizing offset calibration technique, hardware and power consumption overhead are minimized in our design. In addition, a split capacitive digital-to-analog converter (CDAC) and a double-tail dynamic comparator using the clock decoupling technique were applied to eliminate comparator common mode input voltage shift, ensuring conversion accuracy and boosting speed. A 400 MS/s 10-bit dual-channel TI-SAR ADC with comparator multiplexing was designed in 40 nm CMOS and compared to the conventional one. The simulated ADC ENOB and SFDR with 6σ offset mismatch were improved from 5.0-bit and 32.2 dB to 9.7-bit and 77.2 dB, respectively, confirming the merits of the proposed design compared to current state-of-the-art works. Full article