A High-Speed 8-Bit Single-Channel SAR ADC with Tailored Bit Intervals and Split Capacitors ^†

Abstract

As wireless communication systems continue to demand higher data transmission rates, the need for analog-to-digital converters (ADCs) with a higher sampling rate becomes increasingly critical. However, traditional successive approximation register (SAR) ADCs operating at 1 bit/cycle often face speed limitations due to the fixed bit intervals and comparator regeneration delays, which constrain their scalability in advanced technology nodes. To address these challenges, this paper presents a high-speed 8-bit single-channel SAR ADC featuring a novel delay generation circuit that enables tailored bit intervals (TBIs) to reduce conversion latency. A split capacitive digital-to-analog converter (CDAC) is employed to suppress input common-mode voltage shifts, while inverted dynamic latch pairs and early capacitor reset techniques are introduced to improve conversion speed. The proposed ADC is implemented in a 16 nm CMOS process, occupying only 0.0012 mm². Post-layout simulations across extreme process and temperature corners validate the robustness of the design. The TBI-ADC achieves an effective number of bits (ENOB) of 7.20 bits at Typical–Typical (TT) 25 °C with a power consumption of 6.94 mW. Furthermore, it reaches a sampling rate of 1.6 GS/s at Fast–Fast (FF) −40 °C, representing a 33% improvement over the fastest previously reported single-channel, 1 bit/cycle, 8-bit SAR ADC.

1. Introduction

In recent years, high-speed time-interleaved (TI) analog-to-digital converters (ADCs) have been widely adopted in advanced wireline communication systems [1,2,3,4,5,6,7]. In particular, SerDes designs targeting 112 Gbps long-reach (LR) ethernet physical layer (PHY) links demand low-power, high-speed ADCs operating at sampling rates of 56 GS/s or higher. This has created a strong need for the design of GHz-rate single-channel ADCs that can be further scaled through time-interleaving to meet such high aggregate sampling rate requirements. Successive approximation register (SAR) ADCs [8,9,10,11,12,13] are extensively used in TI systems due to their high power efficiency and compact sizes. To meet the growing demand for higher sampling rates, high-speed ADCs are increasingly implemented in advanced technology nodes. However, conventional SAR ADCs, operating at 1 bit/cycle, face speed limitations due to the fixed bit intervals and comparator regeneration delays. Notably, these delays become more significant in scaled technologies, limiting the scalability of SAR architectures.

Fundamentally, SAR ADCs can be classified as synchronous or asynchronous based on the type of control clock. The synchronous ADC requires a high-frequency external clock that significantly exceeds the sampling rate, with the comparator being triggered by the edges of this clock signal. In contrast, the asynchronous ADC can autonomously generate the next comparison clock by detecting the edge of the comparison completion signal, thus saving the time wasted for the fastest decision and external high-speed clock from synchronous SAR [14], which is suitable for high-speed designs. In recent high-speed designs, the bit cycle period is further reduced by overlapping the comparator reset delay, the latch delay, the logic delay, and the capacitive digital-to-analog converter (CDAC) delay, as can be seen from our previous work [15]. After each comparison, the comparator is reset; simultaneously, the output of the comparator controls the switching of the corresponding capacitor through SAR logic. Starting a comparison without sufficient CDAC settling time will result in error codes.

For an asynchronous SAR ADC, the minimum length of the synchronous clock period T is given by the following:

$$T\ge t_{t\&h}+\sum _{i=1}^n{T}_i,$$

(1)

where $t_{t\&h}$ and $T_i$ represent the track and hold time and the i-th conversion time, respectively. The expression for $T_i$ is given by the following:

$$T_i\ge t_{compi}+\max \{t_{Dlatch}+t_{CDACi},t_{logic}+t_{rst\_compi}\},$$

(2)

where $t_{compi}$, $t_{Dlatch}$, $t_{CDACi}$, $t_{logic}$, and $t_{rst\_compi}$ denote the time for the i-th comparison, the time for the latch, the time for the CDAC conversion, the time for the logic delay, and the i-th reset time of the comparator, respectively. To further reduce the time needed in conversion, an ADC with two or eight comparators is proposed for comparator reset-time saving [16,17] while consuming more area and calibrations. In [18], a “look-ahead” SAR architecture is proposed that raises the speed by 2, but at the cost of quadruple CDACs and comparators. In [19], $t_{rst\_comp}$ is reduced by tailoring the size of the loading transistors in the comparator. In [20], a semi-asynchronous timing scheme is introduced to remove the logic delay from the critical path by overlapping the comparator, the CDAC, and the logic operations, which also needs an external high-frequency clock. However, the delay logic must accommodate the slowest most significant bit (MSB) settling to ensure adequate voltage settling, and this extension of time results in wasted time for voltage settling of the lower bits. To minimize bit delays, complex algorithms and calibrations are often employed [21,22] to adjust the intervals for CDAC conversion, which results in additional circuits and power consumption. In [23,24], the two-/three-step tapered bit period method is proposed. However, due to limitations in the delay adjustment logic, it is unable to tailor the delay for each bit to minimize the conversion time. In addition, the logic increases the minimum delay of the comparator clock cycle. In [25], a method is proposed to optimize device sizing by tailoring the delay for different bit intervals, aiming to reduce power consumption in SAR ADCs. However, this approach, which is advantageous for reducing the conversion time in SAR ADCs, has not been applied to high-speed SAR ADCs, especially with sampling rates exceeding 1 GS/s.

To solve the above-mentioned problem, a novel tailored bit interval (TBI) logic for high-speed SAR ADCs is proposed. This circuit does not require complex control codes or delay circuits, yet it allows for tailoring the delay for each bit interval as needed. A high-speed 8-bit SAR ADC utilizing this delay logic is introduced. In this design, we discover that for high-speed SAR ADCs with sampling rates exceeding 1 GS/s, the delay of the LSBs is not determined by $t_{Dlatch}+t_{CDACi}$, but rather by $t_{logic}+t_{rst\_compi}$. According to this, the delay logic is further simplified and optimized. Additionally, several techniques are deployed to improve speed and reduce mismatches between sub-SAR ADCs. The major contributions of this work are as follows:

1.

This paper provides a thorough analysis of the constraints that determine asynchronous time intervals during the conversion phase, and a brand-new delay adjustment logic for TBI is proposed, which serves as the basis for proposing an approach for high-speed SAR-ADC circuits.

2.

Based on the analysis, a high-speed SAR ADC is designed, presenting an 8-bit SAR ADC circuit implementation. Inverted dynamic latch pairs and early reset of capacitors are employed to improve speed. Split capacitive digital-to-analog converters (CDACs) by the latch pairs are employed to mitigate common-mode voltage shifts.

3.

The post-layout simulation shows an effective number of bits (ENOB) of 7.20 bits at Typical–Typical (TT) 25 °C with a power consumption of 6.94 mW. With a sampling rate exceeding 1 GS/s across all process corners, our circuit also has the potential for application in high-speed multi-channel time-interleaved ADCs.

The paper is organized as follows: Section 2 introduces the theoretical foundation of the asynchronous clock cycle and derives the formula for the asynchronous clock period. Section 3 presents the design of the high-speed TBI-SAR-ADC circuit and describes each part of the circuit in detail. Section 4 showcases the simulation results. Finally, the conclusions are summarized in Section 5.

2. Analysis of CDAC Settling

Figure 1a illustrates the basic block diagram of an asynchronous SAR ADC, while Figure 1b shows the timing relationship between the asynchronous $asy\_CLK$ and external synchronous $CLK$ during a single sampling and conversion cycle. During the high phase of $CLK$, the CDAC tracks the input signal. The falling edge of $CLK$ triggers the asynchronous clock generation logic to produce a high-level voltage, initiating the first comparison. The asynchronous clock $asy\_CLK$ in the subsequent loops are generated based on the comparator output. After all bit decisions are completed, the asynchronous clock is reset to low.

Traditional SAR ADCs use the binary search algorithm to convert from the most significant bit (MSB) to the least significant bit (LSB) using comparators. During the conversion, the bottom plate of the capacitors is switched between the reference voltages based on the previous bit. The charge redistribution on the top plate of the capacitors then generates the input voltages for the next comparison. The timing relationships for each conversion are shown in Figure 2.

It can be seen that in the ideal case, the delay between two comparisons depends on the maximum of the CDAC path and the comparator reset path.

For the first m among n conversions, the following equation is satisfied:

$$t_{register}+t_{CDACi}>t_{logic}+t_{rst\_comp}(1\le i\le m),$$

(3)

where $t_{register}$ denotes the input–output delay of the register storing the comparison result, $t_{CDACi}$ denotes the i-th settling time of the CDAC, $t_{logic}$ denotes the total delay of the comparator clock generation module, and $t_{rst\_comp}$ denotes the comparator reset time. Supposing $t_{logic}$ and $t_{rst\_comp}$ are the same in every loop, we now derive the ideal minimum time of conversion from the following:

$$t_{conversion}=\sum _{k=1}^n{t}_{com{p}_k}+\sum _{k=1}^m{t}_{register}+\sum _{k=1}^m{t}_{CDA{C}_k}+(n-m)(t_{logic}+t_{rst\_comp}),$$

(4)

where $t_{com{p}_k}$ denotes the time needed for the k-th comparison.

The duration of $t_{CDACi}$ depends on the choice of capacitor weighting scheme. In the following, the CDAC settling time $t_{CDACi}$ is derived for both binary-weighted (radix-2) and non-binary (with redundancy) schemes. In the conventional radix-2 scheme where the capacitors are binary weighted from MSB to LSB, the CDAC settling error needs to be within 1/2 LSB in each loop before the next comparison, to tolerate the effects of both comparator noise and other distortion. To attain accurate comparison results, the comparator has to be clocked right away or after when the DAC settles. This means that the clock generation module needs to add some delay to accommodate the DAC settling of the MSB. From this, we obtain a new expression for the conversion time after circuit implementation:

$$t_{conversion}=\sum _{k=1}^n{t}_{com{p}_k}+n{t}_{register}+n{t}_{CDA{C}_1},$$

(5)

This means, for the lower conversion bits, there is unnecessary waiting time before the next comparison starts. For this reason, many studies have designed logic units with adjustable delays to approach the ideal conversion time in Equation (4). However, the adjustable delay unit usually extends the fixed delay in the comparator reset path for the complex logic, and increasing the precision of delay control also adds complexity to the control unit, making it more challenging to precisely control the delay of each loop [23,24].

In recent years, non-binary (sub-radix-2) capacitor circuits have been developed to allow us to clock slightly before the DAC settles. This approach not only relaxes the design requirements for delay logic but also tolerates more dynamic errors, such as insufficient DAC settling and comparator kickback. Below, we begin analyzing the delay under these two capacitor weighting schemes.

For an n-bit SAR ADC (whether using a binary or non-binary CDAC), in order to represent $2^n$ different values, the capacitance value $C_i$ for each conversion bit must satisfy the following condition:

$$C_i\le \sum _{k=1}^{i-1}{C}_k,$$

(6)

where the right side of the inequality represents the sum of the capacitance values of the lower $(i-1)$ bits. For non-binary capacitor weights, the redundancy weight of the i-th conversion can be calculated using the following formula:

$$w_{redundan{t}_i}=\sum _{k=1}^{i-1}{w}_k-w_i,$$

(7)

where the weight and the redundancy weight of the i-th conversion are denoted as $w_i$ and $w_{redundan{t}_i}$. The i-th CDAC conversion requires sufficient time for the settling voltage to fall within the acceptable redundancy range so that the accuracy of the next comparison result is ensured as follows:

$$e^{-{\displaystyle \frac{t}{{\tau }_i}}}\le {\displaystyle \frac{w_{redundan{t}_i}}{2^n}},$$

(8)

where the time constant of the i-th conversion is denoted as ${\tau }_i$. If the capacitors are binary weighted, the RC-settling error voltage needs to be less than 1/2 LSB, and the CDAC settling time will be longer, as shown in the following:

$$e^{-{\displaystyle \frac{t}{{\tau }_i}}}\le {\displaystyle \frac{\frac{1}{2}}{2^n}},$$

(9)

Take the 8-bit ADC as an example: after adding one redundant bit, its weight radix is approximately 1.81. Since the process does not allow the selection of any non-integer multiple of the unit capacitance, we need to quantize the weights. Considering the symmetry of the layout, we choose even integers as the weights. In the top-plate sampling structure we use, the MSB is generated without DAC switching, and the first comparison is made directly with voltage on the top plate, so some redundant bits of the MSB are taken to the lower parts [26]. During the first conversion, the reference buffer requires a significant amount of current to charge the top plate of the DAC capacitors. As a result, more redundancy needs to be allocated to the second-bit weight to tolerate the potential unsettling error. According to the analysis above, the weights to be selected are (LSB): 120, 56, 32, 20, 12, 8, 4, 2, 1. Calculating the magnitude of the redundancy according to Equation (7), we obtain the corresponding redundant bits (LSB) as follows: 15, 23, 15, 7, 3, 0, 0, 0, 0.

Thermal noise is one of the main considerations when selecting the unit capacitance value $Cu$. The following relation should be satisfied:

$${\displaystyle \frac{2kT}{C_{single,total}}}\le {\displaystyle \frac{(\frac{Vref}{2^n}{)}^2}{12}},$$

(10)

where $C_{single,total}$ means the single-ended sampling capacitance, and $Vref$ represents reference voltage. Ideally, if only the capacitance in the CDAC (with no parasitic capacitance) is considered, then $C_{single,total}=128Cu$. Then, $Cu$ must be at least 0.1 fF to make ENOB at least 7.5 bits. Considering the process limit, non-ideal factors, and higher ENOB, the unit capacitor value is chosen as 0.732 fF.

3. Circuit Implementation

As shown in Figure 3, the circuit uses the top-plate sampling technique, where the input voltage is directly sampled on the top plate of the capacitors, and eliminates the need for the CDAC switching before the first comparison. The conversion phase undergoes nine quantization steps, including one redundant bit, which ultimately reaches 8-bit precision. The timing diagram of the overall circuit can be seen in Figure 4. The bit weights are chosen as mentioned in Section 2.

3.1. Split Capacitors

Large common-mode variations at the comparator inputs may lead to dynamic errors, such as offset (the Monte Carlo simulations in Section 4 demonstrate the impact of common-mode voltage (VCM) shift on the comparator’s offset), which can impact accuracy. To mitigate this influence, split capacitors are used. The simultaneous conversion of the CDAC at both the $in$ and $ip$ terminals ensures speed and maintains the common-mode voltage at the comparator input.

During tracking, the bottom plates of 64 unit capacitors at the $in$ terminal are connected to $VRP$ (the voltage is 0.7 V), while 63 unit capacitors are connected to $VRN$ (the voltage is 0 V), and the $ip$ terminal is connected oppositely. After sampling, at the falling edge of the synchronous clock, the first comparison is triggered. After the comparator resolves its result, the switches corresponding to the capacitors are switched at the $in$ and $ip$ terminals, as shown in the lower part of Figure 5.

In the final conversion, only the switches corresponding to the capacitors on one terminal (either $in$ or $ip$) are switched. Since the voltage change during this final conversion is minimal, the resulting common-mode variation has a negligible impact on the comparator’s accuracy. This approach reduces the number of capacitors required by half compared to a conventional split capacitor method, which is particularly advantageous for multichannel interleaved ADCs with high bandwidth.

3.2. SAR Logic

In order to maintain a constant VCM, the differential terminals of the CDAC need to convert oppositely driven by the registers. Adding an inverter after the dynamic latch in [27] to drive the other differential output would increase the delay of the critical path. To address this, we propose a pair of inverted dynamic latches $Dyn\_n$ and $Dyn\_p$, as shown in Figure 6. These latches, each driven by the enable clocks $E{N}_i$ and $EN\_b_i$, can directly pass the comparison result to the CDAC switches within their active periods without the need to store the result. The enable clocks [26], requiring the $Rdy$ signal which is generated as shown in Figure 7, are activated half an asynchronous clock cycle before the comparator outputs. Therefore, when the comparator finishes resolving, the results are fed directly into the dynamic latch without waiting for a clock edge. Taking $Dyn\_n$, for example, when $E{N}_i$ is low, the drain of the input NMOS is charged to $VDD$. When $E{N}_i$ is high, the voltage at the drain tracks the input voltage. There is only the input–output delay of the dynamic latch between the generation of the comparator’s result and the switches of the CDAC. The outputs of $Dyn\_n$ and $Dyn\_p$ are reset to 0 or 1, respectively, at the end of the last conversion, where an early reset is introduced in Section 3.4. The output of $Dyn\_n$/$Dyn\_p$ is connected to a $keeper$, a pair of back-to-back inverters. This is used to prevent charge leakage, which could otherwise lead to changes in the output voltage and subsequently affect the state of the switches.

3.3. Delay Generation Logic

From the analysis in Section 2, it can be concluded that the minimum delay between two consecutive comparisons depends on the maximum of the comparator reset path and the CDAC settling path. The latter is determined by the bit weight and the corresponding redundancy. Therefore, the delay for each loop may vary. Based on this, this work proposes a novel delay adjustment circuit that allows the tailoring of each bit interval.

The delay adjustment logic is easy to implement and does not introduce additional delay. As shown in Figure 7, it uses only three logic gates to generate the comparator clock. By controlling the number of PMOS transistors that are turned on, the current to VDD is controlled, thereby adjusting the delay for the transition from “0” to “1”. The circuit only increases the delay of the reset path without extending the “1” duration of the comparator clock. For example, when eight different reset path delays are required, eight sets of PMOS transistors are controlled by the eight enable clocks $EN\_b_9$ to $EN\_b_2$, with each set containing a different number of PMOS transistors, resulting in varying delay lengths. In addition, the $rst$ signal is used to stop generating the comparator clock $CLKcmp$. The target tailored delay of each bit cycle, for example, $t_1,t_2,t_3$, is shown in Figure 4. When the PMOS transistor size is smaller than 1 finger × 4 fins, it cannot sufficiently drive the subsequent circuit. When the size exceeds 12 fingers × 4 fins, the transistor’s intrinsic load becomes too large, preventing further delay reduction. The measured delay range in post-layout simulation is 20–38 ps under Fast-Fast (FF) at −40 °C, 31–45 ps under TT at 25 °C and 39–55 ps under Slow-Slow (SS) at 110 °C.

3.4. Early Reset of Dynamic Latch

Conventional ADC papers rarely mention the time consumed for resetting capacitor bottom plates. However, this is a critical consideration in high-speed ADC design. When the bottom plates of the capacitors are reset to the initial state, for example, with half connected to $VRP$ and half connected to $VSS$ in this implementation, a large current is required from the reference buffer. The limited driving capability restricts the reset speed, and it can take more than 100 ps. However, for multichannel interleaved ADCs with several stages of sampling, the final sampling switch may only be turned on for tens of picoseconds, which is not enough for the capacitors to reset. Thus, achieving an early reset is crucial; without it, a longer delay is needed before the next sampling period, and the maximum sampling rate may be limited, or the power consumption and area of the reference buffer could increase.

In this work, we propose a detection mechanism to early reset the capacitors, as shown in Figure 8. This mechanism allows for an early reset by detecting whether the ninth comparison is complete; otherwise, it will be reset by the external synchronized clock. During the capacitor reset process and before the next sampling, operations such as the comparator calibration can still be performed. Considering the limited driving capacity of the buffer, the ninth group of the latches, together with $Lup$s and $Ldn$s, are synchronized with the external clock. Since their outputs no longer control the capacitor switching, the reset only needs to be finished before the next conversion starts.

4. Post-Simulation Results

Figure 9 shows the delays in the reset of the comparator, settling of the CDAC, and the comparator delay logic in three process corners, FF at −40 °C, TT at 25 °C, and SS at 110 °C. It illustrates the minimum delay required to satisfy Equations (8) and (9) for the CDAC settling time. As can be seen, the sub-radix-2 scheme effectively reduces the minimum time for the CDAC settling. In the delay logic design, it is crucial to ensure that during the first conversion, the path delay is greater than the CDAC settling time under the worst process corner. From the second loop, the reset time exceeds the CDAC settling time. Therefore, the path delay is determined by the comparator resetting time. Thus, two groups of delays are required in this ADC design ($t_1>t_2=t_3$), as outlined in Section 3.3. The first PMOS group is controlled by $E{N}_9$, and the second remains permanently open. This means that when a longer delay is needed, a portion of the PMOS transistors is turned off.

The TBI results in a 36.9% reduction in the total path delay compared to not using any delay adjustment. In addition, other more complex delay adjustment methods would increase the inherent delay of the reset path [23,24].

Figure 10 shows the Monte Carlo simulation results for the offset of the double-tail comparator, with 1000 points running at common-mode voltages of 0.15 V (NMOS-based), 0.3 V (NMOS-based), 0.45 V (NMOS-based), and 0.3 V (PMOS-based). It can be observed that during conversion when using the NMOS-based comparator, the VCM shift caused by monotonic conversion results in a higher probability of a large offset near the LSB (VCM = 0.15 V). Additionally, as VCM decreases, the comparator’s latency of sampling and propagation increases, which may increase the total conversion time. In contrast, when using a PMOS-based comparator, although the latency decreases with a reduction in VCM, the 3$\sigma$ offset increases significantly.

The proposed 8-bit SAR ADC with TBI is implemented in 16 nm FinFET technology. We use Virtuoso for initial design and simulation, Quantus for parasitic extraction. We use the 0.366 fF CSFMOM as a unit capacitor after splitting. Monte Carlo simulations in Virtuoso reveal a 3$\sigma$ mismatch of 2.85% for a single capacitor, resulting in a maximum INL of 0.455 LSB.

Figure 11 shows the layout of the proposed TBI-ADC, with the CDAC, the comparator, and the SAR logic, occupying only 0.0012 mm². The post-layout simulation results, including the highest sampling rates, effective number of bits (ENOB), across various temperatures and process corners, are presented in

Table 1. TBI-SAR-ADC performance of post-layout simulation at different corners.

Model	LPE Type	VDD = 0.9V	Temp.	Max. S. R.	ENOB
TT	RCtypical	nominal	25 °C	1.3 GS/s	7.20@1 GS/s
FF	RCbest	1 + 10%	−40 °C	1.6 GS/s	7.21@1.3 GS/s
FF	RCbest	1 + 10%	110 °C	1.4 GS/s	7.18@1 GS/s
SS	RCworst	1 − 10%	−40 °C	1.05 GS/s	7.05@0.9 GS/s
SS	RCworst	1 − 10%	110 °C	1 GS/s	7.08@0.8 GS/s

.

Table 2. Performance comparison between this work (post-layout simulation) and state-of-the-art silicon-proven SAR ADCs.

JSSC [20]	JSSC [16]	TCAS1 [28]	ISSCC [29]	This Work
Technology	28 nm	32 nm SOI	28 nm FDSOI	40 nm	16 nm FinFET
ADC Type	SAR	2-compSAR	LU-SAR	ci-SAR	SAR
Supply [V]	1.0	1.0	1.0	1.0	1.0        0.9
$f_s$ [GS/s]	1	1.2	0.8	1	1.6       1.3 (max)
Resolution [bit]	7	8	8	6	8
SFDR [dB]	52.0	49.8	50.7	49.7	56.2      53.5    @1.3 & 1 GS/s
SNDR [dB]	40.1	39.3	42.6	34.6	45.1      45.1    @1.3 & 1 GS/s
FOMw [fJ/conv.-s]	34.4	34	22.8	28.7	26.0      24.3    @1.3 & 1 GS/s

compares the post-layout performance of our TBI-ADC under TT and FF process corners with other silicon-proven state-of-the-art designs. In [20], to enhance the ADC speed, the SAR logic operates in parallel to the comparator, eliminating its timing from the critical loop by introducing a semi-asynchronous timing scheme. In [16], high-speed operation is achieved by converting each sample with two alternate comparators clocked asynchronously. In [28], multiple comparators are used to reduce the SAR loop delay, thus improving speed. In [29], a charge-injection SAR is introduced, and the ADC achieves GHz sampling speed and reduces area by more than half. The input signal frequency in our design is at the Nyquist frequency, and correlated sampling is employed. The output results are processed using a 1024-point FFT to obtain the ENOB. Notably, at the FF −40 °C and TT 25 °C corner, the highest sampling rate reaches 1.6 GS/s and 1.3 GS/s respectively, showing a 33% and 8.3% improvement over the fastest previously reported single-channel, 1 bit/cycle, 8-bit SAR ADC. Even under the SS process corner, this TBI-ADC exhibits competitive performance.

Figure 12 shows the post-layout 1024-point FFT simulation results for an input frequency at the TT 25 °C and FF −40 °C process corner. The post-layout simulated power consumption extracted at TT 25 °C RC typical is 6.94 mW, the CDAC consumes 5.34%, the logic 25.4%, and the comparator and its clock generation part 70%. If the efficiency and speed of the comparator are further optimized, the overall power consumption will improve significantly.

5. Conclusions

In this work, a thorough analysis of the delay in the CDAC settling of the asynchronous SAR ADC is given, and a novel TBI logic for high-speed ADCs is proposed. Inverted dynamic latch pairs and early reset of capacitors are employed to improve speed. A split CDAC is employed to mitigate common-mode voltage shifts. Simulated using the 16 nm process, the design demonstrates robust performance across various process corners. The post-simulation results show an ENOB of 7.20 bits at TT 25 °C and 7.21 bits at FF − 40 °C with a power consumption of 6.94 mW and 7.43 mW, respectively and a maximum sampling rate of 1.6 GS/s at FF −40 °C, demonstrating its potential for high-speed ADC applications. However, as technology scales, the conversion time becomes increasingly limited by the comparator reset time. Therefore, realizing a faster conversion loop with lower area overhead will be the focus of future research.