Search Results (565)

The switching characteristics of GaN HEMT devices exhibit a very complex dynamic nonlinear behavior and multi-physics coupling characteristics, and traditional switching current models based on physical mechanisms have significant limitations. This article adopts a hybrid architecture of convolutional neural network and long short-term memory network (CNN-LSTM). In the 1D-CNN layer, the one-dimensional convolutional neural network can automatically learn and extract local transient features of time series data by sliding convolution operations on time series data through its convolution kernel, making these local transient features present a specific form in the local time window. In the double-layer LSTM layer, the neural network model captures the transient characteristics of switch current through the gating mechanism and state transfer. The hybrid architecture of the constructed model has significant advantages in accuracy, with metrics such as root mean square error (RMSE) and mean absolute error (MAE) significantly reduced, compared to traditional switch current models, solving the problem of insufficient accuracy in traditional models. The neural network model has good fitting performance at both room and high temperatures, with an average coefficient close to 1. The new neural network hybrid architecture has short running time and low computational resource consumption, meeting the needs of practical applications. Full article

In this paper, a novel 4H-SiC LDMOS structure with a trench heterojunction in the source (referred as to THD-LDMOS) is proposed and investigated for the first time, to enhance the reverse recovery performance of its parasitic diode. Compared with 4H-SiC, silicon has a smaller band energy, which results in a lower built-in potential for the junction formed by P+ polysilicon and a 4N-SiC N-drift region. A trench P+ polysilicon is introduced in the source side, forming a heterojunction with the N-drift region, and this heterojunction is unipolar and connected in parallel with the body PiN diode. When the LDMOS operates as a freewheeling diode, the trench heterojunction conducts first, preventing the parasitic PiN from turning on and thereby significantly reducing the number of carriers in the N-drift region. Consequently, THD-LDMOS exhibits superior reverse recovery characteristics. The simulation results indicate that the reverse recovery peak current and reverse recovery charge of THD-LDMOS are reduced by 55.5% and 77.6%, respectively, while the other basic electrical characteristics remains unaffected. Full article

AlGaN-based high-electron-mobility transistors are critical for next-generation power electronics and radio-frequency applications, yet achieving stable enhancement-mode operation with a high threshold voltage remains a key challenge. In this work, we designed p-AlGaN superlattices with different structures and performed energy band structure simulations using the device simulation software Silvaco. The results demonstrate that thin barrier structures lead to reduced acceptor incorporation, thereby decreasing the number of ionized acceptors, while facilitating vertical hole transport. Superlattice samples with varying periodic thicknesses were grown via metal-organic chemical vapor deposition, and their crystalline quality and electrical properties were characterized. The findings reveal that although gradient-thickness barriers contribute to enhancing hole concentration, the presence of thick barrier layers restricts hole tunneling and induces stronger scattering, ultimately increasing resistivity. In addition, we simulated the structure of the enhancement-mode HEMT with p-AlGaN as the under-gate material. Analysis of its energy band structure and channel carrier concentration indicates that adopting p-AlGaN superlattices as the under-gate material facilitates achieving a higher threshold voltage in enhancement-mode HEMT devices, which is crucial for improving device reliability and reducing power loss in practical applications such as electric vehicles. Full article

In this paper, preliminary gate reliability of p-GaN HEMTs under high positive gate bias is studied. Gate robustness is of great interest both from an academic and industrial point of view; in fact, different tests and models can be explored to estimate the device lifetime, which must meet some minimum product requirements, as specified by international standards (AEC Q101, JESD47, etc.). However, reliability characterizations are usually time-consuming and are performed in parallel on multiple packaged devices. Therefore, it would be useful to have a faster method to screen out weaker gate trials, already on-wafer, before reaching the packaging step. For this purpose, a room-temperature stress procedure is presented and described in detail. Then, this screening test is applied to devices with a reference gate process, and, as a result, high gate leakage degradation is observed. Afterwards, a different process implementing a dielectric layer between p-GaN and gate metal is evaluated, highlighting the improved behavior during the stress test. However, it is also observed that devices with this process suffer from very high drain leakage, and this effect is then studied and understood through TCAD (technology computer-aided design) simulations. Finally, the effect of a surface treatment performed on the p-GaN is analyzed, showing improved gate pre-reliability while maintaining low drain leakage. Full article

As transistor dimensions continue to scale below 10 nm, traditional MOSFET architectures face increasing limitations from short-channel effects, gate leakage, and variability. FinFETs, especially junctionless FinFETs on silicon-on-insulator (SOI) substrates, offer improved electrostatic control and simplified fabrication, making them attractive for deeply scaled nodes. In this work, we propose a novel Stepped-Spacer Structured FinFET (S³-FinFET) that incorporates a three-layer HfO₂/Si₃N₄/HfO₂ spacer configuration designed to enhance electrostatics and suppress parasitic effects. Using 2D TCAD simulations, the S³-FinFET is evaluated in terms of key performance metrics, including transfer/output characteristics, ON/OFF current ratio, subthreshold swing (SS), drain-induced barrier lowering (DIBL), gate capacitance, and cut-off frequency. The results show significant improvements in leakage control and high-frequency behavior. These enhancements make the S³-FinFET particularly well-suited for Field-Programmable Gate Arrays (FPGAs), where power efficiency, speed, and signal integrity are critical to performance in reconfigurable logic environments. Full article

This paper takes a look at training a generator model based on a limited dataset that can fit the distribution of the original dataset, improving the reconstruction ability of wafer datasets. High-fidelity wafer defect image generation remains challenging due to limited real data and poor physical authenticity of existing methods. We propose an enhanced StyleGANv3 framework with two key innovations: (1) a Heterogeneous Kernel Fusion Unit (HKFU) enabling multi-scale defect feature refinement via spatiotemporal attention and dynamic gating; (2) a Dynamic Adaptive Attention Module (DAAM) adaptively boosting discriminator sensitivity. Experiments on Mixtype-WM38 and MIR-WM811K datasets demonstrate state-of-the-art performance, achieving FID scores of 25.20 and 28.70 alongside SDS values of 36.00 and 35.45. The proposed method in this article helps alleviate the problem of limited datasets and makes an important contribution to data preparation for downstream classification and detection tasks. Full article

InGaN-based photovoltaic devices have attracted great attention due to their remarkable theoretical potential for high efficiency. In this paper, the influence of different distributions of step-gradient indium content within the intrinsic region on the photovoltaic performance of P-I-N type InGaN/GaN solar cells is numerically investigated. Through the comprehensive analysis of carrier dynamics, it is found that for the device with the indium content decreasing stepwise from 50% at the top to 10% at the bottom in intrinsic region, the photovoltaic conversion efficiency is increased to 10.29%, which can be attributed to joint influence of enhanced photon absorption, reduced recombination rate, and optimized carrier transport process. Full article

We report on asymmetrically shaped Fano resonances in Al_0.2Ga_0.8N/GaN-based quantum cascade structures. In order to observe this type of resonance in electro-luminescence, a spectrally narrow feature must interact with a broad, quasi-continuous emission. While the narrow waveform is provided by the GaN-based LO-phonon at 92 meV (13.5 µm, 741 cm⁻¹), the broad peak consists of overlapping inter-subband transitions between several higher-order excited states ranging from 80 to 300 meV and the ground state. Through the interference of these spectrally dissimilar peaks, a typical, asymmetric Fano line shape is generated. Full article

This paper investigates the latch-up effect in CMOS devices based on a 28 nm CMOS process within the temperature range of 200 K to 450 K using Sentaurus Technology Computer-Aided Design (TCAD) simulation, with a particular focus on the single-event latch-up (SEL) effect in the high-temperature range of 300 K to 450 K. The physical mechanism underlying the triggering of SEL in CMOS devices at high temperatures is revealed. The results show that when the linear energy transfer (LET) value is 75 MeV cm²/mg, the CMOS devices do not exhibit SEL effects at 300 K and 350 K. However, when the temperature rises to 400 K, a significant latch-up effect occurs, which becomes more pronounced with increasing temperature. Additionally, at a supply voltage of 1.2 V and a temperature of 450 K, the LET threshold for triggering SEL in CMOS devices decreases by 91.4% compared to 75 MeV cm²/mg at 300 K, dropping to 6 MeV cm²/mg. As the temperature increases, the latch-up trigger current of the CMOS devices decreases from 1.18 × 10⁻⁴ A/μm at 300 K to 4.65 × 10⁻⁵ A/μm at 450 K, and the hold voltage decreases from 1.48 V at 300 K to 1.07 V at 450 K. Full article

This paper proposes a dual-mode CMOS analog front-end (AFE) circuit for short-wave infrared (SWIR) image sensors, which integrates a hybrid readout circuit (ROIC) and a 12-bit two-step single-slope analog-to-digital converter (TS-SS ADC). The ROIC dynamically switches between buffered-direct-injection (BDI) and direct-injection (DI) modes, thus balancing injection efficiency against power consumption. While the DI structure offers simplicity and low power, it suffers from unstable biasing and reduced injection efficiency under high background currents. Conversely, the BDI structure enhances injection efficiency and bias stability via an input buffer but incurs higher power consumption. To address this trade-off, a dual-mode injection architecture with mode-switching transistors is implemented. Mode selection is executed in-pixel via a low-leakage transmission gate and coordinated by the column timing controller, enabling low-current pixels to operate in low-noise BDI mode, whereas high-current pixels revert to the low-power DI mode. The TS-SS ADC employs a four-terminal comparator and dynamic reference voltage compensation to mitigate charge leakage and offset, which improves signal-to-noise ratio (SNR) and linearity. The prototype occupies 2.1 mm × 2.88 mm in a 0.18 µm CMOS process and serves a 64 × 64 array. The AFE achieves a dynamic range of 75.58 dB, noise of 249.42 μV, and 81.04 mW power consumption. Full article

This paper investigates the short-circuit characteristics of 1.2 kV symmetrical and asymmetrical trench-gate SiC MOSFETs. Based on the self-designed short-circuit test platform, single and repetitive short-circuit tests were carried out to characterize the short-circuit capability of the devices under different electrical stresses through the short-circuit withstanding time (SCWT). Notably, the asymmetric trench structure exhibited a superior short-circuit capability under identical test conditions, achieving a longer SCWT compared to its symmetrical counterpart. Moreover, TCAD was used to model the two devices and fit the short-circuit current waveforms to study the difference in short-circuit characteristics under different conditions. For the degradation of the devices after repetitive short-circuit stresses, repetitive short-circuit pulse experiments were conducted for the two groove structures separately. The asymmetric trench devices show a positive Vth drift, increasing on-resistance, increasing C_gs and C_ds, and decreasing C_gd, while the symmetric trench devices show a negative Vth drift, decreasing on-resistance, and inverse variation in capacitance parameters. Both blocking voltages are degraded, but the gate-source leakage current remains low, indicating that the gate oxide has not yet been damaged. Full article

This investigation is centered on the analysis of frequency response characteristics of a p-i-n photodiode using InxGa_1−xAs/InP. The InGaAs/InP can be developed under three conditions: compression, tensile strain, and lattice matching. Initially, we performed calculations on strain, bandgap energy (E_g), and absorption coefficient. We then optimized the influence of indium concentration (x) on stability, critical thickness, bandgap energy, and absorption coefficient. The effects of temperature and deformation on E_g were also studied. Finally, we optimized the cutoff frequency (f_c), capacitive effects, and response frequency by considering the impact of x, active layer thickness (d), and surface area (S). For our future endeavors, we intend to explore additional parameters that may affect the p-i-n response. In future work, we can add transparent double layers in the i. InGaAs layer to reduce the transit time, leading to the development of an ultrafast photodiode. Full article

The impact-ionization-enhanced mechanism is introduced into a SiC light-triggered thyristor (LTT) to improve its switching speed under weak UV illumination. The effects of impact ionization on photogenerated carrier multiplication and the dynamic switching performance of the SiC LTT are investigated through TCAD simulation. The relationships between bias voltage, UV light intensity, and key dynamic parameters are analyzed. Simulation results indicate that when the bias voltage exceeds 14 kV, the device enters the avalanche multiplication regime, leading to a significant increase in photocurrent under a given UV intensity. As the bias voltage increases, the turn-on time of the thyristor first decreases, then saturates, and finally drops rapidly. Under UV illumination of 100 mW/cm², the turn-on time decreases from 10.1 μs at 1 kV to 0.85 μs at 18 kV, while the switching energy dissipation at 18 kV is only 1292.3 mJ/cm². These results demonstrate that the impact-ionization-enhanced effect substantially improves the switching performance of SiC LTTs. Full article

High-power laser diodes (HPLDs) are increasingly used in space applications, yet solder layer (SL) reliability critically limits their performance and lifespan. This study employs finite element analysis to evaluate SL failure mechanisms in microchannel-cooled HPLDs with two packaging configurations under thermal cycling and vibration. Based on the Anand constitutive model, contour plot analysis revealed that the critical stress–strain regions in both SLs were located at their edges. The stress–strain values along the X-axis of the SLs exceeded those in other axial directions, and SL failure would preferentially initiate from the edges along the cavity length direction. During random vibration analysis with excitation applied along the Z-axis, the equivalent stresses in both SLs exceeded X-/Y-axis levels. However, these values remained far below their yield strengths, indicating that only elastic strain and high-cycle fatigue occurred in the SLs. The calculated thermal fatigue lives of the two SLs were 2851 cycles and 5730 cycles, respectively. Their random vibration fatigue lives were determined as 5.75 × 10⁷ h and 8.31 × 10⁷ h. Using damage superposition under combined thermal-vibration loading, the total fatigue lives were predicted as 14,821 h and 29,786 h, respectively, with thermal cycling-induced damage dominating the failure mechanism. Full article