Special Issue "Design Methodologies for Power Reduction in Consumer Electronics"

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (30 September 2017)

Special Issue Editor

Guest Editor
Prof. Dr. Alexander Fish

Faculty of Engineering, Bar-Ilan University, Ramat-Gan, 52900, Israel
Website | E-Mail
Interests: low power electronics; ultra low power VLSI circuits and systems; sub/near-threshold digital logic; low power memory arrays; low power CMOS image sensors; sub-threshold asynchronous design; low power applications; analog and digital on-chip image processing

Special Issue Information

Dear Colleagues,

Advances in technology and the growth of mobile applications have made energy consumption—one of the fundamental limits on both high-performance microprocessor based systems and low- to medium-performance portable electronics—a prime concern in Integrated Circuit design. In many systems, there is a clear trade-off between energy dissipation and performance, where the cost of optimizing one results in the degradation of its counterpart. This is why achieving high performance at low energy consumption is such a challenge.

The primary goal of this Special Issue is to present original methodologies for power reduction in consumer electronics specifically in the area of design microelectronics chips in general and integrated circuits and systems in particular. Authors of original work on low-power design methodologies from the device and technology levels through circuit and architecture and up to the system level are invited to submit manuscripts for consideration.

This issue of JLPEA will feature extended papers from the IEEE international Conference on Consumer Electronics, Taipei, Taiwan, which will be held 12–14 June, 2017. Selection of invited papers will be based on their focus on low-power content and their scientific/technical excellence.

Prof. Dr. Alexander Fish
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 350 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Published Papers (4 papers)

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Research

Open AccessArticle Analysis of Sensitivity and Power Consumption of Chopping Techniques for Integrated Capacitive Sensor Interface Circuits
J. Low Power Electron. Appl. 2017, 7(4), 31; https://doi.org/10.3390/jlpea7040031
Received: 30 September 2017 / Revised: 1 December 2017 / Accepted: 3 December 2017 / Published: 7 December 2017
Cited by 1 | PDF Full-text (3448 KB) | HTML Full-text | XML Full-text
Abstract
In this paper, parameters related to the sensitivity of the interface circuits for capacitive sensors are determined. Both the input referred noise and capacitance of the input transistors are important for capacitive sensitivity. Chopping is an effective technique for signal conditioning circuits because
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In this paper, parameters related to the sensitivity of the interface circuits for capacitive sensors are determined. Both the input referred noise and capacitance of the input transistors are important for capacitive sensitivity. Chopping is an effective technique for signal conditioning circuits because of its capability of reducing circuit noise at low frequencies. The capacitive sensitivity and power consumption of various chopping techniques including the dual chopper amplifier (DCA), single chopper amplifier (SCA) and two-stage single chopper amplifier (TCA) are extracted for different values of total gain and sensor capacitance. The minimum sensitivity for each technique will be extracted based on the gain and sensor capacitance. It will be shown that designation of the amplifier and distribution of gain in the TCA and DCA are important for sensitivity. A design procedure for chopper amplifiers that illustrates the steps required to achieve either the best or the desired sensitivity while minimizing power consumption will be presented. It will be shown that for a small sensor capacitance and large total gain, the DCA has the best sensitivity, while for a large sensor capacitance and a lower gain, the SCA is preferable. The TCA is the desired architecture for an average total gain and a large sensor capacitance. Moreover, when the power consumption is the key requirement and the maximum sensitivity is not the goal; the TCA works best due to its potential to decrease the power consumption. Full article
(This article belongs to the Special Issue Design Methodologies for Power Reduction in Consumer Electronics)
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Open AccessArticle DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability
J. Low Power Electron. Appl. 2017, 7(3), 23; https://doi.org/10.3390/jlpea7030023
Received: 2 August 2017 / Revised: 29 August 2017 / Accepted: 4 September 2017 / Published: 11 September 2017
Cited by 2 | PDF Full-text (626 KB) | HTML Full-text | XML Full-text
Abstract
To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tools, however, cover only a few memory technologies,
[...] Read more.
To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tools, however, cover only a few memory technologies, technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 2D/3D memories designed using SRAM, resistive RAM (ReRAM), spin transfer torque RAM (STT-RAM), phase change RAM (PCM) and embedded DRAM (eDRAM) and 2D memories designed using spin orbit torque RAM (SOT-RAM), domain wall memory (DWM) and Flash memory. In addition to single-level cell (SLC) designs for all of these memories, DESTINY also supports modeling MLC designs for NVMs. We have extensively validated DESTINY against commercial and research prototypes of these memories. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g., latency, area or energy-delay product) for a given memory technology, choosing the suitable memory technology or fabrication method (i.e., 2D v/s 3D) for a given optimization target, etc. We believe that DESTINY will boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers. The latest source-code of DESTINY is available from the following git repository: https://bitbucket.org/sparshmittal/destinyv2. Full article
(This article belongs to the Special Issue Design Methodologies for Power Reduction in Consumer Electronics)
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Open AccessArticle Ultra-Low Power Consuming Direct Radiation Sensors Based on Floating Gate Structures
J. Low Power Electron. Appl. 2017, 7(3), 20; https://doi.org/10.3390/jlpea7030020
Received: 21 June 2017 / Revised: 23 July 2017 / Accepted: 28 July 2017 / Published: 31 July 2017
PDF Full-text (6546 KB) | HTML Full-text | XML Full-text
Abstract
In this paper, we report on ultra-low power consuming single poly floating gate direct radiation sensors. The developed devices are intended for total ionizing dose (TID) measurements and fabricated in a standard CMOS process flow. Sensor design and operation is discussed in detail.
[...] Read more.
In this paper, we report on ultra-low power consuming single poly floating gate direct radiation sensors. The developed devices are intended for total ionizing dose (TID) measurements and fabricated in a standard CMOS process flow. Sensor design and operation is discussed in detail. Original array sensors were suggested and fabricated that allowed high statistical significance of the radiation measurements and radiation imaging functions. Single sensors and array sensors were analyzed in combination with the specially developed test structures. This allowed insight into the physics of sensor operations and exclusion of the phenomena related to material degradation under irradiation in the interpretation of the measurement results. Response of the developed sensors to various sources of ionizing radiation (Gamma, X-ray, UV, energetic ions) was investigated. The optimal design of sensor for implementation in dosimetry systems was suggested. The roadmap for future improvement of sensor performance is suggested. Full article
(This article belongs to the Special Issue Design Methodologies for Power Reduction in Consumer Electronics)
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Open AccessArticle Starting Framework for Analog Numerical Analysis for Energy-Efficient Computing
J. Low Power Electron. Appl. 2017, 7(3), 17; https://doi.org/10.3390/jlpea7030017
Received: 24 April 2017 / Revised: 20 June 2017 / Accepted: 20 June 2017 / Published: 27 June 2017
Cited by 3 | PDF Full-text (715 KB) | HTML Full-text | XML Full-text
Abstract
The focus of this work is to develop a starting framework for analog numerical analysis and related algorithm questions. Digital computation is enabled by a framework developed over the last 80 years. Having an analog framework enables wider capability while giving the designer
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The focus of this work is to develop a starting framework for analog numerical analysis and related algorithm questions. Digital computation is enabled by a framework developed over the last 80 years. Having an analog framework enables wider capability while giving the designer tools to make reasonable choices. Analog numerical analysis concerns computation on physical structures utilizing the real-valued representations of that physical system. This work starts the conversation of analog numerical analysis, including exploring the relevancy and need for this framework. A complexity framework based on computational strengths and weaknesses builds from addressing analog and digital numerical precision, as well as addresses analog and digital error propagation due to computation. The complimentary analog and digital computational techniques enable wider computational capabilities. Full article
(This article belongs to the Special Issue Design Methodologies for Power Reduction in Consumer Electronics)
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