DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability
Abstract
:1. Introduction
- We have presented the motivation behind the development of DESTINY by discussing the design trends in modern processors and the limitations of existing modeling tools (Section 2).
- We have discussed the device-level data storage mechanism of each the memory technology (Section 3).
- We have now added support for modeling new memories (DWM, SOT-RAM) and MLC designs for all NVMs (including Flash). We have discussed their modeling framework and validation (Section 4.2, Section 4.3 and Section 4.4 and Section 5.1, Section 5.2, Section 5.3, Section 5.4, Section 5.5, Section 5.6 and Section 5.7).
- We have now shown the use of DESTINY in performing design-space exploration, for example finding the optimal memory technology for a given optimization target (Section 6.1), finding the optimal number of 3D layers for a given optimization target (Section 6.2), modeling assist structures (Section 6.3), etc.
- We have discussed the usefulness of DESTINY in gaining insights for designing management policies for memory structures such as cache, the register file, etc., using different memory technologies (Section 6.4).
2. Motivation and Related Work
2.1. Motivation behind the Design of DESTINY
2.2. A Comparison of Modeling Tools
3. A Background on Memory Technologies and MLC Design
3.1. Data Storage Mechanism of Memory Technologies
3.2. Multi-Level Cell Memory
3.2.1. MLC PCM and ReRAM
3.2.2. MLC STT-RAM and SOT-RAM
3.2.3. MLC Flash
4. DESTINY Modeling Framework
4.1. eDRAM Model
4.2. DWM Model
4.3. SOT-RAM Model
4.4. MLC Model
4.4.1. Read Operation Modeling
4.4.2. Write Operation Modeling for MLC PCM, ReRAM and Flash
4.4.3. Write Operation Modeling for MLC STT-RAM and SOT-RAM
4.5. 3D Model
5. Validation Results
5.1. DWM Validation
5.2. SLC SOT-RAM Validation
5.3. MLC SOT-RAM Validation
5.4. MLC STT-RAM Validation
5.5. MLC PCM Validation
5.6. MLC ReRAM Validation
5.7. MLC Flash Validation
5.8. 3D SRAM Validation
5.9. 2D and 3D eDRAM Validation
5.10. 3D ReRAM Validation
6. Design Space Exploration Using DESTINY
6.1. Finding the Optimal Memory Technology
6.2. Finding the Optimal Layer Count in 3D Stacking
6.3. Modeling Assist Structures
6.4. Gaining Insights for Designing Architectural Techniques
6.4.1. Finding the Best Memory Technology for Processor Components
6.4.2. Designing Architectural Management Techniques for Memory Technologies
7. Future Work and Conclusions
Acknowledgments
Author Contributions
Conflicts of Interest
References
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CACTI | NVSim |
---|---|
Area: 14.90 mm | Area: 6.75 mm |
Leakage: 0.574 W | Leakage: 0.395 W |
Access and random cycle time: 0.634 and 3.119 ns | Hit/miss/write latency: 2.009, 0.314 and 1.079 ns |
Read dynamic energy: 0.182 nJ | Hit/miss/write dynamic energy: 0.388, 0.032, 0.363 nJ |
Tools | SRAM | eDRAM | PCM | STT-RAM | ReRAM | SOT-RAM | Flash | DWM |
---|---|---|---|---|---|---|---|---|
CACTI(3DD) | 2D | 2D/3D | ✗ | ✗ | ✗ | ✗ | ✗ | ✗ |
NVSim | 2D | ✗ | 2D, SLC | ✗ | ||||
DESTINY | 2D/3D | 2D/3D, SLC/MLC | 2D, SLC/MLC |
Metric | Actual | DESTINY | Error |
---|---|---|---|
Area (mm) | 6.89 | 7.954 | 15.44% |
Read Latency (ns) | 5.83 | 4.424 | −24.12% |
Write Latency (ns) | 12.49 | 12.635 | 1.16% |
Shift Latency (ns) | 5.31 | 4.878 | −8.14% |
Read Energy (pJ) | 236.63 | 257.582 | 8.85% |
Write Energy (pJ) | 1032 | 1145 | 10.95% |
Shift Energy (pJ) | 214.61 | 230 | 7.17% |
Leakage Power (mW) | 163.72 | 147 | −10.21% |
Metric | Actual | DESTINY | Error |
---|---|---|---|
Read Latency (ns) | 3.8 | 3.87 | 1.84% |
Write Latency (ns) | 2.8 | 2.562 | −8.50% |
Metric | Actual | DESTINY | Error |
---|---|---|---|
Write Energy (pJ) | 1.8–3.8 | 2.29–3.25 | — |
Metric | Actual | DESTINY | Error% |
---|---|---|---|
Area (mm) | 3.42 | 3.68 | 7.69% |
Read Latency (ns) | 4.8 | 4.83 | 0.67% |
Write Latency (ns) | 21.2 | 20.46 | −3.48% |
Read Energy (pJ) | 181.01 | 192.00 | 6.07% |
Write Energy (pJ) | 349.64 | 378.00 | 8.11% |
Leakage Power (mW) | 324.54 | 324.50 | −0.01% |
Metric | Actual | DESTINY | Error |
---|---|---|---|
Write Latency (ns) | 696 | 696.96 | 0.14% |
Write Energy (pJ) | 122.92 | 122.92 | 0% |
Metric | Actual | DESTINY | Error |
---|---|---|---|
Write Latency (ns) | 160 | 157.823 | −1.36% |
Metric | Actual | DESTINY | Error (%) |
---|---|---|---|
32 nm 32 Gb MLC Flash prototype [25] | |||
Area (mm) | 159 | 148.12 | −6.84% |
56 nm 16 Gb MLC Flash [26] | |||
Area (mm) | 182 | 183.54 | 0.84% |
Design | Metric | Actual | DESTINY | Error |
---|---|---|---|---|
1 MB [23] 2 layers | Latency | 1.85 ns | 1.91 ns | 3.54% |
Energy | 5.10 nJ | 5.05 nJ | −0.98% | |
1 MB [23] 4 layers | Latency | 1.75 ns | 1.80 ns | 2.68% |
Energy | 4.5 nJ | 4.51 nJ | 0.18% | |
4 MB [24] 2 layers | Latency | 7.85 ns | 7.23 ns | −7.91% |
Energy | 0.13 nJ | 0.13 nJ | −2.59% | |
4 MB [24] 4 layers | Latency | 6.10 ns | 6.95 ns | 14.03% |
Energy | 0.12 nJ | 0.13 nJ | 4.75% | |
2 MB [24] 2 layers | Latency | 5.77 ns | 5.78 ns | 0.05% |
Energy | 0.12 nJ | 0.13 nJ | 2.74% | |
2 MB [24] 4 layers | Latency | 4.88 ns | 5.53 ns | 13.5% |
Energy | 0.12 nJ | 0.13 nJ | 8.46% | |
1 MB [24] 2 layers | Latency | 3.95 ns | 3.90 ns | −1.11% |
Energy | 0.11 nJ | 0.11 nJ | −0.13% | |
1 MB [24] 4 layers | Latency | 3.07 ns | 3.04 ns | −0.85% |
Energy | 0.11 nJ | 0.11 nJ | −0.89% |
Design | Metric | Actual | DESTINY | Error |
---|---|---|---|---|
2D 2 Mb 65 nm [5] | Latency | <2 ns | 1.46 ns | — |
Area | 0.665 mm | 0.701 mm | 5.42% | |
2D 1 Mb 45 nm [4] | Latency | 1.7 ns | 1.73 ns | 1.74% |
Area | 0.239 mm | 0.234 mm | −2.34% | |
2D 2.25 Mb 45 nm [21] | Latency | 1.8 ns | 1.75 ns | −2.86% |
Area | 0.420 mm | 0.442 mm | 5.31% | |
3D 1 Mb 2-layers[20] | Latency | <1.5 ns | 1.42 ns | — |
Area | 0.139 mm | 0.149 mm | 9.32% |
Metric | Actual | DESTINY | Error (%) |
---|---|---|---|
Read latency (ns) | 25 | 24.16 | 3.36 |
Read bandwidth (MB/s) | 305 | 315.786 | −3.54 |
Write latency (MB/s) | 17.2 | 20.13 | −17.03 |
Write bandwidth (MB/s) | 443.56 | 379 | 14.55 |
Optimization Target | Optimal Technology | Area (mm) | Read Lat. (ns) | Write Lat. (ns) | Read En. (nJ) | Write En. (nJ) | Read EDP | Write EDP | Leakage Pw. (mW) |
---|---|---|---|---|---|---|---|---|---|
Area | MLC PCM | 0.376968 | 231.679 | 1806.28 | 0.956917 | 427.855 | 221.697 | 772,826 | 3.39841 |
Read Latency | SOT-RAM | 5.41092 | 2.18991 | 1.55141 | 0.270523 | 0.368301 | 0.592421 | 0.571385 | 223.238 |
Write Latency | SOT-RAM | 4.48621 | 2.5709 | 1.43888 | 0.300592 | 0.384013 | 0.772791 | 0.552548 | 234.453 |
Read Energy | eDRAM | 4.96351 | 15.9016 | 15.8517 | 0.0621384 | 1.83554 | 0.988099 | 29.0964 | 12.0347 |
Write Energy | SRAM | 22.528 | 275.116 | 274.083 | 0.681917 | 0.032005 | 187.606 | 8.77202 | 1303.36 |
Read EDP | SOT-RAM | 3.73355 | 2.44682 | 1.58979 | 0.214578 | 0.310745 | 0.525035 | 0.494018 | 169.274 |
Write EDP | SOT-RAM | 3.73355 | 2.44682 | 1.58979 | 0.214578 | 0.310745 | 0.525035 | 0.494018 | 169.274 |
Leakage | MLC RRAM | 0.581464 | 124.354 | 529.061 | 0.608305 | 11.9998 | 75.6454 | 6348.61 | 3.51614 |
Optimization Target | Optimal D | Area (mm) | Read Lat. (ns) | Write Lat. (ns) | Read En. (nJ) | Write En. (nJ) | Read EDP | Write EDP | Leakage Pw. (mW) |
---|---|---|---|---|---|---|---|---|---|
Area | 16 | 2.6614 | 119.2630 | 125.6090 | 2.9371 | 3.1065 | 350.2820 | 390.2090 | 34.2075 |
Read Latency | 16 | 3.6750 | 3.2444 | 10.7870 | 3.1518 | 3.2280 | 10.2257 | 34.8209 | 1281.6100 |
Write Latency | 16 | 3.9662 | 3.3027 | 10.7563 | 3.3282 | 3.3734 | 10.9921 | 36.2853 | 2477.7100 |
Read Energy | 2 | 9.0916 | 127.2620 | 131.9070 | 0.2395 | 0.4362 | 30.4805 | 57.5427 | 30.0845 |
Write Energy | 2 | 13.7392 | 503.1190 | 509.8560 | 0.4479 | 0.3271 | 225.3390 | 166.7570 | 57.0693 |
Read EDP | 4 | 7.5184 | 4.4265 | 11.6705 | 0.5698 | 0.6816 | 2.5222 | 7.9541 | 787.0820 |
Write EDP | 4 | 8.0937 | 4.7674 | 11.8760 | 0.5439 | 0.6348 | 2.5929 | 7.5393 | 431.0840 |
Leakage Pw. | 1 | 16.8930 | 1813.0100 | 1810.2800 | 0.6430 | 0.6009 | 1165.6900 | 1087.8700 | 7.8901 |
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Mittal, S.; Wang, R.; Vetter, J. DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability. J. Low Power Electron. Appl. 2017, 7, 23. https://doi.org/10.3390/jlpea7030023
Mittal S, Wang R, Vetter J. DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability. Journal of Low Power Electronics and Applications. 2017; 7(3):23. https://doi.org/10.3390/jlpea7030023
Chicago/Turabian StyleMittal, Sparsh, Rujia Wang, and Jeffrey Vetter. 2017. "DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability" Journal of Low Power Electronics and Applications 7, no. 3: 23. https://doi.org/10.3390/jlpea7030023
APA StyleMittal, S., Wang, R., & Vetter, J. (2017). DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability. Journal of Low Power Electronics and Applications, 7(3), 23. https://doi.org/10.3390/jlpea7030023