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Open AccessArticle

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

by Sparsh Mittal 1,*,†, Rujia Wang 2,*,† and Jeffrey Vetter 3
1
IIT Hyderabad, Telangana 502285, India
2
Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA 15260, USA
3
Oak Ridge National Laboratory, Oak Ridge, TN 37830, USA
*
Authors to whom correspondence should be addressed.
These authors contributed equally to this work.
J. Low Power Electron. Appl. 2017, 7(3), 23; https://doi.org/10.3390/jlpea7030023
Received: 2 August 2017 / Revised: 29 August 2017 / Accepted: 4 September 2017 / Published: 11 September 2017
(This article belongs to the Special Issue Design Methodologies for Power Reduction in Consumer Electronics)
To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tools, however, cover only a few memory technologies, technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 2D/3D memories designed using SRAM, resistive RAM (ReRAM), spin transfer torque RAM (STT-RAM), phase change RAM (PCM) and embedded DRAM (eDRAM) and 2D memories designed using spin orbit torque RAM (SOT-RAM), domain wall memory (DWM) and Flash memory. In addition to single-level cell (SLC) designs for all of these memories, DESTINY also supports modeling MLC designs for NVMs. We have extensively validated DESTINY against commercial and research prototypes of these memories. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g., latency, area or energy-delay product) for a given memory technology, choosing the suitable memory technology or fabrication method (i.e., 2D v/s 3D) for a given optimization target, etc. We believe that DESTINY will boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers. The latest source-code of DESTINY is available from the following git repository: https://bitbucket.org/sparshmittal/destinyv2. View Full-Text
Keywords: cache; SRAM; eDRAM; non-volatile memory (NVM or NVRAM); STT-RAM; ReRAM; PCM; SOT-RAM; DRAM; DWM; flash; open-source; modeling tool; emerging memory technologies cache; SRAM; eDRAM; non-volatile memory (NVM or NVRAM); STT-RAM; ReRAM; PCM; SOT-RAM; DRAM; DWM; flash; open-source; modeling tool; emerging memory technologies
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Mittal, S.; Wang, R.; Vetter, J. DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability. J. Low Power Electron. Appl. 2017, 7, 23.

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