Special Issue "Hardware Security – Threats and Countermeasures at the Circuit and Logic Levels"

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (31 July 2016)

Special Issue Editors

Guest Editor
Dr. Osnat Keren

Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel
Website | E-Mail
Interests: reliable and secure circuits; security oriented codes
Guest Editor
Prof. Dr. Ilia Polian

Faculty of Computer Science and Mathematics, University of Passau, D-94030, Passau, Germany
Website | E-Mail
Interests: design and analysis of complex micro and nano-electronic circuits and systems
Guest Editor
Dr. Sanu Mathew

Circuit Research Laboratory, Intel Corporation, Hillsboro, OR, USA
E-Mail
Interests: security circuits and cryptographic hardware accelerators

Special Issue Information

Dear Colleagues,

Nowadays, we witness the transition of our society into its new, post-industrial state, characterized by a variety of electronic devices, non-limited access to various information resources, and intensive use of information technologies. Consequently, knowledge and information security have become a major concern. Along the security chain, hardware security is considered as the weakest link; the hardware leaks information, which can be used by an invasive or passive attacker to deduce details of the algorithms and cryptographic keys. The scope of this Special Issue is on all views of circuit and logic level hardware security.  This Special Issue intends to present state-of-the-art research works on area and power efficient and high performance implementations of cryptography systems, side channel threats on them, and circuit level and logic level countermeasures.

We encourage scientists and engineers, either in academic or industrial environments, to submit their original papers in order to enhance the knowledge, expertise, and experience of the whole community in information security, cryptography, hardware implementations and VLSI design. 

The topics of interests for this Special Issue include, but are not limited to, the following:

  • Side-channel attacks and defenses
  • Fault attacks and countermeasures
  • Hardware tampering and tamper-resistance
  • Hardware Trojans and Backdoors
  • Reverse engineering and countermeasures
  • Anti-overbuilding, anti-counterfeiting schemes
  • Security in reconfigurable hardware
  • Hardware-based security primitives (PUFs, RNGs)
  • Emerging hardware authentication primitives
  • Area efficient and low power implementation of cryptographic primitives
  • Lightweight ciphers for IoT and wearables
  • Secure on chip memories
  • Automatic identification of security-critical parts
  • Relationship between security and testability
  • Security-aware architectures and system-level optimization

Dr. Osnat Keren
Prof. Dr. Ilia Polian
Dr. Sanu Mathew
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 350 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Published Papers (4 papers)

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Open AccessArticle A Novel Design Flow for a Security-Driven Synthesis of Side-Channel Hardened Cryptographic Modules
by 1,2,* and 2,3
1 Integrated Circuits and Systems Lab, Technische Universität Darmstadt, 64289 Darmstadt, Germany
2 The Center for Advanced Security Research Darmstadt (CASED), 64293 Darmstadt, Germany
3 Fakultät für Informatik und Mathematik, Ostbayerische Technische Hochschule Regensburg, 93053 Regensburg, Germany
J. Low Power Electron. Appl. 2017, 7(1), 4; https://doi.org/10.3390/jlpea7010004
Received: 14 May 2016 / Revised: 13 January 2017 / Accepted: 26 January 2017 / Published: 8 February 2017
Abstract | Cited by 1PDF Full-text (626 KB) | HTML Full-textXML Full-text
Abstract: Over the last few decades, computer-aided engineering (CAE) tools have been developed and improved in order to ensure a short time-to-market in the chip design business. Up to now, these design tools do not yet support an integrated design strategy for the development of side-channel-resistant hardware implementations. In order to close this gap, a novel framework named AMASIVE (Adaptable Modular Autonomous SIde-Channel Vulnerability Evaluator) was developed. It supports the designer in implementing devices hardened against power attacks by exploiting novel security-driven synthesis methods. The article at hand can be seen as the second of the two contributions that address the AMASIVE framework. While the first one describes how the framework automatically detects vulnerabilities against power attacks, the second one explains how a design can be hardened in an automatic way by means of appropriate countermeasures, which are tailored to the identified weaknesses. In addition to the theoretical introduction of the fundamental concepts, we demonstrate an application to the hardening of a complete hardware implementation of the block cipher PRESENT.
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Open AccessArticle Completing the Complete ECC Formulae with Countermeasures
1 Riscure BV, 2628 XJ Delft, The Netherlands
2 Institute for Computing and Information Sciences (ICIS), Radboud University, 6525 HP Nijmegen, The Netherlands
3 KU Leuven-imec-COSIC, KU Leuven, 3000 Leuven, Belgium
J. Low Power Electron. Appl. 2017, 7(1), 3; https://doi.org/10.3390/jlpea7010003
Received: 30 October 2016 / Accepted: 22 January 2017 / Published: 1 February 2017
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Abstract: This work implements and evaluates the recent complete addition formulae for the prime order elliptic curves of Renes, Costello and Batina on an FPGA platform. We implement three different versions:(1) an unprotected architecture; (2) an architecture protected through coordinate randomization; and (3) an architecture with both coordinate randomization and scalar splitting in place. The evaluation is done through timing analysis and test vector leakage assessment (TVLA). The results show that applying an increasing level of countermeasures leads to an increasing resistance against side-channel attacks. This is the first work looking into side-channel security issues of hardware implementations of the complete formulae.
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Open AccessArticle On Improving Reliability of SRAM-Based Physically Unclonable Functions
Department of Electrical and Computer Engineering, University of Massachusetts Amherst, Amherst, MA 01003, USA
J. Low Power Electron. Appl. 2017, 7(1), 2; https://doi.org/10.3390/jlpea7010002
Received: 5 July 2016 / Revised: 2 December 2016 / Accepted: 5 January 2017 / Published: 12 January 2017
Abstract | Cited by 1PDF Full-text (3063 KB) | HTML Full-textXML Full-text
Abstract: Physically unclonable functions (PUFs) have been touted for their inherent resistance to invasive attacks and low cost in providing a hardware root of trust for various security applications. SRAM PUFs in particular are popular in industry for key/ID generation. Due to intrinsic process variations, SRAM cells, ideally, tend to have the same start-up behavior. SRAM PUFs exploit this start-up behavior. Unfortunately, not all SRAM cells exhibit reliable start-up behavior due to noise susceptibility. Hence, design enhancements are needed for improving reliability. Some of the proposed enhancements in literature include fuzzy extraction, error-correcting codes and voting mechanisms. All enhancements involve a trade-off between area/power/performance overhead and PUF reliability. This paper presents a design enhancement technique for reliability that improves upon previous solutions. We present simulation results to quantify improvement in SRAM PUF reliability and efficiency. The proposed technique is shown to generate a 128-bit key in ≤0.2 μ s at an area estimate of 4538 μ m 2 with error rate as low as 10 6 for intrinsic error probability of 15%.
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Open AccessFeature PaperArticle Sizing of SRAM Cell with Voltage Biasing Techniques for Reliability Enhancement of Memory and PUF Functions
School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore
J. Low Power Electron. Appl. 2016, 6(3), 16; https://doi.org/10.3390/jlpea6030016
Received: 11 July 2016 / Revised: 18 August 2016 / Accepted: 18 August 2016 / Published: 24 August 2016
Abstract | Cited by 4PDF Full-text (1635 KB) | HTML Full-textXML Full-text
Abstract: Static Random Access Memory (SRAM) has recently been developed into a physical unclonable function (PUF) for generating chip-unique signatures for hardware cryptography. The most compelling issue in designing a good SRAM-based PUF (SPUF) is that while maximizing the mismatches between the transistors in the cross-coupled inverters improves the quality of the SPUF, this ironically also gives rise to increased memory read/write failures. For this reason, the memory cells of existing SPUFs cannot be reused as storage elements, which increases the overheads of cryptographic system where long signatures and high-density storage are both required. This paper presents a novel design methodology for dual-mode SRAM cell optimization. The design conflicts are resolved by using word-line voltage modulation, dynamic voltage scaling, negative bit-line and adaptive body bias techniques to compensate for reliability degradation due to transistor downsizing. The augmented circuit-level techniques expand the design space to achieve a good solution to fulfill several otherwise contradicting key design qualities for both modes of operation, as evinced by our statistical analysis and simulation results based on complementary metal–oxide–semiconductor (CMOS) 45 nm bulk Predictive Technology Model.
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