Hardware Security – Threats and Countermeasures at the Circuit and Logic Levels
A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).
Deadline for manuscript submissions: closed (31 July 2016) | Viewed by 38541
Special Issue Editors
Interests: reliable and secure circuits; security oriented codes
Interests: design and analysis of complex micro and nano-electronic circuits and systems
Interests: security circuits and cryptographic hardware accelerators
Special Issue Information
Dear Colleagues,
Nowadays, we witness the transition of our society into its new, post-industrial state, characterized by a variety of electronic devices, non-limited access to various information resources, and intensive use of information technologies. Consequently, knowledge and information security have become a major concern. Along the security chain, hardware security is considered as the weakest link; the hardware leaks information, which can be used by an invasive or passive attacker to deduce details of the algorithms and cryptographic keys. The scope of this Special Issue is on all views of circuit and logic level hardware security. This Special Issue intends to present state-of-the-art research works on area and power efficient and high performance implementations of cryptography systems, side channel threats on them, and circuit level and logic level countermeasures.
We encourage scientists and engineers, either in academic or industrial environments, to submit their original papers in order to enhance the knowledge, expertise, and experience of the whole community in information security, cryptography, hardware implementations and VLSI design.
The topics of interests for this Special Issue include, but are not limited to, the following:
- Side-channel attacks and defenses
- Fault attacks and countermeasures
- Hardware tampering and tamper-resistance
- Hardware Trojans and Backdoors
- Reverse engineering and countermeasures
- Anti-overbuilding, anti-counterfeiting schemes
- Security in reconfigurable hardware
- Hardware-based security primitives (PUFs, RNGs)
- Emerging hardware authentication primitives
- Area efficient and low power implementation of cryptographic primitives
- Lightweight ciphers for IoT and wearables
- Secure on chip memories
- Automatic identification of security-critical parts
- Relationship between security and testability
- Security-aware architectures and system-level optimization
Dr. Osnat Keren
Prof. Dr. Ilia Polian
Dr. Sanu Mathew
Guest Editors
Manuscript Submission Information
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