Special Issue "Hardware Security – Threats and Countermeasures at the Circuit and Logic Levels"
A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).
Deadline for manuscript submissions: closed (31 July 2016)
Dr. Sanu Mathew
Circuit Research Laboratory, Intel Corporation, Hillsboro, OR, USA
Interests: security circuits and cryptographic hardware accelerators
Nowadays, we witness the transition of our society into its new, post-industrial state, characterized by a variety of electronic devices, non-limited access to various information resources, and intensive use of information technologies. Consequently, knowledge and information security have become a major concern. Along the security chain, hardware security is considered as the weakest link; the hardware leaks information, which can be used by an invasive or passive attacker to deduce details of the algorithms and cryptographic keys. The scope of this Special Issue is on all views of circuit and logic level hardware security. This Special Issue intends to present state-of-the-art research works on area and power efficient and high performance implementations of cryptography systems, side channel threats on them, and circuit level and logic level countermeasures.
We encourage scientists and engineers, either in academic or industrial environments, to submit their original papers in order to enhance the knowledge, expertise, and experience of the whole community in information security, cryptography, hardware implementations and VLSI design.
The topics of interests for this Special Issue include, but are not limited to, the following:
- Side-channel attacks and defenses
- Fault attacks and countermeasures
- Hardware tampering and tamper-resistance
- Hardware Trojans and Backdoors
- Reverse engineering and countermeasures
- Anti-overbuilding, anti-counterfeiting schemes
- Security in reconfigurable hardware
- Hardware-based security primitives (PUFs, RNGs)
- Emerging hardware authentication primitives
- Area efficient and low power implementation of cryptographic primitives
- Lightweight ciphers for IoT and wearables
- Secure on chip memories
- Automatic identification of security-critical parts
- Relationship between security and testability
- Security-aware architectures and system-level optimization
Dr. Osnat Keren
Prof. Dr. Ilia Polian
Dr. Sanu Mathew
Manuscript Submission Information
Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.
Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.
Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 350 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.