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Recent Advances in Field-Programmable Gate Arrays (FPGAs)

A special issue of Applied Sciences (ISSN 2076-3417).

Deadline for manuscript submissions: 20 October 2025 | Viewed by 60

Special Issue Editor


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Guest Editor
Department of Digital Systems, Silesian University of Technology, ul. Akademicka 2A, 44-100 Gliwice, Poland
Interests: logic synthesis; decomposition; technology mapping; cyber-physical systems; FPGA; CPLD
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Special Issue Information

Dear Colleagues,

The increasing complexity of digital systems leads to new challenges for scientists dealing with broadly understood digital technology. It is becoming necessary to propose new methods of logic synthesis or effective verification methods. Design aimed at reducing power consumption, maximizing the speed of operation, limiting the number of resources, or increasing reliability is also particularly important. Another current issue is the use of AI in this process.

A special group is FPGA (field-programmable gate array) systems; their use in the areas of PLC controllers, electric drive control, cyber–physical systems, or space applications has been particularly important in recent years. Articles presenting various applications, uses, or implementations of FPGAs also belong to the thematic area of ​​this Special Issue. Contributions showing the broadly understood SoC (system-on-chip), including the use of microprocessors or IP cores, are also welcome.

Naturally, all works related to logic synthesis are always particularly appreciated, as are works related to fuzzy logic.

In creating this Special Issue, I would like to touch upon the subject of the development of digital systems.If any topic has not been mentioned above and is related to broadly understood digital systems (microprocessors, IoT, etc.), then it naturally fits into the scope of this collection.

Authors can propose their own topics related to the development of digital systems.

Dr. Marcin Kubica
Guest Editor

Manuscript Submission Information

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Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • FPGA
  • logic synthesis
  • PLC controllers
  • low power
  • cyber–physical systems

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Published Papers (1 paper)

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Research

22 pages, 586 KiB  
Article
Error Mitigation Methods for FSM Using Triple Modular Redundancy
by Marcin Kubica and Robert Czerwinski
Appl. Sci. 2025, 15(12), 6726; https://doi.org/10.3390/app15126726 - 16 Jun 2025
Abstract
In many areas of operation, application-specific logic implemented in FPGAs (Field Programmable Gate Arrays) is critical. In these situations, various mitigation methods are used to reduce or completely eliminate malfunctions in the circuit resulting from undesired physical phenomena (e.g., ionizing radiation). Such phenomena [...] Read more.
In many areas of operation, application-specific logic implemented in FPGAs (Field Programmable Gate Arrays) is critical. In these situations, various mitigation methods are used to reduce or completely eliminate malfunctions in the circuit resulting from undesired physical phenomena (e.g., ionizing radiation). Such phenomena may occur, among others, in medicine, the military, nuclear power, and space systems. One of the most popular methods is the use of triple modular redundancy (TMR). Here, the FPGA provides a good basis for building TMR-based safety-critical systems due to its concurrent processing. This paper presents an overview of the implementation of logic structures using TMR. In this paper, the authors focus on different concepts for the implementation of FSMs. The different concepts differ in the way TMR voters are attached and the extent of redundancy of the individual FSM components. The article compares the efficiency of the different solutions. In order to evaluate this efficiency, it is crucial to determine the logic utilization or the power consumption of a given implementation. In the experimental part of the article, the authors show the results of the synthesis of FSM benchmarks, for different mitigation models. The synthesis was carried out for both commercial and academic tools. Full article
(This article belongs to the Special Issue Recent Advances in Field-Programmable Gate Arrays (FPGAs))
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