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Current Updates of Programmable Logic Devices and Synthesis Methods

A special issue of Applied Sciences (ISSN 2076-3417). This special issue belongs to the section "Electrical, Electronics and Communications Engineering".

Deadline for manuscript submissions: closed (20 March 2025) | Viewed by 5770

Special Issue Editors


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Guest Editor
Department of Graphics, Computer Vision and Digital Systems, Silesian University of Technology, ul. Akademicka 16, 44-100 Gliwice, Poland
Interests: programmable digital devices; microprocessors; logic synthesis; technology mapping

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Guest Editor
Department of Digital Systems, Silesian University of Technology, Akademicka 16, 44-100 Gliwice, Poland
Interests: programmable devices and systems; logic synthesis; technology mapping; optimization of digital circuits; low-power devices; binary decision diagram; high-level synthesis; finite state machines; programmable logic controller; microprocessor systems; embedded systems; music data mining; computer posturography in the postural control diagnostics and motor functions rehabilitation
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Special Issue Information

Dear Colleagues,

In recent years, we have witnessed the increasingly prominent role of programmable logic devices, especially FPGA and SoC. Various PLD applications can be found in almost all areas of human life, such as manufacturing systems, smart grids, robotics, transportation systems, medical devices, military, home area networks, digital data analysis, smart buildings and IoT, etc.

This Special Issue aims to discuss recent advances in the design, architecture, synthesis, modeling, specification, analysis, and verification of programmable logic devices. Such aspects involve many fields of science; thus, a wide range of topics is covered (but not limited to): 

  • The logic synthesis and implementation methods of programmable logic devices (FPGA, CPLD, SoC);
  • Design methodologies, analysis techniques, and verification methods of PLDs and digital systems;
  • Optimization techniques (e.g., power, area, delay);
  • Concurrency modeling and analysis of digital systems;
  • Verification and validation techniques, including formal verification methods;
  • Performance evaluation;
  • Real-time systems, including real-time sensing and computing;
  • Internet of Things, including aspects of design, organization, and implementation;
  • Hardware implementation of intelligent algorithms;
  • Reconfigurable control systems (including distributed and integrated systems);
  • Dependable systems (cryptology, security algorithms, security aspects).

Dr. Adam Opara
Prof. Dr. Dariusz Kania
Guest Editors

Manuscript Submission Information

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Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • architecture of FPGA
  • CPLD
  • SoC
  • logic function decomposition
  • technology mapping
  • design methodologies
  • hardware implemented algorithms

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Published Papers (4 papers)

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Research

21 pages, 7696 KiB  
Article
Frequency-Modulated Antipodal Chaos Shift Keying Chaotic Communication on Field Program Gate Array: Prototype Design and Performance Insights
by Filips Capligns, Ruslans Babajans, Darja Cirjulina, Deniss Kolosovs and Anna Litvinenko
Appl. Sci. 2025, 15(3), 1156; https://doi.org/10.3390/app15031156 - 23 Jan 2025
Cited by 1 | Viewed by 748
Abstract
Using chaos for communication can provide more robust channel security, covert transmission, and inherent support for spread-spectrum modulation. Although numerous studies have explored this technology, its practical deployment remains limited due to substantial hardware demands, complex signal processing, and a lack of efficient [...] Read more.
Using chaos for communication can provide more robust channel security, covert transmission, and inherent support for spread-spectrum modulation. Although numerous studies have explored this technology, its practical deployment remains limited due to substantial hardware demands, complex signal processing, and a lack of efficient modulation methods for chaotic signals. In this study, a novel chaotic digital communication system is proposed and studied. A prototype of a frequency-modulated antipodal chaos shift keying (FM-ACSK) system is implemented on an Intel Cyclone V field-programmable gate array (FPGA) along with a complete mathematical model using Matlab R2022a Simulink software. Using FPGAs to implement chaotic oscillators avoids analog system problems such as component drift and high thermal instability while providing determined system parameters, rapid prototyping, and high throughput. The employment of FM over a chaotic modulation layer provides a passband operation (currently at an intermediate frequency of 10.7 MHz) while adding the benefits of carrier frequency offset robustness and constant signal envelope. Within this study, the robustness of FM-ACSK to white noise in the channel was evaluated using bit error rate, which was tested through hardware experiments and simulations. The results show the feasibility and potential performance limitations of this approach to chaotic communication system design. Full article
(This article belongs to the Special Issue Current Updates of Programmable Logic Devices and Synthesis Methods)
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13 pages, 2678 KiB  
Article
An FPGA-Based Data Acquisition System with Embedded Processing for Real-Time Gas Sensing Applications
by Godwin Enemali and Ryan M. Gibson
Appl. Sci. 2024, 14(15), 6738; https://doi.org/10.3390/app14156738 - 1 Aug 2024
Viewed by 1635
Abstract
Real-time gas sensing based on wavelength modulation spectroscopy (WMS) has been widely adopted for several gas sensing applications. It is attractive for its accurate, non-invasive, and fast determination of critical gas parameters such as concentration, temperature, and pressure. To implement real-time gas sensing, [...] Read more.
Real-time gas sensing based on wavelength modulation spectroscopy (WMS) has been widely adopted for several gas sensing applications. It is attractive for its accurate, non-invasive, and fast determination of critical gas parameters such as concentration, temperature, and pressure. To implement real-time gas sensing, data acquisition and processing must be implemented to accurately extract harmonics of interest from transmitted laser signals. In this work, we present an FPGA-based data acquisition architecture with embedded processing capable of achieving both real-time and accurate gas detection. By leveraging real-time processing on-chip, we minimised the data transfer bandwidth requirement, hence enabling better resolution of data transferred for high-level processing. The proposed architecture has a significantly lower bandwidth requirement compared to both the conventional offline processing architecture and the standard I-Q architecture. Specifically, it is capable of reducing data transfer overhead by 25% compared to the standard I-Q method, and it only requires a fraction of the bandwidth needed by the offline processing architecture. The feasibility of the proposed architecture is demonstrated on a commercial off-the-shelf SoC board, where measurement results show that the proposed architecture has better accuracy compared to the standard I-Q demodulation architecture for the same signal bandwidth. The proposed DAQ system has potential for more accurate and fast real-time gas sensing. Full article
(This article belongs to the Special Issue Current Updates of Programmable Logic Devices and Synthesis Methods)
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19 pages, 1679 KiB  
Article
Optimized Sequential State Encoding Methods for Finite-State Machines in Field-Programmable Gate Array Implementations
by Valery Salauyou and Witali Bułatow
Appl. Sci. 2024, 14(13), 5594; https://doi.org/10.3390/app14135594 - 27 Jun 2024
Cited by 5 | Viewed by 1163
Abstract
A Finite-State Machine (FSM) model is frequently employed to represent the behavior of sequential circuits. In the optimal design of these circuits, it is crucial to enhance FSM characteristics such as area (implementation cost), performance (operating frequency), and power consumption. This paper proposes [...] Read more.
A Finite-State Machine (FSM) model is frequently employed to represent the behavior of sequential circuits. In the optimal design of these circuits, it is crucial to enhance FSM characteristics such as area (implementation cost), performance (operating frequency), and power consumption. This paper proposes sequential state encoding methods that aim to reduce the area and enhance the performance of FSMs. The methods involve sequentially selecting FSM states for encoding and determining the most appropriate code for each selected state. Several state and code selection modes are introduced, allowing for consideration of the relationships between states, the number of incoming and outgoing transitions, and the number of input variables initiating transitions to each state. The code selection process takes into account the architectural features of the electronic device in which the FSM is implemented, while some code selection modes are introduced to optimize both the area and performance of the FSM. The experimental results demonstrate that the proposed approach yields, on average, a reduction in the FSM area by 19.7% (in some instances, up to twofold reduction), along with an average performance increase of 21.2% (in certain cases, up to 69.3%), compared to the Sequential mode of the Quartus system. Full article
(This article belongs to the Special Issue Current Updates of Programmable Logic Devices and Synthesis Methods)
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37 pages, 10947 KiB  
Article
Design and Optimization of a Petri Net-Based Concurrent Control System toward a Reduction in the Resources in a Field-Programmable Gate Array
by Remigiusz Wiśniewski, Adam Opara and Marcin Wojnakowski
Appl. Sci. 2024, 14(12), 5212; https://doi.org/10.3390/app14125212 - 15 Jun 2024
Cited by 1 | Viewed by 1306
Abstract
A novel design technique of a Petri net-based concurrent control system is proposed in this paper. The idea is oriented on the effective implementation of the system within the FPGA device. In order to reduce the resources of the targeted device, the concurrent [...] Read more.
A novel design technique of a Petri net-based concurrent control system is proposed in this paper. The idea is oriented on the effective implementation of the system within the FPGA device. In order to reduce the resources of the targeted device, the concurrent control system is optimized by the use of the authors’ techniques. The complete design flow is shown, including the modeling of the system by an interpreted Petri net, its further transformation to the hardware description language, adequate logic optimization, and final implementation within the destination FPGA. The presented method is explained by a case study example of the photovoltaic control system and compared with the already known technique. The performed experiments indicated a very high effectiveness of the proposed technique. It is shown that the photovoltaic control system designed according to the presented method reduces the logic resources of the destination FPGA device by up to 28%. Full article
(This article belongs to the Special Issue Current Updates of Programmable Logic Devices and Synthesis Methods)
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