Receiving-End Voltage Compensation Method with NPC-Inverter-Based Active Power Line Conditioner in Three-Phase Four-Wire Distribution Feeder

Abstract

This study proposes a receiving-end voltage compensation method employing a phase-specific reactive power control strategy with a neutral-point-clamped (NPC) inverter in a three-phase four-wire distribution system. The principle of the proposed receiving end voltage compensation method is explained. Further, the proposed control strategy can solve the problems of the three-phase, four-wire distribution system, which are an increase in the neutral-line current and the unbalanced voltage. Computer simulation is performed to confirm the validity of the proposed method. The simulation results indicate the receiving-end voltages can be compensated using the proposed method.

1. Introduction

Low-voltage distribution systems differ among countries [1]. Both three- and single-phase three-wire low-voltage distribution feeders are used for consumer electronics and industrial loads in the United States, Canada, Taiwan, and Japan. In this case, both the single- and three-phase transformers are connected to a three-phase three-wire high-voltage distribution feeder. Certain Asian and European countries use three-phase four-wire distribution feeders (3P4WDFs). Figure 1 shows an example of a 3P4WDF, where both single- and three-phase loads are directly connected to the 3P4WDF.

Figure 1. Example of a 3P4WDF.

Today, consumer electronics often use diode rectifiers to transform AC into DC. When these single-phase loads are connected to a 3P4WDF, they lead to imbalanced and distorted currents in the feeders [2]. This imbalance and a distortion subsequently increase and distort the current in the neutral line. In particular, the efficiency of the distribution transformer is reduced by an increased and/or distorted neutral current. Therefore, the secondary-side voltages of the $\Delta$-Y-connected transformer $V_{\mathrm{La}}$, $V_{\mathrm{Lb}}$ and $V_{\mathrm{Lc}}$ are also unbalanced.

The per-phase base equivalent circuit for the $\Delta$-Y-connected transformer, which is illustrated in Figure 1, is explained. Let $V_{\mathrm{Hp}}$ and $V_{\mathrm{Lp}}$ be the primary- and secondary-sides phase voltage, $X_{\mathrm{T}}$ be the per-phase based equivalent impedance of $\Delta$-Y-connected transformer, and a be the turns ratio of the transformer. $V_{\mathrm{Lp}}$ is regulated by reactive power $Q_{\mathrm{p}}$ in each phase. Typically, the difference between $V_{\mathrm{Hp}}/a$ and $V_{\mathrm{Lp}}$ is expressed as

$$\begin{array}{c}\hfill Q_{\mathrm{p}}={\displaystyle \frac{V_{\mathrm{Lp}}}{X_{\mathrm{T}}}}\left\{\left({\displaystyle \frac{V_{\mathrm{Hp}}}{a}}\right)-V_{\mathrm{Lp}}\right\}.\end{array}$$

(1)

According to (1), $V_{\mathrm{Lp}}$ is proportional to $Q_{\mathrm{p}}$. Hence, it is evident that controlling the reactive power in each phase is essential for balancing the secondary-side voltages $V_{\mathrm{Lpa}}$, $V_{\mathrm{Lpb}}$, and $V_{\mathrm{Lpc}}$.

Power quality compensation devices include static synchronous compensators (STATCOM) [3,4,5,6,7,8,9] and doubly fed induction generators (DFIG) [10,11], active power line conditioners (APLCs), etc. STATCOM is excellent at reactive power compensation and is the most effective solution [12]. In this paper, we consider an APLC, which is capable of providing comprehensive compensation through current control using a self-excited switch with power semiconductors.

To solve the problems of increased neutral-line current and unbalanced receiving-end voltages in 3P4WDF, an APLC has been proposed [13,14,15,16,17,18,19]. APLCs are active filters comprising a four-leg inverter and a DC capacitor. It can compensate for the unbalanced load currents by injecting compensation currents. However, the DC-capacitor voltage must exceed the feeder voltage. Thus, a high-withstand-voltage switching device and capacitor are required for APLCs.

Numerous papers have been published on the control strategies for APLCs based on the instantaneous active–reactive power theory [20,21,22]. In instantaneous active–reactive power theory, the active, reactive, and harmonic components are calculated on the $dq$ coordinates. Recent studies have proposed new power conditioners for 3P4WDFs [23,24,25]. These studies used an instantaneous active–reactive power theory-based control algorithm with $dq$ transforms to obtain balanced and sinusoidal source-side currents $i_{\mathrm{Sa}}$, $i_{\mathrm{Sb}}$, and $i_{\mathrm{Sc}}$ while suppressing the neutral-line current. In a separate study, a new control algorithm was proposed for single-phase shunt active filters in 3P4WDFs [26]. This algorithm includes a constant DC-capacitor voltage control block in addition to the calculation block of the fundamental active–reactive currents. However, both these studies were limited to linear loads.

Three-phase four-wire distribution systems offer the advantage of concurrently accommodating both single- and three-phase loads. However, they present certain challenges, including increased neutral-line current and unbalanced receiving-end voltages. To address these issues, various control strategies for three-phase inverters have been extensively studied [27,28,29,30,31,32,33,34,35]. Specifically, studies have focused on control methodologies tailored for three-phase four-wire systems [27,28,29,30,31,32,33,34]. Certain proposed methods include the integration of uninterruptible power supply (UPS) and pulse width modulation (PWM) rectifier technologies into three-phase four-wire setups to enhance the control applications. Three-phase inverters have been utilized as compensators for power-quality compensation [27,28,29,30,31]. Although efforts have been made to control the phase-specific power at the source side, compensation for unbalanced receiving-end voltages remains unverified owing to the absence of significant voltage imbalances. Thus, this is merely a confirmation of the principle. Furthermore, the implementation of phase-specific unbalanced currents without suppressing the neutral-line current inadvertently increases the neutral-line current [27]. Techniques employing the thyristor switched capacitors (TSCs), passive filters, and distributed static synchronous compensator (D-STATCOM) aim to mitigate neutral-line currents, reduce voltage flickers, and select harmonics on the 3rd, 5th, and 7th [28]. However, these solutions often involve complex circuit configurations and are not universally effective in all harmonic compensation. In [29], switching from the grid-connected to islanded mode and from the islanded to grid-connected mode through active power compensation was explored. However, it did not adequately address the core challenges of neutral-line currents and unbalanced receiving-end voltages in three-phase four-wire systems.

APLCs in 3P4WDF using new control strategies have been reported [20,23,24,25]. In [20,23,24,25], balancing the source currents in a three-phase four-wire distribution system suppressed the neutral-line current. However, there exists a large neutral-line current under an asymmetrical grid fault [20]. In addition, although research has been carried out on stable operation under unbalanced load conditions and during system faults, there are no reports to date on research into the control of unbalanced voltages in a balanced manner [5,6]. To the best of our knowledge, a method for suppressing the neutral-line currents under unbalanced source current conditions has not yet been reported.

In most cases, there have been no reports on the compensation of unbalanced voltages, which is a major issue for 3P4WDF. According to IEC 60038, the highest voltage must not differ by more than +5% and the lowest voltage by more than –10% from the nominal voltage of the system [36]. Therefore, this study proposes a compensation method for the unbalanced receiving-end voltage deviating from the standards set by IEC while suppressing the total harmonic currents and neutral-line current using a phase-specific reactive power control strategy, as shown in Table 1.

Table 1. Comparison with previous research on control methods.

Method	Advantages	Disadvantages
Overcurrent and restraining method [20]	Suppression of overcurrent Power oscillation suppression under asymmetric grid fault	Increase neutral-line current Not all harmonics compensation Uncompensated unbalanced voltage
Hybrid power conditioner [23,26]	Neutral-line current suppression All harmonics compensation	Not-individual-phase current control Uncompensated unbalanced voltage
Per-phase control strategy [27]	Individulal-phase reactive current control	Increase in neutral-line current Uncompensated unbalanced voltage
Hybrid compensator [28]	Neutral-line current suppression Reduce voltage flickers The 3rd, 5th, and 7th harmonics compensation	Complex circuit configurations Not all harmonics compensation Uncompensated unbalanced voltage
Control of 3 H-bridge inverter [29]	Switching between island mode and grid-connected mode Unbalanced power supply	Increase in neutral-line current Uncompensated unbalanced voltage
Active power control for D-STATCOM [30]	Neutral-line current suppression All harmonics compensation	Not-individual-phase current control Uncompensated unbalanced voltage
Active power filter with 3 H-bridge inverter [31]	All harmonics compensation Unbalanced currents compensation Neutral-line current suppression Reduction in inverter-rated voltage	Not-individual-phase current control Uncompensated unbalanced voltage
Receiving-end voltage compensation method with NPC inverter (this paper)	Individual-phase reactive current control Neutral-line current suppression All harmonics compensation Unbalanced receiving-end voltages compensation	Increase number of power devices

This study proposes a receiving-end voltage compensation method using an NPC-inverter-based APLC in a 3P4WDF. The withstand voltage of the switching devices and capacitors can be reduced compared with the four-leg inverter-based APLC [18,19]. The proposed control strategy aims to compensate for unbalanced voltages at the receiving end while minimizing the current in the neutral line. The shortage of the reactive current component at the receiving end is calculated, and the active power is redistributed to the source side. The former compensates for the unbalanced receiving-end voltages, and the latter provides balanced three-phase source currents. Computer simulations are conducted to verify the effectiveness and feasibility of the proposed control strategy. The simulation results indicate that the strategy successfully compensates for the source currents and receiving-end voltages in each phase, while reducing the neutral-line current.

2. Three-Phase Four-Wire Distribution Systems Under Unbalanced Single-Phase Loads

Figure 2 shows the power circuit diagram of 3P4WDF without an APLC. A $\Delta$-Y-connected transformer is used for low-voltage 3P4WDF. Single-phase linear and nonlinear loads are connected in 3P4WDF. The nonlinear load consists of a diode rectifier with capacitor input filter and resistor in this paper. Computer simulation is implemented using the PSIM circuit simulation software package to confirm the technical issues in 3P4WDF. In a 3P4WDF system, the root mean square (RMS) value of the line-to-line voltage is typically 380 or 400 Vrms. However, in Japan, the RMS value of the line-to-line voltage in a three-phase, three-wire, low-voltage distribution feeder is typically 200 Vrms. However, in this study, the following two points are considered. First, inductors $L_{\mathrm{Sa}}$, $L_{\mathrm{Sb}}$, and $L_{\mathrm{Sc}}$ with 20% of the rated inductance are added to the primary-side feeders. The phase voltages on the primary side are unbalanced and set to 120 Vrms, 115 Vrms, and 110 Vrms. The above settings are used to simulate the voltage unbalanced condition. This simulates the voltage drops and unbalanced conditions caused by long-distance high-voltage distribution feeders. The capacity of a transformer is 6.0 kVA. The rated load current of secondary-side of this transformer is 17.4 Arms per phase. Table 2 lists the circuit constants as shown in Figure 2. Table 2 shows the numerical values for the reduced model used in the experiment, which simulates the power distribution system in South Korea. It is necessary to evaluate at around the rated capacity for verification of compensation effects. In addition, according to reference [37], for capacities of 100 kVA or less, the equipment imbalance ratio is specified as 30% or less. Therefore, in this study, when the phase a load is 1.0 pu, the phase b and c loads are designed to be 0.8 pu and 0.75 pu, respectively, so that the equipment imbalance ratio is within 30%.

Figure 2. Power circuit diagram of a 3P4WDF without an APLC.

Table 2. Circuit constants of linear and nonlinear loads for Figure 2.

Item	Symbol	Value
a-phase load (1.0 pu, power factor 0.82)	$R_{\mathrm{a}}$	17 $\Omega$
	$L_{\mathrm{a}}$	35 mH
	$R_{\mathrm{ha}}$	70 $\Omega$
	$L_{\mathrm{ha}}$	2.7 mH
	$C_{\mathrm{ha}}$	1500 µF
b-phase load (0.8 pu, power factor 0.84)	$R_{\mathrm{b}}$	12 $\Omega$
	$L_{\mathrm{b}}$	25 mH
	$R_{\mathrm{hb}}$	35 $\Omega$
	$L_{\mathrm{hb}}$	2.7 mH
	$C_{\mathrm{hb}}$	1500 µF
c-phase load (0.75 pu, power factor 0.82)	$R_{\mathrm{c}}$	14 $\Omega$
	$L_{\mathrm{c}}$	28 mH
	$R_{\mathrm{hc}}$	40 $\Omega$
	$L_{\mathrm{hc}}$	2.7 mH
	$C_{\mathrm{hc}}$	1500 µ F

Figure 3 presents the simulation results without the proposed phase-specific reactive power control strategy. Here, $v_{\mathrm{Ta}}$, $v_{\mathrm{Tb}}$, and $v_{\mathrm{Tc}}$ are the receiving-end voltage waveforms, $i_{\mathrm{Sa}}$, $i_{\mathrm{Sb}}$, $i_{\mathrm{Sc}}$, and $i_{\mathrm{Sn}}$ are the secondary-side source current waveforms. $i_{\mathrm{La}}$, $i_{\mathrm{Lb}}$, $i_{\mathrm{Lc}}$, and $i_{\mathrm{Ln}}$ are the load current waveforms flowing into the domestic consumers. The NPC inverter and LC filter are removed from the power circuit shown in Figure 4 and do not act as compensators.

Figure 3. Simulation results for Figure 2.

Figure 4. Power circuit diagram of the proposed NPC-inverter-based APLC.

Therefore, the waveforms of the source and load sides are identical. The total harmonic distortion (THD) values of the source currents $i_{\mathrm{Sa}}$, $i_{\mathrm{Sb}}$, and $i_{\mathrm{Sc}}$ and the load curves $i_{\mathrm{La}}$, $i_{\mathrm{Lb}}$, and $i_{\mathrm{Lc}}$ matched perfectly (Table 3); both are unbalanced and heavily distorted. Here, the neutral-line current $i_{\mathrm{Sn}}$ is not suppressed. Thus, on the source side, the RMS value of the a-phase current $I_{\mathrm{Sa}}$ is 15.0 Arms, $I_{\mathrm{Sb}}$ is 11.9 Arms, and $I_{\mathrm{Sc}}$ is 11.0 Arms. Further, the neutral-line current $I_{\mathrm{Sn}}$ is 10.5 Arms, which corresponds to 60% of the rated load current. The measured displacement power factor (DPF) values for phases a, b, and c are 0.87, 0.86, and 0.87, respectively. These values are far from a unity DPF. The RMS values of the receiving-end voltages are 108.1, 102.3, and 107.3 Vrms, exhibiting a large voltage drop. In particular, $v_{\mathrm{Tb}}$ drops 11% from the reference receiving-end voltage value of 115 Vrms, which deviates from the IEC 60038 standard.

Table 3. THD values for Figure 3.

THD	${\mathit{v}}_{\mathbf{T}}$	${\mathit{i}}_{\mathbf{S}}$
a-phase	8.05%	28.4%
b-phase	7.87%	28.0%
c-phase	7.33%	30.2%

3. Proposed Receiving-End Voltage Compensation with NPC-Inverter-Based APLC in 3P4WDF

Figure 4 shows the power circuit diagram of the proposed neutral-point-clamped (NPC) inverter-based APLC in 3P4WDF. This APLC uses the proposed receiving-end voltage compensation method. The APLC features a four-leg NPC inverter, with its fourth leg connected to a neutral line. NPC inverters, which are three-level inverters, can reduce the withstand voltage of the switching element compared with two-level inverters. In addition, since the switching noise is also reduced, the size of the LC filter can be reduced, and the switching frequency can be increased, enabling high-efficiency power conversion [38,39,40]. Our research group confirmed the basic principle of the reactive current control method by injecting arbitrary reactive current components in [18]. It was then shown that individual-phase unbalanced source currents can be achieved by injecting reactive currents for each phase separately. In this paper, a new control block is added to detect the reactive current component required for individual-phase receiving-end voltages compensation.

In Figure 4, a three-phase phase-locked loop (PLL) is used to produce the electric angle ${\theta }_{\mathrm{S}}$. ${\theta }_{\mathrm{S}}$ is synchronized with the receiving-end voltage $v_{\mathrm{Ta}}$. The receiving-end voltages $v_{\mathrm{Ta}}$, $v_{\mathrm{Tb}}$, and $v_{\mathrm{Tc}}$ are expressed as follows:

$$\begin{array}{ccc}\hfill v_{\mathrm{Ta}}& =& \sqrt{2}{V}_{\mathrm{T}}cos\omega t,\hfill \\ \hfill v_{\mathrm{Tb}}& =& \sqrt{2}{V}_{\mathrm{T}}cos\left(\omega t-{\displaystyle \frac{2}{3}}\pi \right),\hfill \\ \hfill v_{\mathrm{Tc}}& =& \sqrt{2}{V}_{\mathrm{T}}cos\left(\omega t+{\displaystyle \frac{2}{3}}\pi \right).\hfill \end{array}$$

(2)

The unbalanced and distorted load currents $i_{\mathrm{La}}$, $i_{\mathrm{Lb}}$, and $i_{\mathrm{Lc}}$ are expressed as

$$\begin{array}{ccc}{i}_{\mathrm{La}}\hfill & =& \sqrt{2}{I}_{\mathrm{La}1}cos(\omega t-{\varphi }_{\mathrm{a}1})\hfill \\ & & +\sqrt{2}\sum _{h=2}^{\infty }{I}_{\mathrm{La}h}cosh(\omega t-{\varphi }_{\mathrm{ah}}),\hfill \\ \hfill i_{\mathrm{Lb}}& =& \sqrt{2}{I}_{\mathrm{Lb}1}cos\left(\omega t-{\displaystyle \frac{2\pi }{3}}-{\varphi }_{\mathrm{b}1}\right)\hfill \\ & & +\sqrt{2}\sum _{h=2}^{\infty }{I}_{\mathrm{Lb}h}cosh\left(\omega t-{\displaystyle \frac{2\pi }{3}}-{\varphi }_{\mathrm{bh}}\right),\hfill \\ \hfill i_{\mathrm{Lc}}& =& \sqrt{2}{I}_{\mathrm{Lc}1}cos\left(\omega t+{\displaystyle \frac{2\pi }{3}}-{\varphi }_{\mathrm{c}1}\right)\hfill \\ & & +\sqrt{2}\sum _{h=2}^{\infty }{I}_{\mathrm{Lc}h}cosh\left(\omega t+{\displaystyle \frac{2\pi }{3}}-{\varphi }_{\mathrm{ch}}\right).\hfill \end{array}$$

(3)

When the source currents in the three phases are unbalanced, and it is defined that the reactive currents for each phase are $I_{\mathrm{qa}}$, $I_{\mathrm{qb}}$, and $I_{\mathrm{qc}}$, the reference source currents $i_{\mathrm{Sa}}^{*}$, $i_{\mathrm{Sb}}^{*}$, and $i_{\mathrm{Sc}}^{*}$ are expressed as

$$\begin{array}{ccc}\hfill i_{\mathrm{Sa}}^{*}& =& \sqrt{2}{I}_{\mathrm{P}}cos\omega t+\sqrt{2}{I}_{\mathrm{qa}}sin\omega t,\hfill \\ \hfill i_{\mathrm{Sb}}^{*}& =& \sqrt{2}{I}_{\mathrm{P}}cos\left(\omega t-{\displaystyle \frac{2\pi }{3}}\right)+\sqrt{2}{I}_{\mathrm{qb}}sin\left(\omega t-{\displaystyle \frac{2\pi }{3}}\right),\hfill \\ \hfill i_{\mathrm{Sc}}^{*}& =& \sqrt{2}{I}_{\mathrm{P}}cos\left(\omega t+{\displaystyle \frac{2\pi }{3}}\right)+\sqrt{2}{I}_{\mathrm{qc}}sin\left(\omega t+{\displaystyle \frac{2\pi }{3}}\right).\hfill \end{array}$$

(4)

The derivations of the reactive currents $I_{\mathrm{qa}}$, $I_{\mathrm{qb}}$, and $I_{\mathrm{qc}}$ are described below. The neutral-line current is expressed as the sum of $i_{\mathrm{Sa}}$, $i_{\mathrm{Sb}}$, and $i_{\mathrm{Sc}}$. In (4), the sum of the first terms of each equation is zero; therefore, the current through the neutral line is the sum of the second term, which are the reactive current components. Therefore, the current flowing through the neutral line $i_{\mathrm{q}}$ is expressed as

$$\begin{array}{c}\hfill i_{\mathrm{q}}=\sqrt{2}{I}_{\mathrm{qa}}sin\omega t+\sqrt{2}{I}_{\mathrm{qb}}sin\left(\omega t-{\displaystyle \frac{2\pi }{3}}\right)+\sqrt{2}{I}_{\mathrm{qc}}sin\left(\omega t+{\displaystyle \frac{2\pi }{3}}\right).\end{array}$$

(5)

This equation indicates that the neutral-line current is not zero, that is, it is not suppressed. Hence, the reactive power is used to cancel $i_{\mathrm{q}}$. Further, $i_{\mathrm{d}}$, which is a component of the neutral-line current suppression, $i_{\mathrm{d}}$, is expressed as

$$\begin{array}{c}\hfill i_{\mathrm{d}}=-i_{\mathrm{q}}=-\sqrt{2}{I}_{\mathrm{qa}}sin\omega t-\sqrt{2}{I}_{\mathrm{qb}}sin\left(\omega t-{\displaystyle \frac{2\pi }{3}}\right)-\sqrt{2}{I}_{\mathrm{qc}}sin\left(\omega t+{\displaystyle \frac{2\pi }{3}}\right).\end{array}$$

(6)

Rewriting (6) in terms of the cosine component to express the active current, we obtain

$$\begin{array}{ccc}\hfill i_{\mathrm{d}}& =& \sqrt{2}{\displaystyle \frac{2\sqrt{3}}{3}}(I_{\mathrm{qb}}-I_{\mathrm{qc}})cos\omega t,\hfill \\ & & +\sqrt{2}{\displaystyle \frac{\sqrt{3}}{3}}(I_{\mathrm{qb}}-I_{\mathrm{qa}})cos\left(\omega t-{\displaystyle \frac{2\pi }{3}}\right),\hfill \\ & & +\sqrt{2}{\displaystyle \frac{\sqrt{3}}{3}}(I_{\mathrm{qa}}-I_{\mathrm{qc}})cos\left(\omega t+{\displaystyle \frac{2\pi }{3}}\right).\hfill \end{array}$$

(7)

The active currents in (7) are added to the reference source currents in (4) for each phase. Thus, the reference source currents $i_{\mathrm{Sa}}^{*}$, $i_{\mathrm{Sb}}^{*}$, and $i_{\mathrm{Sc}}^{*}$ are expressed as

$$\begin{array}{ccc}\hfill i_{\mathrm{Sa}}^{*}& =& \sqrt{2}{I}_{\mathrm{P}}cos\omega t+\sqrt{2}{I}_{\mathrm{qa}}sin\omega t\hfill \\ & & +\sqrt{2}{\displaystyle \frac{2\sqrt{3}}{3}}(I_{\mathrm{qb}}-I_{\mathrm{qc}})I_{\mathrm{P}}cos\omega t,\hfill \\ \hfill i_{\mathrm{Sb}}^{*}& =& \sqrt{2}{I}_{\mathrm{P}}cos\left(\omega t-{\displaystyle \frac{2\pi }{3}}\right)+\sqrt{2}{I}_{\mathrm{qb}}sin\left(\omega t-{\displaystyle \frac{2\pi }{3}}\right)\hfill \\ & & +\sqrt{2}{\displaystyle \frac{\sqrt{3}}{3}}(I_{\mathrm{qb}}-I_{\mathrm{qa}})I_{\mathrm{P}}cos\left(\omega t-{\displaystyle \frac{2\pi }{3}}\right),\hfill \\ \hfill i_{\mathrm{Sc}}^{*}& =& \sqrt{2}{I}_{\mathrm{P}}cos\left(\omega t+{\displaystyle \frac{2\pi }{3}}\right)+\sqrt{2}{I}_{\mathrm{qc}}sin\left(\omega t+{\displaystyle \frac{2\pi }{3}}\right)\hfill \\ & & +\sqrt{2}{\displaystyle \frac{\sqrt{3}}{3}}(I_{\mathrm{qa}}-I_{\mathrm{qc}})I_{\mathrm{P}}cos\left(\omega t+{\displaystyle \frac{2\pi }{3}}\right).\hfill \end{array}$$

(8)

In (8), the sum of the first term of each equation is zero. Further, the reactive current component $i_{\mathrm{q}}$ in the second term and the active current component $i_{\mathrm{d}}$ in the third term cancel each other out. Consequently, the neutral-line current $i_{\mathrm{Sn}}$ becomes $i_{\mathrm{Sn}}^{*}=i_{\mathrm{Sa}}^{*}+i_{\mathrm{Sb}}^{*}+i_{\mathrm{Sc}}^{*}=0$, and the current that flows through the neutral line $i_{\mathrm{Sn}}$ can be effectively reduced. Therefore, by injecting an arbitrary reactive current and determining the reference source currents $i_{\mathrm{Sa}}^{*}$, $i_{\mathrm{Sb}}^{*}$, and $i_{\mathrm{Sc}}^{*}$, the reactive power of each phase can be regulated while minimizing the neutral-line current.

Next, the extraction of reactive currents and their flows are described. The multiplication of the receiving-end voltages $v_{\mathrm{Ta}}$, $v_{\mathrm{Tb}}$, and $v_{\mathrm{Tc}}$ with the calculated $\sqrt{2}cos\omega t$, $\sqrt{2}cos\left(\omega t-{\displaystyle \frac{2\pi }{3}}\right)$, and $\sqrt{2}cos\left(\omega t+{\displaystyle \frac{2\pi }{3}}\right)$ in each respective phase yields the following

$$\begin{array}{ccc}\hfill v_{\mathrm{Ta}}·\sqrt{2}cos\omega t& =& V_{\mathrm{Ta}}(1+cos\left(2\omega t\right)),\hfill \\ \hfill v_{\mathrm{Tb}}·\sqrt{2}cos\left(\omega t-{\displaystyle \frac{2\pi }{3}}\right)& =& V_{\mathrm{Tb}}\left(1+cos2\left(\omega t-{\displaystyle \frac{2\pi }{3}}\right)\right),\hfill \\ \hfill v\mathrm{Tc}·\sqrt{2}cos\left(\omega t+{\displaystyle \frac{2\pi }{3}}\right)& =& V_{\mathrm{Tc}}\left(1+cos2\left(\omega t+{\displaystyle \frac{2\pi }{3}}\right)\right).\hfill \end{array}$$

(9)

A moving average low-pass filter (MALPF) is used to extract the AC components in (9) because the instantaneous power that flows into and out of the APLC is all even-order components, and by adopting MALPF, which uses a moving average of half a cycle as a low-pass filter, it is possible to remove the even-order component, 2$\omega$ component. The RMS values $V_{\mathrm{Ta}}$, $V_{\mathrm{Tb}}$, and $V_{\mathrm{Tc}}$ of the receiving-end voltages are expressed as follows:

$$\begin{array}{ccc}\hfill \overline{v_{\mathrm{Ta}}·\sqrt{2}cos\omega t}& =& V_{\mathrm{Ta}},\hfill \\ \hfill \overline{v_{\mathrm{Tb}}·\sqrt{2}cos\left(\omega t-{\displaystyle \frac{2\pi }{3}}\right)}& =& V_{\mathrm{Tb}},\hfill \\ \hfill \overline{v\mathrm{Tc}·\sqrt{2}cos\left(\omega t+{\displaystyle \frac{2\pi }{3}}\right)}& =& V_{\mathrm{Tc}}.\hfill \end{array}$$

(10)

Finally, the reactive currents $I_{\mathrm{qa}}$, $I_{\mathrm{qb}}$, and $I_{\mathrm{qc}}$ are calculated using feedback control with a PI controller. Substituting this reactive current into (8) enables reactive power control, that is, compensation of the terminal voltages.

PI controllers in dq0 coordinates are used to control the output currents $i_{\mathrm{C}1}$, $i_{\mathrm{C}2}$, and $i_{\mathrm{C}3}$ of the APLC. Further, the gate signals for ${\mathrm{Q}}_1$–${\mathrm{Q}}_8$ are generated by using the sine-triangle intercept technique with a two-phase modulation.

4. Simulation Results

A computer simulation is performed using the PSIM circuit simulation software package to verify the effectiveness of the proposed control method. The circuit constants in Figure 4 are listed in Table 4. In Table 4, the cut-off frequency is designed to be 5.19 kHz. The reference DC-capacitor voltage $V_{DC}^{*}$ is 400 Vdc because the line-to-line voltages on the source side are 200 Vrms. The $C_{\mathrm{DC}}$ is decided to smooth the DC voltage sufficiently. Table 5 shows the parameters of PI controllers for Figure 4. The gain of the PI controller is determined by trial and error. The method of determining the gain needs to be examined in detail in the future. The inductors $L_{\mathrm{Sa}}$, $L_{\mathrm{Sb}}$, and $L_{\mathrm{Sc}}$ with 20% of the rated inductance are added to the primary-side feeders and the phase voltages on the primary side are unbalanced and set to 120 Vrms, 115 Vrms, and 110 Vrms, as in Figure 2.

Table 4. Control constants for Figure 4.

Item	Symbol	Value
Reference DC-capacitor voltage	$V_{\mathrm{DC}}^{*}$	400 Vdc
DC-capacitor	$C_{\mathrm{p}}$, $C_{\mathrm{q}}$	3900 µF
Filter inductor	$L_{\mathrm{f}1}$	1.5 mH
	$L_{\mathrm{f}2}$	0.1 mH
Filter capacitor	$C_{\mathrm{f}}$	10 µF
Switching frequency	$f_{\mathrm{SW}}$	12 kHz

Table 5. Parameters of PI controllers for Figure 4.

Item	Symbol	Value
Proportional gain for current control	$K_{\mathrm{c}}$	0.2
Proportional gain for DC-capacitor voltage control	$K_{\mathrm{DC}}$	0.1
Proportional gain for voltage compensation	$K_{\mathrm{V}}$	0.2
Proportional gain for PLL	$K_{\mathrm{PLL}}$	1
Integral constant for current control	$T_{\mathrm{c}}$	0.1 ms
Integral constant for DC-capacitor voltage control	$T_{\mathrm{DC}}$	20 ms
Integral constant for voltage compensation	$T_{\mathrm{V}}$	0.1 ms
Integral constant for PLL	$T_{\mathrm{PLL}}$	0.1 s

4.1. Employing the Phase-Specific Reactive Power Control Strategy

The simulation results for Figure 4 obtained using the proposed phase-specific reactive power control strategy are shown in Figure 5. Here, $v_{\mathrm{Ta}}$, $v_{\mathrm{Tb}}$, and $v_{\mathrm{Tc}}$ are the receiving-end voltage waveforms, $i_{\mathrm{Sa}}$, $i_{\mathrm{Sb}}$, $i_{\mathrm{Sc}}$, and $i_{\mathrm{Sn}}$ are the source current waveforms, $i_{\mathrm{La}}$, $i_{\mathrm{Lb}}$, $i_{\mathrm{Lc}}$, and $i_{\mathrm{Ln}}$ are the load-current waveforms, $i_{\mathrm{Ca}}$, $i_{\mathrm{Cb}}$, $i_{\mathrm{Cc}}$, and $i_{\mathrm{Cn}}$ are the output current waveforms of the four-leg NPC-inverter-based APLC, and $v_{\mathrm{DC}}$ is the DC-capacitor voltage waveform. The unbalanced and heavily distorted source currents $i_{\mathrm{Sa}}$, $i_{\mathrm{Sb}}$, and $i_{\mathrm{Sc}}$ in Figure 3 are found to be balanced and sinusoidal owing to the compensation currents $i_{\mathrm{Ca}}$, $i_{\mathrm{Cb}}$, $i_{\mathrm{Cc}}$, and $i_{\mathrm{Cn}}$.

Figure 5. Simulation results with proposed control strategy.

The THD values of $i_{\mathrm{Sa}}$, $i_{\mathrm{Sb}}$, and $i_{\mathrm{Sc}}$ are 5.51%, 4.44%, and 4.38%, respectively, and those of $i_{\mathrm{La}}$, $i_{\mathrm{Lb}}$, and $i_{\mathrm{Lc}}$ are 35.5%, 31.1%, and 32.1%, respectively (Table 6). The current in the neutral line, $i_{\mathrm{Sn}}$, is significantly reduced. Further, the source current’s RMS value $I_{\mathrm{Sa}}$ for a-phase is 12.6 Arms, $I_{\mathrm{Sb}}$ for b-phase is 11.9 Arms, and $I_{\mathrm{Sc}}$ for c-phase is 10.7 Arms. Conversely, the neutral-line current $I_{\mathrm{Sn}}$ is 1.39 Arms, which corresponds to 8.0% of the rated load current. In the a-phase, the DPF value between the terminal voltage $v_{\mathrm{Ta}}$ and the source current $i_{\mathrm{Sa}}$ is 1.00. Similarly, the DPFs are also 1.00 in b-phase and c-phase, respectively. The DPF values for each phase are maintained at unity. Table 7 lists the RMS values of the receiving-end voltages $v_{\mathrm{Ta}}$, $v_{\mathrm{Tb}}$, and $v_{\mathrm{Tc}}$ in each phase prior to compensation in Figure 3 and after compensation in Figure 5 operation. The phase voltages on the primary side are set as 120, 115, and 110 Vrms, respectively. Before compensation, the RMS values of the receiving-end voltages are 108.1, 102.3, and 107.3 Vrms, exhibiting a large voltage drop. However, after compensation, the RMS values of the receiving-end voltages are 117.4, 109.4, and 113.8 Vrms, respectively. The voltage drops caused by the long-distance high-voltage distribution feeders increased. This confirmed the compensation at the receiving-end while satisfying the standards of IEC 60038. Moreover, the voltage of the DC-capacitor, $v_{\mathrm{DC}}$, is effectively maintained at the reference value $V_{\mathrm{DC}}^{*}$ of 400 Vdc.

Table 6. THD values for Figure 5.

THD	${\mathit{i}}_{\mathbf{S}}$	${\mathit{i}}_{\mathbf{L}}$
a-phase	5.51%	35.5%
b-phase	4.44%	31.1%
c-phase	4.38%	32.1%

Table 7. Before and after comparison in terms of compensation of the RMS value of the receiving-end voltages.

Secondary-Side Line-to-Line Voltages $V_{\mathrm{T}}$	Before Compensation	After Compensation
a-phase	108.1 Vrms	117.4 Vrms
b-phase	102.3 Vrms	109.4 Vrms
c-phase	107.3 Vrms	113.8 Vrms

Therefore, the receiving-end voltage can be compensated for by suppressing the neutral-line current using the proposed phase-specific reactive power control strategy.

4.2. Load Fluctuation for a Phase

The simulation results for Figure 4, which presents the variation in the a-phase load, are shown in Figure 6a,b. Here, $v_{\mathrm{Ta}}$, $v_{\mathrm{Tb}}$, and $v_{\mathrm{Tc}}$ are the receiving-end voltage waveforms, $i_{\mathrm{Sa}}$, $i_{\mathrm{Sb}}$, $i_{\mathrm{Sc}}$, and $i_{\mathrm{Sn}}$ are the source current waveforms, $i_{\mathrm{La}}$, $i_{\mathrm{Lb}}$, $i_{\mathrm{Lc}}$, and $i_{\mathrm{Ln}}$ are the load current waveforms, $i_{\mathrm{Ca}}$, $i_{\mathrm{Cb}}$, $i_{\mathrm{Cc}}$, and $i_{\mathrm{Cn}}$ are the output current waveforms of the four-leg NPC-inverter-based APLC, $v_{\mathrm{DC}}$ is the DC-capacitor voltage waveform, $v_{\mathrm{C}1}$ and $v_{\mathrm{C}2}$ are the capacitor voltage waveforms, and $v_{\mathrm{n}}$ is the neutral-line point voltage waveform.

Figure 6. Simulation results for Figure 4 showing the variation in the a-phase load from (a) 1.0 to 0.6 pu and (b) 0.6 to 1.0 pu.

Figure 6a illustrates the variation in the a-phase load from 1.0 to 0.6 pu. With the a-phase load of 0.6 pu, the THD values of $i_{\mathrm{Sa}}$, $i_{\mathrm{Sb}}$, and $i_{\mathrm{Sc}}$ are 3.63%, 5.69%, and 5.96%, respectively, whereas those of $i_{\mathrm{La}}$, $i_{\mathrm{Lb}}$, and $i_{\mathrm{Lc}}$ are 30.2%, 30.7%, and 32.8%, respectively. The DPF is well-controlled under a-phase load variation. The recorded DPF values for each phases are 1.00, respectively, for both 1.0 and 0.6 pu of a-phase load. The measured DPF values are consistent with the predetermined DPF values, which are unity. The voltage values of $v_{\mathrm{C}1}$ and $v_{\mathrm{C}2}$, where $v_{\mathrm{DC}}=v_{\mathrm{C}1}+v_{\mathrm{C}2}$, during load fluctuation, are almost uniformly distributed. The maximum difference between $v_{\mathrm{C}1}$ and $v_{\mathrm{C}2}$ is 1.1 Vdc, which is only a bias of 0.6%. The difference between the maximum and minimum values of $v_{\mathrm{C}1}$ is 5.3 Vdc, with an amplitude of 2.7%. Similarly, the difference between the maximum and minimum values of $v_{\mathrm{C}2}$ is 4.9 Vdc, which has an amplitude of 2.5%. Thus, even when load fluctuation occurred, the voltage values of $v_{\mathrm{C}1}$ and $v_{\mathrm{C}2}$ have no bias.

Figure 6b illustrates the variation in the a-phase load from 0.6 to 1.0 pu. With the a-phase load of 1.0 pu, the THD values of $i_{\mathrm{Sa}}$, $i_{\mathrm{Sb}}$, and $i_{\mathrm{Sc}}$ are 5.50%, 4.50%, and 4.43%, respectively, whereas those of $i_{\mathrm{La}}$, $i_{\mathrm{Lb}}$, and $i_{\mathrm{Lc}}$ are 35.5%, 31.1%, and 32.1%, respectively. The DPF is well-controlled under a-phase load variation. The recorded DPF values for phases a, b, and c are 1.00, respectively, for both 1.0 and 0.6 pu of a-phase load. The measured DPF values are consistent with the predetermined DPF values, which are unity. The maximum difference between the voltage values of $v_{\mathrm{C}1}$ and $v_{\mathrm{C}2}$ is only 4.2 Vdc. Further, the difference between the maximum and minimum values of $v_{\mathrm{C}1}$ is 14.6 Vdc, with an amplitude of 7.3%. Similarly, the difference between the maximum and minimum values of $v_{\mathrm{C}2}$ is 12.9 Vdc with an amplitude of 6.5%. Thus, even when load fluctuations occurred, the voltage values of $v_{\mathrm{C}1}$ and $v_{\mathrm{C}2}$ have no bias.

In Figure 6a, the maximum and minimum values of the DC-capacitor voltage, $v_{\mathrm{DC}}$, are 405.8 and 398.6 Vdc. In Figure 6b, the maximum and minimum values of the DC-capacitor voltage, $v_{\mathrm{DC}}$, are 407.2 and 382.9 Vdc, too. Thus, the fluctuation rate of the DC-capacitor voltage can be suppressed within 10%, which is practical. From the above, it can be confirmed that a quick recovery can be expected even under load fluctuations.

4.3. Relationship Between Capacitance of DC-Capacitor and THD

In this section, the relationship between the capacitances of the DC-capacitors $C_{\mathrm{p}}$ and $C_{\mathrm{q}}$ and THD is discussed. Figure 7a,b shows the simulation results with the phase-specific reactive power control strategy for different capacitances of the DC-capacitors $C_{\mathrm{p}}$ and $C_{\mathrm{q}}$, respectively. Here, $v_{\mathrm{Ta}}$, $v_{\mathrm{Tb}}$, and $v_{\mathrm{Tc}}$ are the receiving-end voltage waveforms, $i_{\mathrm{Sa}}$, $i_{\mathrm{Sb}}$, $i_{\mathrm{Sc}}$, and $i_{\mathrm{Sn}}$ are the source current waveforms, $i_{\mathrm{La}}$, $i_{\mathrm{Lb}}$, $i_{\mathrm{Lc}}$, and $i_{\mathrm{Ln}}$ are the load current waveforms, $i_{\mathrm{Ca}}$, $i_{\mathrm{Cb}}$, $i_{\mathrm{Cc}}$, and $i_{\mathrm{Cn}}$ are the output current waveforms of the four-leg NPC-inverter-based APLC, and $v_{\mathrm{DC}}$ is the DC-capacitor voltage waveform.

Figure 7. Simulation results for $C_{\mathrm{p}}$ and $C_{\mathrm{q}}$ of (a) 3900 µF and (b) 700 µF.

In Figure 7a, the measured DPF values for each phase are 1.00, and the RMS value of the neutral-line current $I_{\mathrm{Sn}}$ is 1.39 Arms, which corresponds to only 8.0% of the rated load current. The THD values of $i_{\mathrm{Sa}}$, $i_{\mathrm{Sb}}$, and $i_{\mathrm{Sc}}$ are 5.51%, 4.44%, and 4.38%, respectively, whereas those of $i_{\mathrm{La}}$, $i_{\mathrm{Lb}}$, and $i_{\mathrm{Lc}}$ are 35.5%, 31.1%, and 32.1%, respectively.

In Figure 7b, the measured DPF values for each phase are 1.00 and the RMS value of the neutral-line current $I_{\mathrm{Sn}}$ is 1.37 Arms, which corresponds to only 7.9% of the rated load current. The THD values of $i_{\mathrm{Sa}}$, $i_{\mathrm{Sb}}$, and $i_{\mathrm{Sc}}$ are 6.33%, 6.39%, and 5.08%, respectively, whereas those of $i_{\mathrm{La}}$, $i_{\mathrm{Lb}}$, and $i_{\mathrm{Lc}}$ are 36.2%, 32.5%, and 32.8%, respectively.

Table 8 indicates the THD values for Figure 7a,b. From Table 8, the compensation performance is almost the same. Therefore, the same results are obtained regardless of whether the $C_{\mathrm{p}}$ and $C_{\mathrm{q}}$ are 3900 µF or 700 µF. Thus, the capacitances of DC-capacitors $C_{\mathrm{p}}$ and $C_{\mathrm{q}}$ are successfully miniaturized.

Table 8. THD values for Figure 7a,b.

	Figure 7a		Figure 7b
THD	${\mathit{i}}_{\mathrm{S}}$	${\mathit{i}}_{\mathrm{L}}$	${\mathit{i}}_{\mathrm{S}}$	${\mathit{i}}_{\mathrm{L}}$
a-phase	5.51%	35.5%	6.33%	36.2%
b-phase	4.44%	31.1%	6.39%	32.5%
c-phase	4.38%	32.1%	5.08%	32.8%

The simulation results for Figure 4, which is the variation in the a-phase load with the capacitances of DC-capacitors $C_{\mathrm{p}}$ and $C_{\mathrm{q}}$ of 700 µ, F are shown in Figure 8a,b. Here, $v_{\mathrm{Ta}}$, $v_{\mathrm{Tb}}$, and $v_{\mathrm{Tc}}$ are the receiving-end voltage waveforms, $i_{\mathrm{Sa}}$, $i_{\mathrm{Sb}}$, $i_{\mathrm{Sc}}$, and $i_{\mathrm{Sn}}$ are the source current waveforms, $i_{\mathrm{La}}$, $i_{\mathrm{Lb}}$, $i_{\mathrm{Lc}}$, and $i_{\mathrm{Ln}}$ are the load current waveforms, $i_{\mathrm{Ca}}$, $i_{\mathrm{Cb}}$, $i_{\mathrm{Cc}}$, and $i_{\mathrm{Cn}}$ are the output current waveforms of the four-leg APLC, $v_{\mathrm{DC}}$ is the DC-capacitor voltage waveform, and $v_{\mathrm{C}1}$ and $v_{\mathrm{C}2}$ are the capacitor voltage waveforms.

Figure 8. Simulation results for Figure 4 with the capacitance of DC-capacitor of 700 µF, depicting the changes in the a-phase load from (a) 1.0 to 0.6 pu and (b) 0.6 to 1.0 pu.

Figure 8a illustrates the variation in the a-phase load from 1.0 to 0.6 pu. With an a-phase load of 0.6 pu, the THD values of $i_{\mathrm{Sa}}$, $i_{\mathrm{Sb}}$, and $i_{\mathrm{Sc}}$ are 4.31%, 5.69%, and 5.52%, respectively, whereas those of $i_{\mathrm{La}}$, $i_{\mathrm{Lb}}$, and $i_{\mathrm{Lc}}$ are 30.6%, 30.9%, and 32.5%, respectively. The DPF values are well-controlled under a-phase load variation. The measured DPF values for each phases are 1.00. The measured DPF values are consistent with the predetermined DPF values, which are unity. The voltage values of $v_{\mathrm{C}1}$ and $v_{\mathrm{C}2}$, where $v_{\mathrm{DC}}=v_{\mathrm{C}1}+v_{\mathrm{C}2}$, during the load fluctuation are almost uniformly distributed. The maximum difference between $v_{\mathrm{C}1}$ and $v_{\mathrm{C}2}$ is 5.5 Vdc, which is only a bias of 2.8%. The difference between the maximum and minimum values of $v_{\mathrm{C}1}$ is 16.4 Vdc. The ripple ratio of $v_{\mathrm{C}1}$ is approximately 8.2%. Similarly, the difference between the maximum and minimum values of $v_{\mathrm{C}2}$ is 17.5 Vdc. The ripple ratio of $v_{\mathrm{C}2}$ is approximately 8.8%. Thus, even when load fluctuations occurred, the voltage values of $v_{\mathrm{C}1}$ and $v_{\mathrm{C}2}$ have no bias.

Figure 8b illustrates the variation in the a-phase load from 0.6 to 1.0 pu. With the a-phase load of 1.0 pu, the THD values of $i_{\mathrm{Sa}}$, $i_{\mathrm{Sb}}$, and $i_{\mathrm{Sc}}$ are 5.16%, 4.51%, and 4.48%, respectively, whereas those of $i_{\mathrm{La}}$, $i_{\mathrm{Lb}}$, and $i_{\mathrm{Lc}}$ are 35.6%, 31.1%, and 32.1%, respectively. The DPF values are well-controlled under the a-phase load variation. The measured DPF values for each phases are 1.00 for both 1.0 pu and 0.6 pu of a-phase load. The measured DPF values are consistent with the predetermined DPF values, which are unity. The maximum difference between the voltage values of $v_{\mathrm{C}1}$ and $v_{\mathrm{C}2}$ is only 29.1 Vdc. The difference between the maximum and minimum values of $v_{\mathrm{C}1}$ is 61.0 Vdc with an amplitude of 30.5%. Similarly, the difference between the maximum and minimum values of $v_{\mathrm{C}2}$ is 41.0 Vdc with an amplitude of 20.5%. Thus, even when load fluctuations occurred, $v_{\mathrm{C}1}$ and $v_{\mathrm{C}2}$ were balanced.

In Figure 6a, the maximum and minimum values of the DC-capacitor voltage, $v_{\mathrm{DC}}$, are 427.3 and 395.5 Vdc. In Figure 6b, the maximum and minimum values of the DC-capacitor voltage, $v_{\mathrm{DC}}$, are 405.4 and 334.3 Vdc, too. Thus, the fluctuation rate of the DC-capacitor voltage can be suppressed around 10%, which is practical. From the above, it can be confirmed that a quick recovery can be expected even under load fluctuations.

5. Conclusions

This study proposed a method for compensating the receiving-end voltage in 3P4WDF systems using a phase-specific reactive power control strategy implemented with a four-leg APLC using an NPC inverter. The method effectively reduced the neutral-line current. The reference source currents were determined using a derivation block to calculate the reactive current and equations incorporating the active component. When the phase-specific reactive power control was applied using these calculated source currents, sinusoidal currents were generated on the source side; however, the neutral-line current was larger. This study proposed redistributing the active components on the source side to mitigate this issue. By redistributing these active components, the neutral-line current was suppressed while maintaining unity DPFs in each phase. The simulation results show that the proposed phase-specific reactive power control strategy successfully compensated for the receiving-end voltage and achieved sinusoidal source currents with unity DPFs in each phase, thereby reducing the neutral-line current. In addition, it was confirmed that the proposed system quickly recovered and operated normally after the quickly recovery when the load varied. Furthermore, even when the capacitance of the DC-capacitor was reduced, no deterioration in the THD or DPF was observed. Therefore, this study demonstrated that successful operation can be achieved even with a small capacitance of the DC-capacitor. In the future, we will try to improve compensation performance for receiving-end voltage and harmonic current compensation by increasing the number of levels of NPC inverter.