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Application of Diverse Testing to Improve Integrated Circuit Test Yield and Quality

Eng 2024, 5(4), 3517-3539; https://doi.org/10.3390/eng5040183

by Chung-Huang Yeh^1,*

, Shou-Rong Chen² and Kan-Hsiang Liao³

Reviewer 1: Anonymous

Reviewer 2: Anonymous

Reviewer 3:

Lucjan Setlak

Eng 2024, 5(4), 3517-3539; https://doi.org/10.3390/eng5040183

Submission received: 30 October 2024 / Revised: 11 December 2024 / Accepted: 18 December 2024 / Published: 20 December 2024

(This article belongs to the Section Electrical and Electronic Engineering)

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

Point 1:

In section 4, Figure 8 explains the workflow of the proposed DTMs. Instead of traditional test Yt=P, the reiteration of tests increases Yt=PP+PFP+FPP. However, this logic is straightforward because retests can eliminate some test errors from the ATE (like false alarm, etc.). Here are a few questions regrading this workflow:

1) Did the authors consider the time spent in reiterations as a disadvantage of the DTM application? How to balance the trade-offs between the increases of Yt as the time, labor, materials spent on DTMs?

2) Is there a reason to pick three iteration as the best estimate of Yt? Have the authors considers 5 iterations, 7 iterations, etc? In addition to (1), how to optimize iteration numbers and the costs? As it can be expected that the more iterations, the higher Yt. Will there be a convergence of Yt? How to determine if it is worthy to perform an extra iteration?

Point 2:

In section 3, case 1 and case 2 show sample calculation with proposed formula. Table 2 shows estimated test results for different test methods. Did the authors verify if the estimates match the real data? How to validate the proposed model?

Point 3:

Please edit point (5) from line 514: The proposed modeling improves Yt with specific assumption setups (as section 2 indicates), need to specify the assumption in point 5. This statement may not be valid with another set of original chip (other distributions).

Author Response

Dear Sir,

Please find, in the submission section of the authors, our final response to the comments received from the three reviewers to " Application of Diverse Testing to Improve Integrated Circuit Test Yield and Quality."

We appreciate your comments very much, as they have pointed out a number of issues that need to be addressed. We would like to thank the editor and the reviewers for taking time reading and suggesting modifications to the paper, and your cogent comments have proven to be very useful for the improvement of the paper. We did several modifications to the initial manuscript based on the suggestions of the reviewers. We hope that the editor will find the paper eligible for publication. In the answers we have explicate all the changes we have done. We hope that this will be useful for the new review. Thank you very much for your kind consideration of this resubmitted version of our manuscript.

Sincerely yours,

Yeh C-H,

(On behalf of the authors of the manuscript)

COMMENTS FOR THE AUTHOR:

Responses to Reviewers Comments

The responses to the individual comments of three reviewers are detailed below.

(Note: Reviewer comments are in italic, authors' responses are in normal text).

The authors would like to thank all of the reviewers for precise and thoughtful comments and constructive criticism which have helped us refine our manuscript. Below are our responses to each referee comments respectively.

Response to Anonymous Referee #1:
Reviewer #1: Comments to the Author

Comments and Suggestions for Authors

Comment1:

Did the authors consider the time spent in reiterations as a disadvantage of the DTM application? How to balance the trade-offs between the increases of Y_t as the time, labor, materials spent on DTMs?

Response 1:

Thank you for pointing this out. I agree with the reviewer’s comment. The extra time incurred in retesting is indeed the main disadvantage of the DTM method. While trying to improve the test yield and increase the profit of the enterprise, we must consider the cost of the test. Although the tests themselves only account for a small part of the total equipment cost, and the overall contribution of reducing test costs to the manufacturer's profitability will be very small. The rental test machine is charged on an hourly basis. If a company wanted to promote test yield, then more tests must be carried out, which means more test time and test cost were needed to increase a bit of quality; this was not allowed from the perspective of cost. Diverse testing can improve the test yield and test quality; however, if the test time and the number of tests are increased, the test cost will gradually increase. Furthermore, when the increased test cost is higher than the increased profit (the profit obtained by increasing the test yield), it will cause the company's profit to decline. Hence, this method loses practical value when the cost of testing using the method of diverse testing exceeds the profit from the yield increase. Because the performance and value of each chip are different, the test cost is different. It is necessary to do the analysis and calculation of the overall market in order to analyze the detailed data, to assess the test times needed to be added, and to evaluate the maximum profit that the increased test yield can produce.

Comment2:

Is there a reason to pick three iteration as the best estimate of Yt? Have the authors considers 5 iterations, 7 iterations, etc? In addition to (1), how to optimize iteration numbers and the costs? As it can be expected that the more iterations, the higher Yt. Will there be a convergence of Yt? How to determine if it is worthy to perform an extra iteration?

Response 2:

Thanks for pointing out this significant issue. The rental IC tester (ATE) is charged on an hourly basis. If a company wanted to promote test yield, then more tests must be carried out, which means more test time and test cost were needed to increase a bit of quality; this was not allowed from the perspective of cost. Similarly, under the same quality principle, as the frequency of repeat testing increased, the promotion of test yield would tend to moderate gradually without large-scale of increase. However, this method loses practical value when the cost of testing using the method of repeated testing exceeds the profit from the yield increase. If you consider the detailed cost problem, the test cost problem will be more complicated.

As we all know, retesting has been widely used in the IC testing industry and can effectively improve the test yield. However, aimlessly repetitive retesting can cause the cost of testing to surpass the profit from retesting. Because the performance and value of each chip are different, the test cost is different. It is necessary to do the analysis and calculation of the overall market in order to analyze the detailed data, to assess the test times needed to be added, and to evaluate the maximum profit that the increased test yield can produce. Therefore, in order to meet the requirements of manufacturers for high profit and high yield, we plan to propose an intelligent test system in the future. Based on the obtained test yield and test cost, under the feedback of intelligent calculation, the required number of retests is calculated. Reducing the number of tests can avoid unnecessary retesting, save manpower and time, and reduce testing costs. Judging from the feedback of intelligent computing, when the test cost is greater than the profit brought by the yield improvement, the test process is stopped and the next product manufacturing stage is entered. Through the above intelligent testing methods, we can optimize iteration numbers and the costs. Your suggestion is very valuable and worthy of reference as a next-stage paper study.

Comment3:

Response 3:

You have raised an important point here. At this stage, we only performed computer simulation estimation. From the analysis of the simulation results, this method (DTM) has an excellent effect on improving the test yield and quality. Our GRC team (GRC, group reliable computing) will prepare to apply for a patent and complete the physical test system and connection in the next stage. In the past few years, our GRC team has continued to cooperate with ASE Technology Holding Co. (The world's largest chip packaging and testing services) to improve the test plan of the Wafer map and has made good progress. I believe this set of theories and methods will be applied in the actual VLSI test environment shortly. Thank you very much for your comments and suggestions. The comments and suggestions are valuable and very helpful for revising and improving our manuscript.

Comment4:

Response 4:

Thank you for your valuable feedback. We appreciate your suggestions for enhancing the section 5 of our paper. We have revised the point (5) from line 514 on your feedback. The revisions can be found on page 18. Thank you once again for your constructive feedback. The specific changes are as follows:

On the basis that the chip characteristics are normally distributed, the paper proposes an IC retesting solution to address the challenges associated with semi-conductor IC shipment and low yield. According to the above experiments, the paper proposed method (DTM) offers the following contributions:

(1) The method accurately estimates the test yield and test quality of future wafers through iterative derivation and calculation.

(2) DITM not only predicts and accurately depicts the test yield curve of future wafers but also enables tester manufacturers to enhance the testing capabilities and methods of ATE in advance according to the estimated data.

(3) The proposed method enhances the testing capabilities of the IC tester (ATE) and mitigates the occurrence of killing errors (α, Type I) and missing errors (β, Type II) in test chips.

(4) The proposed method challenges traditional theoretical concepts by simultaneously increasing output and quality, thereby increasing the company’s shipment volume and alleviating market chip shortages.

(5) The proposed method effectively improves the test yield, thereby significantly enhancing the yield of the tested products. This not only stabilizes the chip supply chain but also enhances company profits. Furthermore, it significantly enhances the company’s overall product profits and corporate reputation.

(6) The proposed DTM can achieve zero-defect and reliable products by moving the test guard band (TGB).

We assume the normal state only for the convenience of calculation, and our method can be deduced to other distributions. If the IC characteristics or test signals are abnormally distributed, the inferred test yield may be different. But in theory, the diverse test method works by moving test guardband (changing test specifications) and this method can eliminate abnormal components from total components. Therefore, even if the IC characteristics or the distribution of test signals are abnormal, we are confident that the method of repeated testing will still get a considerable increase in yield.

Thank you for your comments. We have gone through your comments carefully and tried our best to address them one by one. We hope the manuscript has been improved accordingly.

Sincerely yours,

Chung-Huang Yeh

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

This study presents a novel approach to addressing the ongoing challenges in semiconductor manufacturing caused by the COVID-19-induced disruptions and persistent chip shortages. By leveraging a digital integrated circuit testing model, the research evaluates the impact of test guardband (TGB) adjustments on the test yield curve of future wafers and proposes the Diverse Test Method (DTM) to enhance testing efficiency and outcomes. The findings demonstrate the potential of DTM to improve wafer quality, increase test yields, and optimize the capabilities of Automatic Test Equipment (ATE) based on projections from the IEEE International Roadmap for Devices and Systems (2023). The primary strength of the study lies in its practical contribution to stabilizing chip supply chains and improving industry profitability; however, the results are limited by the reliance on simulation models, which may not fully capture real-world manufacturing complexities.

My comments:

Introduction. Despite the fact that the review of studies is done qualitatively, the introduction lacks key elements, namely:

1. Unresolved issues are not highlighted.

2. The purpose of the research is not clearly formulated.

3. The contribution of the study to the subject area is not shown.

Chip Manufacturing and IC Testing Errors. This section demonstrates that semiconductor testing ensures chip functionality aligns with test specifications (TS) by eliminating defective units, with test accuracy enhanced through the application of a test guardband (TGB), defined as the difference between design specifications (DS) and TS, TGB=DS−TS. One potential limitation of the approach discussed in this section is the reliance on a fixed test guardband (TGB), which may not account for variability in manufacturing processes, potentially leading to suboptimal trade-offs between yield and quality. How can the test guardband (TGB) be dynamically adjusted to account for variability in manufacturing processes and optimize the balance between yield and quality?

2.1. IC manufacturing yield calculation and estimation. 2.2. Derivation and estimation of IC test yield and defect levels. 2.3. Analysis for defect-level estimation of IC. These sections describe the mathematical apparatus, which fully reveals the proposed approaches. No comments.

Impact of TGB on Test Results. This section presents the results of the research. The high cost of ATE systems, ranging from $1 million to $4 million, necessitates that test engineers balance test yield and quality with economic considerations, selecting IC testers that meet customer quality demands and align with market conditions. How can test engineers optimize the selection of IC testers to balance cost efficiency with the required test yield and quality under varying market conditions?

Schedule of Diverse Testing. This section shows that the rapid advancements in semiconductor technology over the past decades have enhanced chip performance, but the increasing complexity of technologies and products has raised costs in production and verification. To address these challenges, various wafer-retesting schemes have been proposed, including predictive models, optimization approaches, and machine learning algorithms aimed at improving testing quality, reducing defects, and minimizing costs. The growing complexity of semiconductor technologies and the persistent chip shortage have led to increased challenges in product verification and testing. To mitigate these issues and improve test yield, various wafer-retesting schemes have been proposed, utilizing predictive models, optimization methods, and machine learning algorithms to enhance testing accuracy and reduce defects.

The conclusions are written qualitatively. The conclusions fully reflect the obtained results.

I recommend that the references be formatted in accordance with the requirements of the MDPI, and that outdated sources from 1998, 1999, 2001, and 2009 be replaced with more modern ones.

Author Response

Dear Sir,

Sincerely yours,

Yeh C-H,

(On behalf of the authors of the manuscript)

COMMENTS FOR THE AUTHOR:

Responses to Reviewers Comments

The responses to the individual comments of three reviewers are detailed below.

(Note: Reviewer comments are in italic, authors' responses are in normal text).

Response to Anonymous Referee #2:
Reviewer #2: Comments to the Author

Comments and Suggestions for Authors

Comment1:

Introduction. Despite the fact that the review of studies is done qualitatively, the introduction lacks key elements, namely:

Unresolved issues are not highlighted.
The purpose of the research is not clearly formulated.
The contribution of the study to the subject area is not shown.

Response 1:

Thank you for your comments and suggestions that allowed us to greatly improve the quality of the manuscript. We have supplemented the description in the introduction of the paper. Furthermore, at the end of Section 1 (Introduction), we have listed the key contributions of this paper. The revisions can be found on page 2. Thank you once again for your constructive feedback. The specific changes are as follows:

Transistors on integrated circuits (ICs) exponentially grow according to Moore’s law, with their number doubling every 18 to 24 months. When the number of transistors per unit area doubles, chip performance typically improves by 40% compared with the previous generation, which has resulted in faster and unpredictable development in the semiconductor industry [1–4]. As semiconductor manufacturing processes continue to advance rapidly, accurately forecasting future trends in IC product development is increasingly becoming challenging [5–8]. Consequently, the paper explores the interplay between semiconductor manufacturing capability parameters and testing capability parameters, leveraging statistical probability and the digital integrated circuit testing model (DITM) [9–13] to estimate IC manufacturing yield (Y_m) and testing yield (Y_t). Additionally, the paper employs an iterative calculation method (DITM) to precisely project future IC test yield curves, utilizing data from the IEEE International Equipment and Systems Roadmap (IRDS, 2023) [14].

As semiconductor test equipment (such as IC testers and ATE) capabilities fail to meet the yield and quality requirements of wafers, foundries (fabs) must seek more effective alternative testing methods to enhance testing quality and yield. To address the significant challenges posed by the low test quality and test yield of semiconductor wafers, various wafer-retesting schemes have been proposed across academia and industry. For instance, Kirmse et al. introduced a novel wafer probabilistic model [15] designed for timely analysis of wafer operations and provided recommendations for wafer retesting. This approach promises quicker and more efficient detection of test errors. Jang, S.I. et al. [16] proposed an automated wafer-retesting system for enhancing test yields in wafer probing tests. They developed an artificial neural network model to differentiate between types of wafer failures and employed the error back-propagation algorithm for neural network training. This system has been implemented in mass production, resulting in an approximately 0.1% increase in total wafer yield and an approximately 80% reduction in total wafer test time. Furthermore, Jena, S.K. et al. [17] identified acceptable circuits (AcIC) through retesting, indirectly improving effective yield. The idea is to divide the testing process into two phases. In the first phase, the research paper follows the traditional testing process architecture and collect rejected circuits. In the second phase, all circuits that were rejected or not tested perfectly in the first phase undergo retesting using specific test patterns. Although this approach does not strictly adhere to the definition of AxIC, it can significantly improve yield. Additionally, Selg, H. et al. proposed [18] a mechanism that applies machine learning to effectively predict whether failed wafers should be retested. This method monitors wafers, providing data on initial and subsequent test runs. Experimental results using actual commercial product data validate the efficiency of the retest-success prediction method, leading to a significant optimization of manufacturing test time with a prediction accuracy of 78%. Building on the foundational concept of retesting [19], the research introduces the diverse testing method, which involves changing the testing process. In this method, we used iterative derivation calculations to estimate the test yield and quality of future wafers. Moreover, by leveraging the chip product forecast table released by the IEEE International Equipment and Systems Roadmap (IRDS, 2023), the proposed testing method can enhance the capabilities of semiconductor test equipment (ATE) and chip productivity. Furthermore, to meet consumers’ requirements for product quality, the proposed DTM can improve both test yield and quality, and facilitate the screening of high-quality, zero-defect products. To select high-quality chips, we modified the entire testing process and the testing specifications. Among them, one approach involves adjusting the test guard band (TGB) to minimize Type I (α) and Type II (β) errors, thereby extending the test time to identify reliable and marketable products. The proposed repeated testing method breaks the conventional theoretical concept of mutual exchange between yield and quality. Overall, the DTM mechanism can reduce the number of defective wafers and increase wafer shipments without reducing product yield. The proposed DTM method can be used to improve the testing capabilities of the machine and address solutions to the following constraints:

(1) A curve that can predict future wafer yield and quality;

(2) Strengthen the testing capabilities of the ATE;

(3) Reduce the occurrence of errors during the testing process and improve chip shipments and product quality;

(4) Stabilize the chip supply chain.

We have revised our manuscript according to your comments and suggestions point by point.

Comment2:

Response 2:

During testing process, because of the problem of tester inaccuracy, the ST sent by tester would have edge placement. When the ST sent by tester is faster than the time set by the tester, the testing error probability of determining “good” as “fail” would increase; on the contrary, when the ST sent by tester is slower than the time set by the tester, then the testing error probability of determining “bad” as “pass” would increase. Thus, the accuracy of tester should also be taken into consideration when using tester to measure the device under test. When considering the problem of tester inaccuracy, guardband test must be used. Fig. 7 showed TGB (Test Guardband), it is defined as the distance of test specifications and design specifications (TGB = DS – TS); assuming TGB is expanded, then test specification would be stricter and that might cause the increase of killing error and decrease of missing error. In other words, test yield would decrease due to the expansion of TGB, while test quality would be promoted correspondingly. Assuming TGB is lessened, then test specification would be looser and that might cause the increase of missing error and decrease of killing error. In other words, test yield would increase due to the lessening of TGB, while test quality would be worsened and that led to huge amount of returned products. Therefore, the use of TGB could serve as a weighing factor of test yield and test quality.

It is important to select a test point to fully satisfy the custom's requirement. We first set the scope of the test quality, then use the movement of the Test Guardband to find the appropriate test specifications. When using traditional testing method, test guardband could be changed and moved, and product test yield and test quality could be exchanged but could not be obtained concurrently. Defective manufacturing would lead to product defect, so it is necessary to adjust test guardband appropriately during the test process in order to pick most of the defective products out. Then, according to the above DL and TSs, the test guardband was moved, and the test range was narrowed. Finally, the product conformed to the quality conditions, and the best TSs were found. If stricter TSs are used, the test pass rate will be reduced, and the test quality will be relatively improved. Assuming that the TGB is lowered, that is, a loose TS is used, the test pass rate will increase, and the test quality will be relatively reduced. As seen from the above analysis, the TSs directly affect the final test yield. Therefore, test engineers must be careful in choosing TSs.

Thank you for your comments. We have gone through your comments carefully and tried our best to address them one by one. We hope the manuscript has been improved accordingly.

Comment3:

Response 3:

Thank you for your helpful comments. We have revised our paper accordingly and feel that your comments helped clarify and improve our paper.

Comment4:

Response 4:

Over the past 30 years, ICs have become increasingly smaller, but their complexity has increased. According to the ITRS roadmap, semiconductors maintain an annual progress rate of 30%. However, ATE maintains an annual improvement rate of 12%. The development speed of the tester is far slower than that of the semiconductor device fabrication. If the trend continues, the inaccuracy of the tester will cause a large loss of yield. Furthermore, several factors affect the test results, such as the tester quality and the TSs (test guardband). In addition to the yield rate, it is also important to choose the appropriate tester. The OTA is the accuracy specification parameter of the tester, which can be used to indicate the tester testability. Here, the test standard deviation, σT, is set to three times that of the OTA. The smaller the OTA value, the better is the test capability, and a high test quality yield rate can be obtained. Conversely, when the OTA value is larger, the test quality and yield will decrease. This makes the problems of missing and killing errors more serious. Undoubtedly, a tester with high accuracy (OTA) would certainly cost a lot. The rental test machine is charged on an hourly basis. However, a high-precision tester will require more testing costs; therefore, test decision-makers should also consider how to choose cost-effective test equipment based on market demand.

This method loses practical value when the cost of testing using the method of repeated testing exceeds the profit from the yield increase. Because the performance and value of each chip is different, the test cost is different. It is necessary to do the analysis and calculation of the overall market in order to analyze the detailed data, to assess the times needed to be added, and to evaluate the maximum profit that the increased test yield can produce. If you consider the detailed cost problem, the test cost problem will be more complicated. Thank you very much for your comment and suggestion. It will be considered as the research direction of the next stage of the thesis.

The comments and suggestions are valuable and very helpful for revising and improving our manuscript.

Comment 5:

The conclusions are written qualitatively. The conclusions fully reflect the obtained results.

Response 5:

Thank you for your valuable feedback. We appreciate your suggestions for enhancing the conclusion of our paper. We have revised the conclusion on your feedback. The revisions can be found on page 19. Thank you once again for your constructive feedback. The specific changes are as follows:

The paper employs the DITM for estimating test results in wafer testing. Through iterative derivation and calculation, the test yield and quality of the wafer are estimated. Additionally, the paper utilizes forecast data from the 2023 IRDS table to predict future trends in test yield. The DITM iterative calculation method not only forecasts the test yield curve of forthcoming wafers but also enables test houses to enhance and adjust tester functionalities and test methods according to the predicted curves. Despite the rapid progress in semiconductor manufacturing technology, the development of IC testers has progressed very slowly. Manufacturing technology and testing technology are evolving at different speeds, resulting in testing manufacturers being unable to effectively distinguish product quality using current IC testers (ATE) and testing methods. Hence, the paper introduces the DTM to enhance test outcomes. This method involves testing through various process mechanisms and dynamically adjusting the TGB.

A chip product estimation table was released through the IEEE International Roadmap for Devices and Systems (IRDS, 2023), DTM, and effective iterative calculations. The research demonstrated that our proposed method could notably enhance the testing yield by over 20% compared with relatively outdated IC testers (ATEs). Furthermore, zero-defect high-quality products (Zero Defect Manufacturing, ZDM) are the ultimate goal pursued by the semiconductor industry. However, traditional chip testing must sacrifice the yield in exchange for a high yield. Considering aerospace and automotive electronics chips that require high reliability, the proposed DTM can extend the test time and change the test guard band (TGB). Retesting wafers that pass the test multiple times without sacrificing yield, the DTM reduces errors during the test process and adjusts the TGB to reduce the occurrence of killing and missing errors. Apart from enhancing the testing capabilities of the IC tester (ATE), through repeated testing, we searched for reliable products and obtained close to zero-defect products (10 ppm). Undoubtedly, DTM enhances the testing capabilities of IC testers and the quality of the tested products. Furthermore, considering the potential for future chip shortages and supply disruptions, DTM could help electronics manufacturers maintain increased productivity and stabilize the chip supply chain, resulting in a significant increase in company profit.

Comment 6:

I recommend that the references be formatted in accordance with the requirements of the MDPI, and that outdated sources from 1998, 1999, 2001, and 2009 be replaced with more modern ones.

Response 6:

All have been modified. Thanks for your friendly reminder.

Dong, H.; Chen, N.; Wang, K. Wafer yield prediction using derived spatial variables. Reliab. Eng, 2017, 2327-2342.
Pak, S.; Park.; Cho, J.; An, D.; Park, C.; Kim, J.; Baek, J. Yield Prediction Using Support Vectors Based Under-Sampling in Semiconductor Process. WASET, Open Science Index 72, International Journal of Industrial and Manufacturing Engineering, 2012, 6(12), 2755 - 2759.
Jang, S-J.; Kim, J-S.; Kim, T-W.; Lee, H-J.; Ko, S. A Wafer Map Yield Prediction Based on Machine Learning for Productivity Enhancement. in IEEE Transactions on Semiconductor Manufacturing, , Nov. 2019, 32, no. 4, 400-407. https://doi: 10.1109/TSM.2019.2945482.
Yeh, C.H.; Chen, J.E. Using the Test Guardband Estimation Method to Forecast Future Semiconductor Yield Trends. IETE Journal of Research. 2024, 1–14. https://www.semiconductors.org/resources/2015-international-technology-roadmap-for-semiconductors-itrs/.
International Technology Roadmap for Semiconductors 2.0., System Integration. 2015. Available online: http://www.itrs2.net/itrs-reports.html (accessed on 7 July 2024).
The IEEE International Roadmap for Devices and Systems Table; 2017 Edition, 18–23. Available online: https://irds.ieee.org/images/files/pdf/2017/2017IRDS_MM.pdf (accessed on 4 Dec 2024 ).
The IEEE International Roadmap for Devices and Systems Table; 2021 Available online: https://irds.ieee.org/images/files/pdf/2021/2021IRDS_SA.pdf (accessed on 4 Dec 2024 ).
The IEEE International Roadmap for Devices and Systems Table; 2022 Available online: https://irds.ieee.org/images/files/pdf/2022/2022IRDS_ES.pdf (accessed on 4 Dec 2024 ).
Yeh, C.H.; Chen, J.E. The Decision Mechanism Uses the Multiple-Tests Scheme to improve Test Yield in IC Testing. In Proceedings of the 2020 IEEE International Test Conference in Asia (ITC-Asia), Taipei, Taiwan, 23–25 September 2020, 88–93.
Yeh, C.H.; Chen, J.E. Recycling Test Methods to Improve Test Capacity and Increase Chip Shipments. IEEE Des. Test 2022, 40, 45–52.
Yeh, C.H.; Chen, J.E. Application of Three-Repetition Tests Scheme to Improve Integrated Circuits Test Quality to Near-Zero Defect. Sensors 2022, 22, 4158. https://doi.org/10.3390/s22114158.
Yeh, C.H.; Chen, J.E. Repeated Testing Applications for Improving the IC Test Quality to Achieve Zero Defect Product Requirements. Electron. Test, 2019, 35, 459–472.
Yeh, C.H.; Chen, J.E. Unbalanced-Tests to the Improvement of Yield and Quality. 2022, 10, 3032. https://www.mdpi.com/2079-9292/10/23/3032.
The IEEE International Roadmap for Devices and Systems Table; 2023 Available online: https://irds.ieee.org/editions/2023/20-roadmap-2023-edition (accessed on 4 Dec 2024 ).
Kirmse, M.; Petersohn, U.; Paffrath, E. Optimized Test Error Detection by Probabilistic Retest Recommendation Models. In Proceedings of the 2011 Asian Test Symposium, New Delhi, India, 20–23 November 2011, 317–322.
Jang, S. I.; Lee, J. H.; An Automated Retesting Approach for Wafer Probing Test Systems Using Neural Networks. In Proceedings of The World Congress on Engineering and Computer Science (WCECS 2011). San Francisco, USA, 1058-1063.
Jena, S. K.; Biswas S.; Deka, J. K. Maximizing Yield through Retesting of Rejected Circuits using Approximation Technique. In Proceedings of The 2020 IEEE REGION 10 CONFERENCE (TENCON 2020), Osaka, Japan, 182-187. https://doi: 10.1109/TENCON50793.2020.9293891.
Selg, H.; Jenihhin, M.; Ellervee, P. Wafer-Level Die Re-Test Success Prediction Using Machine Learning. In Proceedings of the 2020 IEEE Latin-American Test Symposium (LATS), Maceio, Brazil, 30 March–April 2020, 1–5.
Yeh, C.-H.; Chen, J.-E. Retesting Schemes That Improve Test Quality and Yield Using a Test Guardband. Eng 2023, 4, 3007-3025. https://doi.org/10.3390/eng4040169.
Mezouara, H.; Dlimi, L.; Salih, A.; Afechcar, M. Determination of the Optimal Guardbanding to Ensure Acceptable Risk Decision in the Declaration of Conformity. 2014.
Yu, K.; Qi, J. Evaluation and analysis of domestic ATE based on IC testing application. 2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), Nangjing, China, 2022, pp. 1-3. doi: 10.1109/ICSICT55466.2022.9963195.
Yan, H.; Feng, X.; Hu Y.; Tang, X. Research on Chip Test Method for Improving Test Quality. 2019 IEEE 2nd International Conference on Electronics and Communication Engineering (ICECE), Xi'an, China, 2019, pp. 226-229. doi: 10.1109/ICECE48499.2019.9058553.
Park, I.; Lee, D.; Chmelar, E.; McCluskey. E. J. Inconsistent Fail due to Limited Tester Timing Accuracy. 26th IEEE VLSI Test Symposium (vts 2008), San Diego, CA, USA, 2008, pp. 47-52. https://doi: 10.1109/VTS.2008.23.
Yeh, C.H.; Chen, J.E. Test yield and quality analysis models of chips. Journal of the Chinese Institute of Engineers. 2020, 43(3), 279–287. doi: 10.1080/02533839.2019.1708806.
Greenberg, B. S., & Stokes, S. L. Repetitive Testing in the Presence of inspection Errors. Technometrics, 37(1), 102–111. https://doi.org/10.1080/00401706.1995.10485893.
Horng, S.C.; Lin, S.Y.; Cheng, M.H.; Yang, F.Y.; Liu, C.H.; Lee, W.Y.; Tsai, C.H. Reducing the overkills and retests in wafer testing process. In Proceedings of the Advanced Semiconductor Manufacturing Conference and Workshop (IEEEI/SEMI 2003), Munich, Germany, 31 March–1 April 2003, 286–291.
Cheng, K. C. -C. et al.; Machine Learning-Based Detection Method for Wafer Test Induced Defects. in IEEE Transactions on Semiconductor Manufacturing, May 2021, vol. 34, no. 2, 161-167. https://doi: 10.1109/TSM.2021.3065405.

Thank you for your comments. We have gone through your comments carefully and tried our best to address them one by one. We hope the manuscript has been improved accordingly.

Sincerely yours,

Chung-Huang Yeh

Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

After reading the paper sent for review, it should be noted that the manuscript in terms of content was developed at a very high scientific level, thus contributing to the knowledge of the proposed strategy in the area of application of diverse tests for increasing the yield and quality of integrated circuit (IC) testing.

To this end, the authors of this article based their research inquiries on both using the iterative calculation method of DITM (integrated circuit testing model) to predict the test performance curve of future boards, and thus obtain and adjust the functionality of testers and techniques, as well as primarily to create an IC test model for calculating the test performance curve and doing the necessary research on the impact of TGB (test guardband) on quality and performance.

The authors realized their concept/technical approach to solve the scientific problem through a comprehensive research not only based on the conducted critical analysis of the literature of the research subject [1]-[27], or the proposed mathematical model using formulas (1)-(8) or experimental tests, simulations, tabulation, etc..., but mainly as a result of verification of the results obtained by making comparative characteristics of the techniques used (DTMs and traditional TTM methods) based on the estimation of IRDS (2023) test performance using DTMs (diverse testing methods), presented in Figures 9-11 and tabular summaries (Tables 2-3) in Chapters 4-5, respectively., and on this basis presented relevant insights and formulated final conclusions, reflected in practical applications.

The article submitted for review, both in terms of methodology and, above all, in the field of content, is characterized by a very high research level, making a significant scientific contribution that contributes to the deepening of knowledge in various fields, including electronics, computer science, including industrial engineering and manufacturing engineering for the purpose of conducting differentiated tests in improving the performance and quality of the techniques used to test ICs.

It should be noted that this is very important from the point of view of existing knowledge, as evidenced by the results obtained by the authors in terms of the adopted strategy for solving the research problem.

For example, in order to confirm the above assessment, it should be emphasized that the authors of this manuscript not only presented substantive knowledge in accordance with the subject of the research, discussed and analysed in detail their research to solve the scientific problem, but above all, with the help of in-depth analysis, the use of apt methods (TTM, DTM, TGB, etc. ), supported by the use of mathematical apparatus within the framework of the applied approach using the developed digital model of IC testing, they made comparative characteristics of traditional (TTM) and proposed techniques (DTM) within the framework of the use of various tests for the purpose of improving both the performance and quality of ICs testing.

Methodologically, including in terms of the layout and structure of the construction of the presented paper, apart from the introduction according to the subject of the study (Chapter 1), based on the critical analysis of the literature made, the authors carried out the characterization of the subject of the study, i.e. iterative computational technique (DTIM) for improving the performance and quality of the IC tests carried out by highlighting the errors arising during chip manufacturing and IC testing presented in Chapter 2 in terms of calculating and evaluating manufacturing performance , as well as determining and estimating IC test performance and defect levels , including in the aspect of evaluating the defect level of the IC analysed.

It should be noted that the proposed approach related to the use of various tests to improve the yield and quality of IC testing, was made not only through an in-depth analysis supported by the use of mathematical apparatus, graphical depiction of the cited components of the IC testing process, including errors during production, characteristics, modules, graphs, etc., but also through the comparative characteristics of selected techniques (TTM, DTM, DTM, etc.). (Figs. 1-8), but also through the comparative characteristics of selected techniques (TTM, DTM), presented both graphically (Figs. 9-11) and through tabular summaries (Tables 1-3) showing the comparison of performance and quality using the proposed testers (OTA, TTM) and estimated test results for different test methods.

During the review of this paper, with the exception of minor editing errors and some inaccuracies of a methodological nature, particularly in the abstract and in the final part of the paper, no other shortcomings were observed in this paper, having a key impact on the level and quality of the work presented.

Abstract:

In accordance with the recommendations of reputable publishing houses and journals, e.g., IEEE TTE, IEEE Access, Wiley and Sons, or MDPI, part of the abstract should contain the following basic elements: introduction (reference to the subject matter of the study), clear definition of the aim of the work, approximation/addressing of the potential solution to the problem/methods, and response to on the basis of the research, test, experience, developed mathematical model, to formulate relevant observations and final conclusions.

The abstract should not exceed 200 words, in this article there are 203 of them. In my opinion, the abstract section of this paper lacks both the key element, i.e. the citation of the explicit purpose of the paper developed, as well as the reference to the insights and conclusions formulated (the conclusion section of the paper) in the context of the approach used and the prediction of the results obtained.

Inaccuracies observed in part of the abstract of this article:

Lack of clear definition of the purpose of the study.
There is no clear reference either to the expected and predicted results of the research (analysis, model, simulations, verification, etc.) or to the relevant insights and final conclusions reflected in practical applications.
In the abstract of the article, work or manuscript, it is not recommended to explain the abbreviations, as it is done in this manuscript, e.g. TGB, DTM, ATE. It should be noted that these are not serious shortcomings, but in my opinion the summary should focus on the much more important elements (aim, results achieved, methods used, conclusions, etc.). In my opinion, the abbreviations used in the abstract should be explained in the rest of the paper, i.e. for example in the introduction, key words or in the rest of the work.

The rest of the paper:

Inaccuracies noted in the rest of the paper:

1. According to my opinion, it is not advisable to present the sequences in the personal form, e.g. of the type our ..., we ... etc.., as is done in this paper both in the abstract and in the rest of the paper, e.g., regarding the use of we ..., p. 1, points 9 and 17 (abstract), or p. 1, points 34 and 37 (introduction); p. 2, 4-5, 8, 12, 14-16 and 18. Similarly, regarding the use of our ..., e.g., on p. 18, points 501, 534-535 and 539. The content in the paper should be in the impersonal form or in the 3rd person, please check the entire paper in this regard.

2. In methodological terms, in my opinion, it is not advisable to present figures/tables or formulas in the concluding part of a chapter/subchapter, point/subpoint, etc., ... as has been done in this article, e.g., Figure 1 on page 3; Figure 2 on page 4 and Figure 9 on page 15; in the case of tables, Table 1 on page 11, or formula (8) on page 13.

3. Duplication of explanations of some abbreviations both in the abstract and in the rest of the work, e.g., TGB on page 2, points 67-68; DTM on page 2, point 66, or on pages 15-17, points116, 476 and 495-496, respectively, in the case of figure descriptions (Figures 9-11). Please check the entire work in this regard.

4. The article observed both a lack of proper order and duplication, such as [16] on page 2 for reference [16] to reference [19], points 46, 49, 54 and 60, and [16-22] and [15], points 66 and 71, respectively. Also, [5-8] on page 3, point 100; [9, 10] on page 5, point 134; [23, 24] on page 7, point 202; [5-8] on page 10, point 278; [16-22] on page 11, point 326; [20], [21] and [22] on page 11, points 327, 330 and 334, respectively, or [15] on page 15, point 436, etc. ... Please check the entire work in this regard and make the appropriate corrections if possible.

5. When presenting the mathematical model in the form of formulas (1)-(8), I noticed a failure to keep them unambiguous, e.g., p. 4, point 125 .....; pp. 8-9, points 240-261, where there is no numbering.

6. Duplication of explanations of the notation of some abbreviations both in the text of the work and in the case of descriptions of figures. For example, test yeld (Yt), pp. 1, 6, 10, or in the case of test quality (Yq), pp. 1, 6, 8, 16, or OTA on p. 8, 10, etc., respectively. ... Please check the entire paper in this regard and make appropriate corrections if possible.

7. Quoting too short sequences, e.g. page 5, points 142-143. Please check the whole article in this respect.

8. In the paper, I observed a lack of explanation of some abbreviations, such as FET. Please check the entire article in this regard.

9. The final conclusions should be supported by the obtained research results. This is all the more incomprehensible, since the reviewed manuscript was prepared by the authors at a very high scientific level, especially in terms of the research performed (in-depth analysis, simulations, verification tests, comparative characterization, etc.), as well as in terms of in-depth analysis of the results obtained.

Strong aspects:

A technical approach, an idea to solve the problem and its explanation, a thorough analysis of the obtained research results supported by the formulation of final conclusions, the adequacy of the methods used and the ability to use them.

Weak aspects:

Minor shortcomings that do not significantly affect the quality of the reviewed work, i.e. editorial errors and low quality of the methodological part (abstract and conclusion).

Recommended changes:

Regardless of the Editor's decision, at this stage of the work, I would recommend that the authors improve the paper in accordance with the recommendations in points 1-9 (weak aspects) and other observations in this review.

In addition, it should be noted that the high evaluation of this manuscript was influenced by many factors, including a thorough and critical analysis of the current state of knowledge, properly designed layout and structure of the work, and most importantly, the properly conducted research (analysis, testing, design), supported by graphic illustration and tabulation of the obtained results, having a significant impact on the important observations and formulation of the final practical conclusions.

The article was developed correctly except for minor inaccuracies both methodologically and mainly in terms of content, contributing a very large body of theoretical and practical knowledge in the field of research and thus contributing to scientific development.

Author Response

Dear Sir,

Sincerely yours,

Yeh C-H,

(On behalf of the authors of the manuscript)

COMMENTS FOR THE AUTHOR:

Responses to Reviewers Comments

The responses to the individual comments of three reviewers are detailed below.

(Note: Reviewer comments are in italic, authors' responses are in normal text).

Response to Anonymous Referee #3:
Reviewer #3: Comments to the Author

Comment1:

1.According to my opinion, it is not advisable to present the sequences in the personal form, e.g. of the type our ..., we ... etc.., as is done in this paper both in the abstract and in the rest of the paper, e.g., regarding the use of we ..., p. 1, points9 and 17 (abstract), or p. 1, points 34 and 37 (introduction); p. 2, 4-5, 8, 12, 14-16 and 18. Similarly, regarding the use of our ..., e.g., on p. 18, points 501, 534-535 and 539. The content in the paper should be in the impersonal form or in the 3rd person, please check the entire paper in this regard.

Response 1:

Thanks for pointing out this significant issue. We have revised our manuscript based on your comments and suggestions.

Comment 2:

In methodological terms, in my opinion, it is not advisable to present figures/tables or formulas in the concluding part of a chapter/subchapter, point/subpoint, etc., ... as has been done in this article, e.g., Figure 1 on page 3; Figure 2 on page 4 and Figure 9 on page 15; in the case of tables, Table 1 on page 11, or formula (8) on page 13.

Response 2:

Thank you for your valuable feedback. We hope these changes meet your expectations and improve the overall quality of the paper. Thank you once again for your constructive feedback.

Comment 3:

Duplication of explanations of some abbreviations both in the abstract and in the rest of the work, e.g., TGB on page 2, points 67-68; DTM on page 2, point 66, or on pages 15-17, points116, 476 and 495-496, respectively, in the case of figure descriptions (Figures 9-11). Please check the entire work in this regard.

Response 3:

Thank you very much for your valuable feedback. We appreciate the time and effort you have taken to review our manuscript. Based on your suggestions, We have revised our manuscript according to your comments and suggestions point by point. We hope that this revision meets your expectations and improves the overall quality of the manuscript. If there are any specific areas that require further attention, please provide additional details, and we will address them promptly. Once again, thank you for your constructive feedback.

Comment 4:

The article observed both a lack of proper order and duplication, such as [16] on page 2 for reference [16] to reference [19], points 46, 49, 54 and 60, and [16-22] and [15], points 66 and 71, respectively. Also, [5-8] on page 3, point 100; [9, 10] on page 5, point 134; [23, 24] on page 7, point 202; [5-8] on page 10, point 278; [16-22] on page 11, point 326; [20], [21] and [22] on page 11, points 327, 330 and 334, respectively, or [15] on page 15, point 436, etc. ... Please check the entire work in this regard and make the appropriate corrections if possible.

Response 4:

All have been modified. Thanks for your friendly reminder. The specific changes are as follows:

Dong, H.; Chen, N.; Wang, K. Wafer yield prediction using derived spatial variables. Reliab. Eng, 2017, 2327-2342.
Pak, S.; Park.; Cho, J.; An, D.; Park, C.; Kim, J.; Baek, J. Yield Prediction Using Support Vectors Based Under-Sampling in Semiconductor Process. WASET, Open Science Index 72, International Journal of Industrial and Manufacturing Engineering, 2012, 6(12), 2755 - 2759.
Jang, S-J.; Kim, J-S.; Kim, T-W.; Lee, H-J.; Ko, S. A Wafer Map Yield Prediction Based on Machine Learning for Productivity Enhancement. in IEEE Transactions on Semiconductor Manufacturing, , Nov. 2019, 32, no. 4, 400-407. https://doi: 10.1109/TSM.2019.2945482.
Yeh, C.H.; Chen, J.E. Using the Test Guardband Estimation Method to Forecast Future Semiconductor Yield Trends. IETE Journal of Research. 2024, 1–14. https://www.semiconductors.org/resources/2015-international-technology-roadmap-for-semiconductors-itrs/.
International Technology Roadmap for Semiconductors 2.0., System Integration. 2015. Available online: http://www.itrs2.net/itrs-reports.html (accessed on 7 July 2024).
The IEEE International Roadmap for Devices and Systems Table; 2017 Edition, 18–23. Available online: https://irds.ieee.org/images/files/pdf/2017/2017IRDS_MM.pdf (accessed on 4 Dec 2024 ).
The IEEE International Roadmap for Devices and Systems Table; 2021 Available online: https://irds.ieee.org/images/files/pdf/2021/2021IRDS_SA.pdf (accessed on 4 Dec 2024 ).
The IEEE International Roadmap for Devices and Systems Table; 2022 Available online: https://irds.ieee.org/images/files/pdf/2022/2022IRDS_ES.pdf (accessed on 4 Dec 2024 ).
Yeh, C.H.; Chen, J.E. The Decision Mechanism Uses the Multiple-Tests Scheme to improve Test Yield in IC Testing. In Proceedings of the 2020 IEEE International Test Conference in Asia (ITC-Asia), Taipei, Taiwan, 23–25 September 2020, 88–93.
Yeh, C.H.; Chen, J.E. Recycling Test Methods to Improve Test Capacity and Increase Chip Shipments. IEEE Des. Test 2022, 40, 45–52.
Yeh, C.H.; Chen, J.E. Application of Three-Repetition Tests Scheme to Improve Integrated Circuits Test Quality to Near-Zero Defect. Sensors 2022, 22, 4158. https://doi.org/10.3390/s22114158.
Yeh, C.H.; Chen, J.E. Repeated Testing Applications for Improving the IC Test Quality to Achieve Zero Defect Product Requirements. Electron. Test, 2019, 35, 459–472.
Yeh, C.H.; Chen, J.E. Unbalanced-Tests to the Improvement of Yield and Quality. 2022, 10, 3032. https://www.mdpi.com/2079-9292/10/23/3032.
The IEEE International Roadmap for Devices and Systems Table; 2023 Available online: https://irds.ieee.org/editions/2023/20-roadmap-2023-edition (accessed on 4 Dec 2024 ).
Kirmse, M.; Petersohn, U.; Paffrath, E. Optimized Test Error Detection by Probabilistic Retest Recommendation Models. In Proceedings of the 2011 Asian Test Symposium, New Delhi, India, 20–23 November 2011, 317–322.
Jang, S. I.; Lee, J. H.; An Automated Retesting Approach for Wafer Probing Test Systems Using Neural Networks. In Proceedings of The World Congress on Engineering and Computer Science (WCECS 2011). San Francisco, USA, 1058-1063.
Jena, S. K.; Biswas S.; Deka, J. K. Maximizing Yield through Retesting of Rejected Circuits using Approximation Technique. In Proceedings of The 2020 IEEE REGION 10 CONFERENCE (TENCON 2020), Osaka, Japan, 182-187. https://doi: 10.1109/TENCON50793.2020.9293891.
Selg, H.; Jenihhin, M.; Ellervee, P. Wafer-Level Die Re-Test Success Prediction Using Machine Learning. In Proceedings of the 2020 IEEE Latin-American Test Symposium (LATS), Maceio, Brazil, 30 March–April 2020, 1–5.
Yeh, C.-H.; Chen, J.-E. Retesting Schemes That Improve Test Quality and Yield Using a Test Guardband. Eng 2023, 4, 3007-3025. https://doi.org/10.3390/eng4040169.
Mezouara, H.; Dlimi, L.; Salih, A.; Afechcar, M. Determination of the Optimal Guardbanding to Ensure Acceptable Risk Decision in the Declaration of Conformity. 2014.
Yu, K.; Qi, J. Evaluation and analysis of domestic ATE based on IC testing application. 2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), Nangjing, China, 2022, pp. 1-3. doi: 10.1109/ICSICT55466.2022.9963195.
Yan, H.; Feng, X.; Hu Y.; Tang, X. Research on Chip Test Method for Improving Test Quality. 2019 IEEE 2nd International Conference on Electronics and Communication Engineering (ICECE), Xi'an, China, 2019, pp. 226-229. doi: 10.1109/ICECE48499.2019.9058553.
Park, I.; Lee, D.; Chmelar, E.; McCluskey. E. J. Inconsistent Fail due to Limited Tester Timing Accuracy. 26th IEEE VLSI Test Symposium (vts 2008), San Diego, CA, USA, 2008, pp. 47-52. https://doi: 10.1109/VTS.2008.23.
Yeh, C.H.; Chen, J.E. Test yield and quality analysis models of chips. Journal of the Chinese Institute of Engineers. 2020, 43(3), 279–287. doi: 10.1080/02533839.2019.1708806.
Greenberg, B. S., & Stokes, S. L. Repetitive Testing in the Presence of inspection Errors. Technometrics, 37(1), 102–111. https://doi.org/10.1080/00401706.1995.10485893.
Horng, S.C.; Lin, S.Y.; Cheng, M.H.; Yang, F.Y.; Liu, C.H.; Lee, W.Y.; Tsai, C.H. Reducing the overkills and retests in wafer testing process. In Proceedings of the Advanced Semiconductor Manufacturing Conference and Workshop (IEEEI/SEMI 2003), Munich, Germany, 31 March–1 April 2003, 286–291.
Cheng, K. C. -C. et al.; Machine Learning-Based Detection Method for Wafer Test Induced Defects. in IEEE Transactions on Semiconductor Manufacturing, May 2021, vol. 34, no. 2, 161-167. https://doi: 10.1109/TSM.2021.3065405.

Comment 5:

When presenting the mathematical model in the form of formulas (1)-(8), I noticed a failure to keep them unambiguous, e.g., p. 4, point 125 .....; pp. 8-9, points 240-261, where there is no numbering.

Response 5:

Thank you for your valuable feedback and for highlighting this important point.

Lines 125 and 240–261 are examples based on previously derived formulas; therefore, we did not number the examples. We have added reference numbers to make it easier for readers to understand. The specific changes are as follows:

Case 1:

300 ppm

Case 2:

Thank you very much for your comments and suggestions. The comments and suggestions are valuable and very helpful for revising and improving our manuscript. We have revised our manuscript according to your comments and suggestions point by point (P8-P9).

Comment 6:

Duplication of explanations of the notation of some abbreviations both in the text of the work and in the case of descriptions of figures. For example, test yeld (Yt), pp. 1, 6, 10, or in the case of test quality (Yq), pp. 1, 6, 8, 16, or OTA on p. 8, 10, etc., respectively. ... Please check the entire paper in this regard and make appropriate corrections if possible.

Response 6:

Thank you for pointing this out. We have revised our manuscript according to your comments and suggestions point by point.

Comment 7:

Quoting too short sequences, e.g. page 5, points 142-143. Please check the whole article in this respect.

Response 7:

Thank you for noticing that. We have revised our manuscript based on your comments and suggestions. The revisions can be found on page 5. Thank you once again for your constructive feedback. The specific changes are as follows:

The primary aim of the testing is to verify whether the electrical characteristics of each die in the wafer align with the specifications stipulated by the design. A small red mark is added for identification if a product is deemed defective. Figure 3 shows the internal threshold test module of a general chip testing machine, which determines the quality of the chip by comparing signal speeds. The X parameter represents the chip delay time (DUT) within the circuit under test, and the ST (strobe) parameter denotes the signal time dispatched by the IC tester. The threshold voltage test sequence initially transmits the signal to the comparator of the chip IC tester (ATE). The ATE assesses the quality of the chip product according to the signal speed. If the test feedback signal is ST > X (X1 < X2), indicating that the ST time is later than the circuit under test, the DUT is classified as a good product (Pass). Conversely, if the test feedback signal shows ST < X (X1 > X2), indicating that the ST time is earlier than the DUT, the DUT is classified as a problematic product (Fail).

Comment 8:

In the paper, I observed a lack of explanation of some abbreviations, such as FET. Please check the entire article in this regard.

Response 8:

Thank you for noticing that. We have added the definition of FET (field-effect transistor) in section 2.2. To make it easier for readers to understand the paper, we have organized explanations of the abbreviations into a table of nomenclature. The specific changes are as follows:

Nomenclature:

TGB test guardband

DTM diverse test method

Y_m IC manufacturing yield (Y_m = G/N)

Y_t IC testing yield

DITM digital integrated circuit testing model

Y_q test quality

DUT the device under test

OTA overall time accuracy of ATE

N the semiconductor fabrication plant (fab) produces a certain quantity (N) of IC wafers

G Components meeting design specifications (DS)

B failing to meet DS are labeled Bad (B)

P wafers that pass the test (P, pass)

F wafers that fail (F, fail)

Type I (α) errors killing error

Type II (β) errors missing error

ATE Automatic test equipment

TS test specification

DS design specification

μ_M the average value of the delay time Chip of device under test (DUT)

σ_M the standard deviation of the delay time Chip of device under test (DUT)

X1 The X parameter represents the chip delay time (DUT) within the circuit under test (X1)

ST strobe parameter denotes the signal time dispatched by the IC tester (X2)

μ_T the average value of test the capability of the IC tester

σ_T the standard deviation of the test capability of the IC tester

TTM the traditional testing method

DL(defect level) indicating the fraction of faulty chips among those that pass the test

ppm parts per million (ppm)

FET field-effect transistor

Comment 9:

The final conclusions should be supported by the obtained research results. This is all the more incomprehensible, since the reviewed manuscript was prepared by the authors at a very high scientific level, especially in terms of the research performed (in-depth analysis, simulations, verification tests, comparative characterization, etc.), as well as in terms of in-depth analysis of the results obtained.

Response 9:

Thank you for your valuable feedback. We appreciate your suggestions for enhancing the conclusions of our paper. We have revised the conclusions on your feedback. The conclusions now include a more detailed explanation of the research background and the research question. The revisions can be found from page 18 to page 19. Thank you once again for your constructive feedback. The specific changes are as follows:

A relevant description has been added to the conclusion.

Furthermore, zero-defect high-quality products (Zero Defect Manufacturing, ZDM) are the ultimate goal pursued by the semiconductor industry. However, traditional chip testing must sacrifice the yield in exchange for a high yield. Considering aerospace and automotive electronics chips that require high reliability, the proposed DTM can extend the test time and change the test guard band (TGB). Retesting wafers that pass the test multiple times without sacrificing yield, the DTM reduces errors during the test process and adjusts the TGB to reduce the occurrence of killing and missing errors. Apart from enhancing the testing capabilities of the IC tester (ATE), through repeated testing, we searched for reliable products and obtained close to zero-defect products (10 ppm). Undoubtedly, DTM enhances the testing capabilities of IC testers and the quality of the tested products. Furthermore, considering the potential for future chip shortages and supply disruptions, DTM could help electronics manufacturers maintain increased productivity and stabilize the chip supply chain, resulting in a significant increase in company profit.

Thank you for your comments. We have gone through your comments carefully and tried our best to address them one by one. We hope the manuscript has been improved accordingly.

Sincerely yours,

Chung-Huang Yeh

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

The responses for point 1 and point 2 from previous review are only shown in the attached response file. The authors did not address the comments in the manuscript and did not make noticeable edits accordingly. The authors admit the disadvantages but there is nowhere in the manuscript pointing this out and explain why this model is significant regardless of the above disadvantages. The current responses are not convincing, not showing the significance of the proposed model. Please address all the response with either reasoning/real data in the manuscript. The current revision is not acceptable.

Response 1 and Response 2 are simply generally admitting the issues without any edits on the manuscript nor any additional evidence to support the significance of the model. How can the author prove the model is valid without any comparison with the field data?

Author Response

Dear Sir,

Please find, in the submission section of the authors, our final response to the comments received from the two reviewers to

" Application of Diverse Testing to Improve Integrated Circuit Test Yield and Quality."

Sincerely yours,

Yeh C-H,

(On behalf of the authors of the manuscript)

COMMENTS FOR THE AUTHOR:

Responses to Reviewers Comments

The responses to the individual comments of two reviewers are detailed below.

(Note: Reviewer comments are in italic, authors' responses are in normal text).

Response to Anonymous Referee #1:
Reviewer #1: Comments to the Author

Comments and Suggestions for Authors

Comments and Suggestions for Authors

Comment1:

Response 1:

Thank you for pointing this out. I agree with the reviewer’s comment. The extra time incurred in retesting is indeed the main disadvantage of the DTM method. We have added section 4.2 on your feedback. The revisions can be found on pages 15-16. Thank you once again for your constructive feedback. The specific changes are as follows:

4.2 Optimization of iteration numbers (best estimate of Y_t)

According to the ITRS 2015 [5], testing costs account for approximately 5% of the total production cost. For example, if the manufacturing cost of a wafer is $20, the testing cost would be $1. The international chip pricing strategy typically follows the 8:20 pricing model [28]; for example, if the chip cost is $8, the chip price would be $20. Assuming that Company “B” produces 10 million 1.0 GHz (1000 ps) wafers annually, with a unit price of $25 per wafer, the cost of each wafer is $10. The estimated cost of testing this batch of wafer products is approximately $5 million (10,000,000 × 10 × 5% = $5,000,000). By implementing a new testing method (DTM), which increases the test yield by 1% per test, Company “B” can sell an additional one hundred thousand chips annually(10,000,000 × 1% = 100,000), generating an additional profit of $2.5 million (10,000,000 × 25 × 1% = $2,500,000). If the test yield increases to 2% (10,000,000 × 25 × 2% = $5,000,000), the cost of product testing can be fully covered. However, if chips are retested excessively in pursuit of higher yields, the cost of testing may exceed the profit gained from the retesting process. This increases testing time and reduces company profitability. Therefore, test engineers must optimize the number of test iterations to balance costs and maximize the company’s profits effectively. Assume that Company “B” produces a batch of 10 million 1.0 GHz (1000 ps) wafers, each priced at $25, with circuit characteristic parameters modeled as X~N (x; μ_M = 800 ps, σ_M = 120 ps). According to the estimation equation provided, a manufacturing yield of 95% is achieved. If the wafers are tested using traditional methods (single test) with a tester selected at OTA = 150 ps and the DL set at 300 ppm, a test yield of 77.72% is obtained, as shown in Table 2. To meet the manufacturer’s requirements for high profits and yield, employing the DTM test method (Yt = PP + PFP + FPP) achieved a test yield of 86.3%, representing an increase of 9.1% compared with the traditional method (86.3% − 77.72% = 9.1%). As a result, Company “B” can sell an additional 910,000 wafers annually (10,000,000 × 9.1% = 910,000), generating an extra annual revenue of $22.75 million (10,000,000 × 9.1%× 25 = $22.75 million). However, owing to extended lease times and the cost of repeated tests, the net additional revenue after deductions was $7.75 million ($22.75 million − $5 million − $5 million − $5 million = $7.75 million). To further improve yield, we apply an additional retest (one iteration, denoted as DTM₊₁) to the same batch of wafer products using a test specification of μ_T = 941 ps. This achieves a test yield of 87.1%, representing a 0.8% increase over DTM (87.1% − 86.3% = 0.8%). That is, each additional test iteration improves the yield by 0.8%. However, if the number of retests is increased by two iterations (denoted as DTM₊₂), further considerations is required. Using the test specification μ_T = 942 ps, the DTM₊₂ test yield is estimated to be 0.2% higher than the DTM₊₁ yield (87.3% − 87.1% = 0.2%).

From the above data analysis, the profit generated by additional DTM retests is insufficient to offset the cost of a single round of product testing unless the yield increases by at least 2%. That is, further increasing the number of DTM retests not only fails to enhance the company’s profitability but also leads reduces profits. Additionally, the experimental observations indicate that yield improvement is directly proportional to profit growth. However, under the same quality principles, as the number of repeated tests (iterations) increases, the rate of yield improvement gradually diminishes, with no significant large-scale gains. Therefore, when engineers plan the retesting process, they must carefully balance the time, labor, and material costs to maximize the company’s profits. Additionally, DTM results in a 9.1% increase in Yt compared with TTM (86.3% − 77.2% = 9.1%). Retesting the DUT not only reduces the likelihood of killing errors but also enhances the performance of the IC tester by adjusting the TGB, thereby improving the test yield under specific test quality conditions. According to the above results, DTM effectively enhances the testing machine capabilities and maximizes the economic benefits.

Table 2. Estimated test results for different test methods.

DL		ppm	10	100	300
OTA = σ_T × 3 = 50 × 3		ps	150	150	150
	Y_t	%	62.1	72	77.2
	TS (μ_T)	ps	840	876	897
	Y_t	%	78.2	83.6	86.3
	TS (μ_T)	ps	897	922	936
Yield↑	Improve Y_t	%	16.1	11.6	9.1
OTA = σ_T × 3 = 40 × 3		ps	120	120	120
	Y_t	%	72.6	79.7	83
	TS (μ_T)	ps	876	905	921
	Y_t	%	83.5	87.3	89
	TS (μ_T)	ps	920	940	951
Yield↑	Improve Y_t	%	10.9	7.6	6
OTA = σ_T × 3 = 30 × 3		ps	90	90	90
	Y_t	%	81.3	85.7	87.9
	TS (μ_T)	ps	910	932	945
	Y_t	%	87.7	90.2	91.4
	TS (μ_T)	ps	941	957	966
Yield↑	Improve Y_t	%	6.4	4.5	3.5

Thank you for your comments. We have gone through your comments carefully and tried our best to address them one by one. We hope the manuscript has been improved accordingly.

Sincerely yours,

Chung-Huang Yeh

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

The authors have taken my comments and recommendations into account. I think that the article can be reviewed by the editor for acceptance for publication.

Author Response

Thank you very much, your concerns have substantially improved our manuscript and we are very grateful for your time and your valuable input.

Round 3

Reviewer 1 Report

Comments and Suggestions for Authors

Point 1:

Thanks for adding section 4.2, the explanation improves a lot by adding calculation from reference. However, the verification section of justify the model's significance is still missing. Whether this model has been verified by the field data (not in a way of plugging in reference numbers, and calculating the yield increase, but comparing the simulation results and the field measurement) , or this model is only an theoretical model is not clear. Please at lease add a few sentence to clarify.

Author Response

Dear Sir,

Please find, in the submission section of the authors, our final response to the comments received from the two reviewers to

" Application of Diverse Testing to Improve Integrated Circuit Test Yield and Quality."

Sincerely yours,

Yeh C-H,

(On behalf of the authors of the manuscript)

COMMENTS FOR THE AUTHOR:

Responses to Reviewers Comments

The responses to the individual comments of two reviewers are detailed below.

(Note: Reviewer comments are in italic, authors' responses are in normal text).

Response to Anonymous Referee #1:
Reviewer #1: Comments to the Author

Comment1:

Response 1:

Thank you for pointing this out. The revisions can be found on pages 18. Thank you once again for your constructive feedback. The specific changes are as follows:

Chips intended for automotive, aerospace, or medical electronics demand high-reliability standards owing to safety imperatives. Consequently, the testing procedure entails greater time and expense. However, discerning high-quality products from the vast array of manufactured chips poses a significant issue and challenge. This selection process not only tests the capabilities and expertise of test engineers but also presents a formidable challenge to the capabilities and methodologies of ATE testers. Consider a scenario in which a fab produces a batch of automotive chips, with a stringent quality requirement of 10 ppm. As depicted in Figure 11 and Table 3, the implementation of DTM can significantly enhance the test yield of wafers produced in 2034 (3.7 GHz) to 22.2% (70.2% (DTM) − 48% (TTM) = 22.2%). Overall, repetitive testing enhances chip product quality, test yield, and the performance of IC testers, leading to substantial improvements in test results. Incorporating additional testing steps and mechanisms reduces the number of defective chips and increases product output and enhances the overall profitability and reputation of the company. At this stage, this experiment only performed computer simulation estimation. From the analysis of the simulation results, this method has an excellent effect on improving the test yield and quality by saving manpower and reducing test costs. We believe that this set of theories and methods will be applied in the actual VLSI test environment shortly.

Thank you for your comments. We have gone through your comments carefully and tried our best to address them one by one. We hope the manuscript has been improved accordingly.

Sincerely yours,

Chung-Huang Yeh

Author Response File: Author Response.pdf

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Application of Diverse Testing to Improve Integrated Circuit Test Yield and Quality

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