# Pure Sinusoidal Output Single-Phase Current-Source Inverter with Minimized Switching Losses and Reduced Output Filter Size

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## Abstract

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## 1. Introduction

- No high-switching frequency modulation is used for current inversion processing.The proposed method applies two times fundamental frequency of the output for controlling the current direction by switching modules in order to generate staircase current waveform. In other words, without any high-switching frequency modulation. Therefore, the switching losses in the current inversion process or in the H-bridge part is extremely low. Nevertheless, the high-switching frequency modulation is still needed for generating constant current and linear current sources.
- No dedicated linear amplifier is used for generating pure sinusoidal output.The amount of energy for constructing pure sinusoidal output current is still dominantly supplied by constant current sources through a staircase current waveform. The linear amplifier produces only a very small amount of amperage to compensate and reshape the staircase current waveform into pure sinusoidal. Hence, the power losses wasted by linear amplifier circuit can be minimized.
- No large output L-C filter utilization.The size of the utilized output L-C filter affects the power density [27]. Due to linear amplifier utilization, the output total harmonic distortion (THD) is always being kept low in order to comply with IEEE-1547, IEEE-929, and EN-61000-3-2 standards [26]. Therefore, the proposed system only needs small output capacitor that is sufficient to eliminate the current ripples. As a result, the power quality and the power density of the proposed system are slightly improved.
- No isolated multiple power sources utilization.Figure 1 describes the proposed MCSI concept employs several isolated current sources. Moreover, the research finding by author [1] also points towards that the proposed concept is consistent with literature. However, the implementation is totally different. The depicted current sources actually can be represented by only using one power source. The detailed implementation will be elaborated in the next section.

## 2. Operation Principle, Circuit Configuration, Switching Strategy and Control System

#### 2.1. Operation Principle

_{LEVEL}is the number of levels. The number of constant current sources that equals to the number of switching modules is written as:

#### 2.2. Direct Current (DC) Module

_{L}. In order to reduce the L size, a high-switching frequency modulation is applied for Q1. D1 is used to keep continuous conduction of the chopper part by circulating the load current. In order to maintain I

_{L}stability, a close-loop controller is applied for this circuit. The switching module part directs I

_{L}whether to deliver it to the load or circulate back to the source. When Q2 is turned off, I

_{L}flows to the load before flowing back to the source through D1. On the other hand, when Q2 is turned on, I

_{L}flows directly back to the source so that no current supplies the load. The switching module part is working based on the comparison between the absolute value of the sinusoidal reference with the determined current limit of each DCM.

#### 2.3. Circuit Configuration

_{O}supplies the load so that giving the load a potential difference of v

_{O}. In order to keep the output voltage stability, i

_{O}must be maintained at:

_{O}is sinusoidal waveform, it has a peak or maximum value that equals:

_{m}determines the required DC link current. Because the I

_{m}robustness is the key of v

_{O}stability, therefore the current generated by each current source is limited to:

_{CS}is limited to I

_{m}/6 amperes. Five DCMs are set to generate constant current of I

_{m}/6 amperes, meanwhile the linear current generator is programmed to generate linear current from 0 to I

_{m}/6 amperes.

_{O}is added in order to eliminate the ripple current that accumulated from each current source as a consequence of using the buck chopper circuit. In order to reverse the current polarity of the load, the operation of Q

_{A}is paired with Q

_{D}and the operation of Q

_{B}is paired with Q

_{C}. When a zero-cross of the sinusoidal reference is detected, prior to changing the polarity, switches Q

_{A}–Q

_{D}are turned on for a few microseconds to make sure the DC current does not lose its current path. This is well-known as overlap time that always required by the CSI system to prevent any damages.

#### 2.4. Staircase Current Waveform Generation

_{CS}is the current generated by the corresponding current source of the stage and D is the duty cycle that equals to the turn-on period divided by the total period-length. In Figure 5, θ1 and θ2 can be found by:

_{STAIRCASE}) waveform can be written as:

#### 2.5. Linear Current Waveform Generation

_{LINEAR}) waveform can be estimated as:

#### 2.5.1. Class-A Amplifier-Based Linear Current Generator

#### 2.5.2. Class-D Amplifier-Based Linear Current Generator

#### 2.6. Control System

_{O}is subtracted with the voltage reference V

_{REF}in order to identify an error. This error is then amplified with proportional-integral (P-I) controller to generate the current reference I

_{m}. By using Equation (6), the current limit I

_{CS}of each current source is determined. In order to control inductor current of DCM I

_{L}, the output of current P-I controller is modulated by high frequency sawtooth carrier waveform. In the output frequency control section, the phase output of the PLL drives the sinusoidal look-up table (LUT) to generate sinusoidal waveform reference for H-bridge polarity inversion, staircase current generator, and linear current generator. H-bridge changes its polarity when the zero-crossing detector (ZCD) detects a zero-cross of sinusoidal reference. During overlap time, all switches of H-bridge are turned on to provide free-wheeling current path. The staircase and linear generators have already been explained in the previous section.

#### 2.7. Power Losses’ Theoretical Analysis

_{L}, the load R

_{L}requires a current of I

_{m}. If the parasitic resistance of each current source is assumed equal as R

_{DCM}, then each current source will generate the current that equals Equation (6).

_{d}is the DC link voltage, f

_{S}is the switching frequency, I

_{d}is the passing current through the device, t

_{r}is the rise time of the switching transition, t

_{f}is the fall time of the switching transition, C

_{OSS}is the device output capacitance, Q

_{g}is the gate charge, and V

_{g}is the gate voltage. If all calculations of the power losses are plotted into graphics and normalized to the 3-level CSI, the results are shown in Figure 11a–c.

## 3. Simulation Results

_{1}), 25 kHz (F

_{2}), 50 kHz (F

_{3}), 75 kHz (F

_{4}), and 100 kHz (F

_{5}). While the various output filter capacitor used in this simulation were 680 nF (which is denoted as C

_{1}), 2.2 µF (C

_{2}), 6.8 µF (C

_{3}), 22 µF (C

_{4}), and 68 µF (C

_{5}).

## 4. Experimental Results

## 5. Conclusions

## Author Contributions

## Funding

## Acknowledgments

## Conflicts of Interest

## References

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**Figure 11.**Theoretical MCSI power losses correspond to the number of levels. All data is normalized to 3-level CSI: (

**a**) conduction losses; (

**b**) switching losses; (

**c**) gate charge losses.

**Figure 12.**The proposed 9-level hybrid MCSI simulation results: (

**a**) operation principle; (

**b**) fast Fourier transform analysis of the unfiltered load current and the load voltage.

**Figure 13.**The conventional 9-level MCSI performances correspond to the various switching frequencies and output filter capacitors: (

**a**) power efficiency; (

**b**) voltage total harmonic distortion (THD-V).

**Figure 14.**The proposed 9-level MCSI with class-A linear current compensator performances correspond to the various switching frequencies and output filter capacitors: (

**a**) power efficiency; (

**b**) voltage total harmonic distortion (THD-V).

**Figure 15.**The proposed 9-level MCSI with class-D linear current compensator performances correspond to the various switching frequencies and output filter capacitors: (

**a**) power efficiency; (

**b**) voltage total harmonic distortion (THD-V).

**Figure 17.**Nine-level hybrid MCSI with class-D linear compensator experimental results: (

**a**) output waveforms; (

**b**) fast Fourier transform analysis of the unfiltered load current and the load voltage.

**Figure 18.**Nine-level hybrid MCSI with class-A linear compensator experimental results: (

**a**) output waveforms; (

**b**) fast Fourier transform analysis of the unfiltered load current and the load voltage.

**Figure 19.**Performance comparison between simulation vs experimental results corresponds to the number of levels: (

**a**) power efficiency; (

**b**) total harmonic distortion of the load voltage.

Q1 | Q2 | Output |
---|---|---|

0 | X ^{1} | 0 |

Switching | 0 | I_{L} |

X ^{1} | 1 | 0 |

^{1}X = do not care.

Parameter | Value (Unit) |
---|---|

Power source DC voltage | 160 V |

DCM Inductor | 560 µH/90 mΩ |

Chopper Carrier Frequency | 50 kHz |

Output Filter Capacitor | 6.8 µH/1 mΩ |

Load | 10 Ω/1 mH |

Output AC Voltage/Line Freq | 100 V/60 Hz |

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**MDPI and ACS Style**

Priandana, E.R.; Noguchi, T. Pure Sinusoidal Output Single-Phase Current-Source Inverter with Minimized Switching Losses and Reduced Output Filter Size. *Electronics* **2019**, *8*, 1556.
https://doi.org/10.3390/electronics8121556

**AMA Style**

Priandana ER, Noguchi T. Pure Sinusoidal Output Single-Phase Current-Source Inverter with Minimized Switching Losses and Reduced Output Filter Size. *Electronics*. 2019; 8(12):1556.
https://doi.org/10.3390/electronics8121556

**Chicago/Turabian Style**

Priandana, Eka Rakhman, and Toshihiko Noguchi. 2019. "Pure Sinusoidal Output Single-Phase Current-Source Inverter with Minimized Switching Losses and Reduced Output Filter Size" *Electronics* 8, no. 12: 1556.
https://doi.org/10.3390/electronics8121556