Experimental Study of a Two-Stage Interleaved Boost Converter with Litz Wire Inductor and Zero-Current Switching for Photovoltaic Systems

Abstract

Power converters are essential for solar energy systems but achieving over 96% efficiency at 1 kW and 300 kHz with compact magnetic and EMC compliance remains challenging for high-power-density PV applications. This study presents the design, modeling, and experimental validation of a 1 kW two-phase interleaved boost converter operating from 12 V input to 48 V/20 A output, featuring a single EE32 Litz-wound coupled-core inductor with coupling coefficient k = −0.475 that reduces per-phase current ripple to just 120 mA (0.6% relative) at full load, a load-selective active zero-current switching (ZCS) circuit activated above 5 A threshold via DCR sensing to minimize switching losses without light-load penalties, and digital peak-current control with 2P2Z compensator implemented on an XMC4200 microcontroller, ensuring robust stability. Experimental results demonstrate peak efficiency of 98.6% at approximately 190 W load, full-load efficiency of approximately 96% with total losses limited to 40 W dominated by conduction rather than switching, thermal rise below 80 °C on key components, voltage regulation with less than 1% deviation down to 2 A minimum load, and full compliance with electromagnetic compatibility standards, including EN 55014-1/2 and EN 61000-4-2 ESD testing. The novel integration of selective ZCS, single-core magnetic, and high-frequency operation outperforms prior interleaved boost converters, which typically achieve 94–97% peak efficiency at lower switching frequencies of 20–100 kHz using multiple inductors or complex always-active resonant networks, making this solution particularly suitable for compact photovoltaic micro-converters, electric vehicles, and industrial power supplies requiring high efficiency, reliability, and regulatory compliance.

1. Introduction

A primary concern in the study of solar system integration pertains to the spatial demands of the solar control system itself. Despite the presence of wiring management and storage mechanisms, the performance of the converter is evaluated based on its resilience and dependability. This approach aligns with market demands that emphasize safety and efficiency standards to ensure end-user security [1,2]. As is well known, transformers come in different types, which can be divided into DC converters [3] and AC converters [4]. The converters rating plays a crucial role in the operational performance of power systems, especially photovoltaic (PV) systems; the higher the converter rating is, the better the operational performance is, and the higher the resulting output is [5].

1.1. Current Challenges and Research Gap in the Existing Literature

Digital power supplies have found extensive use across a broad spectrum of applications, thereby demonstrating their versatility and widespread adoption. Consequently, the significance of high-power density and low-noise power sources cannot be overstated in ensuring optimal performance and efficiency [6]. Power converters play a crucial role in solar energy systems and a wide range of electrical applications. A variety of converter types are employed in this regard, including AC-DC [7], DC-AC [8], AC-AC [9], and DC-DC converters [10]. Furthermore, multilevel converter topologies offer significant advantages in power electronics, including higher voltage levels, reduced voltage stress on switching devices, an improved power factor, lower power losses, and smaller filter requirements [11,12]. Consequently, a plethora of advancements and enhancements have been proposed for this specific topology, garnering interest from both the industrial and academic sectors. This exemplifies the continuous evolution and refinement of digital power supplies to address the shifting requirements of diverse industries and research domains. The topology of the DC-DC interleaved converter technique has found wide application in scenarios that necessitate high-density power and thermal distribution. This technique has been particularly successful in compact high-power systems, including electric vehicle charging units, power walls, central processing unit power supplies, and 5G network servers, as outlined in [13]. Article [14] proposes a new design for a DC-DC converter specifically aimed at renewable energy applications (e.g., solar power or other low-voltage sources). In the proposed design, interference and a switching capacitor cell (dual-capacitor multiplier) are combined to produce a high step-up voltage gain without the need for a transformer or long duty cycle. A key advantage of this topology is that the input current becomes essentially ripple-free, reducing conduction losses and electromagnetic interference (EMI). Also, due to the lower output amplitude requirements, the transformer can be built with smaller components (and therefore cheaper and more compact). Another advantage highlighted is that the voltage stress on the switching elements (switches, diodes) remains low, allowing the use of low-resistance switches; this reduces losses and increases efficiency. In general, simulation results were presented that validate the performance of the proposed converter, showing that the designed architecture achieves high profitability, low stress on components, reduced size and cost, and suitable input current characteristics, making this proposed solution a promising solution for energy conversion from renewable energy. The completed article in [15] presents a new DC-DC converter topology designed for renewable energy systems and electric vehicles that need to efficiently step up a relatively low input voltage. In this proposed design, a dual-input architecture (i.e., the converter can accept two different DC sources), a voltage multiplier cell/diode multiplier, and a capacitor are combined to achieve high-voltage gain while using fewer semiconductor switches. This proposed design simplifies the number of switches required in the circuit, reduces cost and complexity, and helps to reduce voltage stress on switching devices. To demonstrate the feasibility of the proposed design, the authors developed a real-world hardware prototype and validated it in a “hardware-in-the-loop” setup using a real-time simulator (OPAL-RT OP5700), confirming that the converter can deliver high gain with good efficiency—approximately 97.09% under tested duty cycle and power rating. The authors believe that this designed topology (dual input, high gain, low number of switches) is particularly suitable for applications such as hybrid renewable energy systems or electric vehicles, where multiple power sources (e.g., battery + solar) may be available and where high voltage enhancement, high efficiency, and minimal stress on components are required.

Additionally, the reduction in power losses in interleaved converters on their magnetic core and electronic power semiconductor can be significantly minimized [16].

Interleaved DC-DC converters have been shown to enhance efficiencies in PV systems by increasing voltage gain, reducing current stress, improving soft switching capabilities, and minimizing energy losses. These converters employ coupled inductors and voltage multiplier cells to achieve a substantial increase in voltage without necessitating high duty cycles [17,18]. The interleaved structure has been demonstrated to reduce current stress, resulting in a 16% increase in voltage gain compared to other topologies [19]. Moreover, it enhances efficiency by reducing conduction losses and elevating overall system performance [20]. The efficacy of interleaved DC-DC converters in optimizing power extraction from PV arrays is attributable to their adept management of voltage gain, current stress, and switching conditions [21]. In [22], the authors address the challenge of providing “pulsation loads”—loads that require rapid bursts of high power (peaking in fractions of a second) but with low average power—which are common in systems such as ship rectifiers or hybrid power sources. Under these pulsed load conditions, conventional rectifier and capacitor systems struggle to perform; large capacitors are usually needed to compensate for instantaneous power spikes, resulting in bulky and expensive designs. To solve this problem, the authors propose a bidirectional DC-DC converter, parallel and interleaved, that acts as a power pulse buffer (PPB). The designed control strategy combines model predictive control (MPC) with a Weinberger monitor whose gains are adaptively adjusted in real time using a gradient regression algorithm (based on the consistency of gradient trends), enabling the estimation and compensation of perturbations (such as parasitic coefficient effects or voltage ripple) that degrade accuracy. By analyzing the pulsed load current into intermediate and dynamic (pulsating) components, the PPB is controlled so that its input current follows the pulsating component, while a buffer capacitor absorbs the ripple energy. Meanwhile, the main power supply handles the intermediate current requirements. This separation enables the system to provide stable DC output and smooth three-phase AC under pulsed load while significantly reducing DC voltage ripple and AC current distortion. Simulations and experimental verification (according to the article) show that this integrated control and converter topology can effectively suppress excesses, improve current tracking accuracy, and maintain stable operation even under challenging, rapidly changing pulsed loads—without the need for massive capacitors and avoiding excessive strain on switching devices. In [23], the authors present a non-isolated, nested boost transformer topology that combines magnetic coupling (coupled inductors/transformer-like coils) with voltage multiplier cells to achieve a high boost from a low input voltage to a much higher output voltage—without the need for extreme duty cycles or bulky isolation transformers. Its design uses a transformer with two primary windings (connected to ensure equal impedance) to distribute the current evenly, along with several secondary windings and an inductor coupled to three windings. These transformers boost the output voltage and help stabilize the voltage across the switches and diodes, keeping these voltages well below the output voltage. One of the most important advantages of this system is its ease of installation and flexibility; the output voltage gain can be modified by changing the ratio of the magnetic windings, by adding more secondary windings, or by introducing additional voltage multiplier cells, which allows designers options to balance the gain, number of components, and efficiency. A 1 kW prototype (48 V input → 400 V output, with 25 kHz switching) was built and a measured efficiency of approximately 95.12% was demonstrated under full load conditions. In general, this transformer topology provides a compelling solution for high-power and high-step-up DC applications (e.g., PV solar power systems, battery-powered DC inverters, and small DC buses) where galvanized insulation is not required. It provides high voltage step-up, balanced phase currents, low device stress, and high efficiency while keeping the design relatively compact and scalable. The article [24] explores how to improve the stability of small DC networks when they provide “constant power loads” (CPLs)—loads whose increasing negative impedance tends to destabilize conventional DC transformers. The authors propose using a two-phase interferometric boost converter (IBC) regulated by a digital controller based on the RST method (i.e., using carefully selected R, S, and T polynomials) instead of conventional PI controllers or slide-mode controllers. This RST-based control is designed by electrode placement and sensitivity shaping: the control parameters are set so that the closed-loop system keeps its electrodes in fixed positions (even under the destabilizing influence of CPLs), ensuring strong disturbance rejection, good robustness to parameter changes, and a rapid response to transient states. Through simulation studies, it has been shown that under sudden changes in load power (CPL variation), load type (from CPL to resistive), or input voltage, the IBC controller equipped with the RST controller maintains the DC bus voltage close to the reference value (with an overshoot of less than ±2%), and recovers its stability within tens of milliseconds. A balanced distribution of current between overlapping phases and good curbing of current ripple were also observed, which helps to reduce stress on components and improves efficiency under dynamic operating conditions. In [25], a strategy was presented to improve energy extraction from PV arrays under partial shading—a situation in which some PV modules are shaded, resulting in the creation of multiple local peaks in the power-voltage (P-V) curve and complicating conventional maximum power point tracking (MPPT).To address this problem, it was proposed to replace the traditional single-switch scheme (class booster switch or CBC) with multiple parallel branches: each PV string is connected to its own Interconnected Boost Switch (IBS), and each IBS is controlled independently using a fuzzy logic controller-based MPPT. This design allows each string of PV cells to operate at its optimal point, enabling the system not only to find a single global maximum power point (GMPP), but also to capture the maximum possible power from all the photovoltaic strings—which may be under different irradiance and shading conditions. Compared to the traditional CBC approach, the proposed fuzzy logic IBC and MPPT system provides higher total output power, better efficiency, more stable DC link voltage, less ripple and harmonic distortion, and improved power quality—both under uniform irradiation and under partial shading conditions. Work [26] proposes a new design for a bidirectional DC/DC converter, in which the number of parallel sub-converters (“multiplicity”) can be dynamically changed according to the operating duty cycle-rather than being fixed as in conventional multi-converter systems. The motivation behind this design is that the amount of current ripple on a DC bus depends not only on the number of parallel channels used, but also on the voltage ratio; as a result, a fixed multiplicity design does not guarantee minimal ripple under all conditions. Through this work, analytical expressions were deduced that relate the total current ripple to the duty cycle and the number of parallel branches, and it was shown that for each range of duty cycles, there is an optimal number of parallel branch transformers that reduce the ripple. Accordingly, a control method was designed that actively monitors the duty cycle, turning on/off the parallel transformer “branches” to maintain minimal ripple—complemented by a current compensation loop to maintain a balanced current distribution between the channels. The idea was validated through simulations and experiments on the prototype: the results showed that the “multi-variable crossover bidirectional converter” significantly reduces DC carrier current ripple compared to a fixed parallel converter, without increasing the switching frequency (which would lead to a deterioration in efficiency).

In general, the interleaving operation of a multiphase converter has been shown to result in a reduction of peak ripple magnitude and enhanced control in the context of current control mode. For an N-phase interleaved converter, the peak current ripple magnitude is reduced by a factor of N, thereby extending the system bandwidth by N times [27].

In recent years, research on power conversion for solar and storage systems has increasingly focused on the adoption of wide-band gap (WBG) devices such as SiC and GaN. These devices enable higher switching frequencies, reduced conduction losses, and improved thermal behavior, making them ideal for compact, high-efficiency designs [28]. Concurrently, state-of-the-art digital control methodologies, encompassing generalized and finite-control-set MPC, have been implemented to optimize dynamic performance, current balancing, and fault tolerance in interleaved and multilevel converter systems [29,30]. Furthermore, the integration of smart control algorithms with digital microcontrollers affords greater flexibility, thereby enabling real-time monitoring, parameter tuning, and intelligent fault detection in renewable energy applications [31]. The integration of these innovations has the potential to enhance the efficiency of next-generation solar energy conversion systems, while also reducing electromagnetic interference and improving reliability.

The proposed study of the two phase’s interleaved boost DC-DC device structure illustrates the operation mode of the converter under current control mode. The converter incorporates a novel active zero-current switching (ZCS) circuit that combines the advantages of a Z-source network and interleaved parallel structure [32,33]. This configuration facilitates high-voltage gain, low-current stress on switches and automatic current sharing between inductors. Similarly, the interleaved boost converter with a single magnetic core contributes to common-mode noise reduction without the necessity of electromagnetic interference (EMI) filters, thereby enhancing power density [34]. In [35], the authors studied common problems when using conventional “strict switching” buck converters to convert DC power from renewable sources (such as photovoltaic panels, fuel cells, and batteries). It has been noted that these transformers often suffer from high conversion losses, large electromagnetic interference, large stress on the transforming elements, and reverse recovery losses in free diodes. To overcome these problems, a modified buck converter topology was proposed that included a “soft switching cell”: using passive components (inductors, capacitors, diodes) alongside active switches (such as MOSFETs), the converter could achieve zero-voltage switching (ZVS)—meaning that the MOSFETs switch when the voltage across them is close to zero. This soft-switching design significantly reduces switching losses, active switching stress, and EMI emissions. It also mitigates reverse recovery losses of free diodes by using a passive soft-switching cell consisting of a capacitor and two diodes. The design is validated through simulation (for solar, fuel cell, or battery sources), showing that a soft-switched buck converter is more efficient, has less electromagnetic noise and can be more compact (smaller size and less heat dissipation) compared to a conventional hard-switched buck converter. In summary, the proposed active ZCS control demonstrates significant performance improvements, rendering it suitable for a variety of renewable energy applications [36]. A series of conducted studies have been published that examine bidirectional converters with multi-mode control strategies. These control strategies include variable frequency control and phase-shift control. The objective of these studies is to optimize the performance of battery energy storage systems. The goal is to achieve zero-voltage switching and increased current rating [37]. In [38], the author compared a conventional Class E inverter-operating under ZVS-with several “improved” variants (specifically, second and third harmonic versions: Class EF2 inverter, Class EF3/Class E/F3 inverter, and the so-called “flat” Class E) under the same design constraints. By scanning parameters such as the switching frequency, duty cycle, capacitance ratio, and load impedance, they measure key performance metrics: output power capacity, efficiency, peak switching voltage and current, resonant capacitor stresses, and peak current/voltage in auxiliary networks. The results of the work show that some improved versions (particularly the EF₂ and E/F₃ in a specific configuration) can achieve much higher efficiency—around 90%—compared to around 80% for the conventional E-Class under optimal conditions. At the same time, these improved transformers offer 20–30% lower peak voltage and current (for a suitable capacity ratio), reducing stress on the transformers, which helps improve reliability and possibly size. Therefore, this work claims that enhanced harmonic (EF and E/F) inverters provide a more efficient and less stress-intensive alternative to the classic E-class—especially when the design parameters are carefully chosen—making them attractive for applications requiring high-frequency inverters with small size and good efficiency. In [39], the authors present a control strategy for a three-level active dual-bridge DC-DC converter that combines a three-level intermediate clamp topology with a sophisticated MPC method to achieve ZVS for all semiconductor switches and fast dynamic response under varying load or input conditions. The different connection modes of the three-level converter under single-phase shift modulation were analyzed, state-space equations were derived separately for each mode, and then a predictive control algorithm was constructed; at each switching period, the controller evaluates the cost function (measuring the error between the expected output voltage and its reference) and adjusts the phase-shift control variable accordingly to minimize that cost and enforce smooth switching. Simulations show that, compared with traditional control strategies (e.g., dual closed loop with PI), the MPC approach can greatly accelerate startup, e.g., reaching a stable output voltage in about 57.5 ms instead of about 224 ms, and recover more quickly from sudden load changes, all while maintaining ZVS and avoiding overshoot. In [40], the authors propose a novel DC-DC converter topology designed for PV power systems: a three-level QZ-source converter whose output stage uses a double cell arranged in a three-level structure. Unlike many high-gain converters, this design uses only one switch and avoids auxiliary switches, thus simplifying the circuit and control. By combining a QZ source network with a three-level output multiplier, the converter achieves high gain for high voltage (in the prototype: from 36 V input to about 720 V output) without the need for a transformer. Thanks to its design, the inverter also enjoys smooth switching conditions, reducing conduction, switching and ohmic losses, resulting in high efficiency (around 97.6% at full load in the 200 W prototypes) and reduced EMI compared to more complex topologies. Additional advantages: The converter has a common ground between the inputs and outputs (which helps reduce noise), low input current ripple, limited stress on the active and passive components (since the voltage/current stresses remain much lower than the output voltage), and a simple PWM-controlled linear structure—making it perfectly suited for PV power applications that require high-gain DC-DC conversion. In [41], the authors propose a new version of the Quadratic Boost Converter (QBC), specifically designed for renewable energy applications, such as PV power systems, electric vehicle charging stations, and micro-DC grids. The proposed design achieves high voltage gain (significantly raising the low input voltage to a much higher output voltage) by using a coupled inductor and active stabilization circuit, allowing the converter to operate without the need for excessive operating cycles-a common drawback of high-gain designs. Most importantly, the converter employs seamless switching technology: the leakage inductance of the coupled inductor ensures ZVS for the power switches when on, while the diodes activate at zero current (ZCS) when off. This seamless switching system significantly reduces switching losses and stress on semiconductor devices, thus improving the converter’s efficiency and lifespan. A prototype device with a power of 250 W was built and tested; the experimental results confirmed that the converter achieves the promised high gain and high efficiency (peak efficiency reaches approximately 97%) under practical operating conditions. The design also features relatively low voltage across switches; continuous operation (suitable for stable input sources such as photovoltaic cells); low electromagnetic interference; and a simpler, more compact, and non-isolated structure—all of which make it attractive for renewable energy conversion systems.

1.2. Research Objectives and Main Contributions

In this paper, we present the investigation of a fully digital integrated interleaving DC-DC controller based on an Infineon XMC 4200 microcontroller unit (MCU) solution, from current control mode and compensators to the internal current slope generator. The integration of a 300 kHz pulse-width modulation (PWM) working frequency generator unit with interrupt manipulation in conjunction with the analog-to-digital converter (ADC) current prescheduled sampling was conducted. The impact of parasitic inductances (e.g., bond wires, package leads, and long metal traces) on power delivery was analyzed via signal-to-noise ratio measurements for the analog control circuitry and radio frequency propagation from power nodes. In addition, the utilization of high switching PWM has been employed to minimize losses in the inductor, copper, and magnetic core. This approach has been found to offer a substantial enhancement in packing density. The implementation of a specialized single ferrite EE32 core Litz-wire H-class insulation coupled inductor has been adopted in accordance with the IEC 60085 standard (Electrical insulation–Thermal evaluation and designation. International Electrotechnical Commission (IEC): Geneva, Switzerland, 2007.) requirements.

Interleaved boost converters (IBCs) with soft-switching are well established for high-step-up PV applications. However, achieving > 96% efficiency at 1 kW and 300 kHz while maintaining compact single-core magnetic and EMC compliance remains challenging. Recent IBCs achieve high efficiency through ZVS/ZCS, but typically at lower frequencies (20–100 kHz) or require multiple inductors and complex always-active resonant networks that increase volume and light-load losses [42,43,44].

Key limitation of prior ZCS-IBC research (2020–2025): While demonstrate ZCS in multiphase IBCs, these employ continuous resonant operation across all loads, causing auxiliary losses at light loads (<20% rated power). High-frequency (f_sw > 200 kHz) SiC (Science Citation Index)-based IBCs excel at >10 kW but remain costly for 1 kW PV micro-converters. No prior work has combined selective load-adaptive ZCS (>5 A threshold), a single Litz-wound coupled-core inductor, and digital peak-current control to achieve 98.6% peak/96% full-load efficiency at 300 kHz with 120 mA ripple and has passed EMC certification (EN 55014) [45,46].

This study’s novel contribution addresses this gap through a two-phase 12–48 V IBC integrating:

• Load-selective active ZCS (disabled below 5 A via DCR sensing), eliminating reverse recovery while avoiding light-load penalties.
• Single EE32 Litz-core coupled inductor (k = −0.475), enabling 300 kHz with 0.6% ripple.
• Digital 2P2Z peak-current control (XMC4200) with verified stability.
• Full experimental validation, including thermal, dynamic, and EMC testing.

1.3. Structure of the Paper

The paper is divided into seven sections. Following the introduction, the design and analysis are discussed in Section 2. Section 3 of this study focuses on the application of a Litz-wire-based coupled inductor design analysis. Section 4 provides a detailed operating principle of the proposed ZCS cell. Section 5 is devoted to an in-depth examination of peak current mode control integration. Section 6 of this study presents the efficiency and loss analysis. Section 7 provides the experimental results and analysis. Section 8 offers a synopsis of the conclusions that were derived from this experimental work.

2. Design and Analysis

The working principle is illustrated by a simplified two-phase synchronous interleaved boost converter circuit in Figure 1.

Figure 1. Block diagram of the two phases interleaved buck boost converter with built-in ZCS circuit.

The built converter prototype is operating with a single core-coupled inductor, and the input current ripple is contingent on the coupled inductor configuration. In order to ensure that the phase shift between the coupled inductor windings does not exceed 180 degrees, it is necessary to ensure that the mutual inductance between the two inductors wound around the same core, which represents the coupling coefficient, takes a negative value, not with standing the argument in favor of non-inverted or the direct wounded inductor, where the coupling coefficient is positive.

The relationship between the voltage of the inversely coupled inductors and the currents that traverse the inductors for both phase 1 and 2 is expressed as follows:

$${v_L}_1=L_1{\displaystyle \frac{d{i}_1}{dt}}-M_{12}{\displaystyle \frac{d{i}_2}{dt}}$$

(1)

$${v_L}_2=L_2{\displaystyle \frac{d{i}_2}{dt}}-M_{21}{\displaystyle \frac{d{i}_1}{dt}}$$

(2)

where L₁ and L₂ are the self-inductance for the windings; M₁₂ and M₂₁ are the mutual inductance for each phase. These equations could be rearranged to show the inductors voltages under their matrix form by:

$$\left[\begin{array}{c}{v}_{L_1}\\ v_{L_2}\end{array}\right]=\left[\begin{array}{c}{L}_1\hspace{1em}\hspace{1em}{M}_{12}\\ M_{21}\hspace{1em}{L}_2\end{array}\right]\left[\begin{array}{c}{\displaystyle \frac{d{i}_1}{dt}}\\ {\displaystyle \frac{d{i}_2}{dt}}\end{array}\right]$$

(3)

where v_L1 is the voltage across the self-inductance of winding L₁ in the coupled-core inductor of phase 1.

v_L2 is the voltage across the self-inductance of winding L₂ in the coupled-core inductor of phase 2.

i₁ is the current flowing through the winding L₁.

i₂ is the current flowing through the winding L₂.

By assuming that L₁ = L₂ and M₁₂ = M₂₁, the inductors voltages could be represented by:

$$v_{L_1}=L(1-k^2){\displaystyle \frac{d{i}_1}{dt}}-k{v}_{L2}$$

(4)

$$v_{L2}=L(1-k^2){\displaystyle \frac{d{i}_2}{dt}}-k{v}_{L1}$$

(5)

where k is the coupling coefficient.

Equation (6) shows how to obtain the value k.

$$k={\displaystyle \frac{M}{\sqrt{L_2{L}_1}}}={\displaystyle \frac{M}{L}}\le 1$$

(6)

On this case, the mean value of the current by each inductor for both phases is:

$$I_{L_{mean}}={\displaystyle \frac{I_{in}}{2}}={\displaystyle \frac{I_{out}}{2(1-D)}}$$

(7)

where D is the duty cycle.

3. Application of a Litz-Wire-Based Coupled Inductor Design Analysis

Litz wires, a type of inductor, are composed of multiple insulated wires that are wound together to form a single unit. The company has gained renown for its superlative performance in high-frequency applications. A variety of studies on Litzwire windings based on Dowell’s [47] model have been presented [48].

Dowell’s equation was initially developed to calculate the variation in winding resistance with frequency for inductors with a wide foil. According to Dowell, the F_R ratio, defined as the AC to the DC resistance ratio in multilayer transformer windings, could be represented by:

$$F_R={\displaystyle \frac{R_{AC}}{R_{DC}}}$$

(8)

Dowell has deduced that the impedance Z_W of multilayer winding as for the different parameters constructing the inductor core could be represented by:

$$Z_w={\displaystyle \frac{\rho l_T{l_T}^2}{\eta bh}}\left\{mM+{\displaystyle \frac{m\left(m^2-1\right)D}{3}}\right\}$$

(9)

With:

$$\eta ={\displaystyle \frac{N_{l}a}{b}};\alpha =\sqrt{{\displaystyle \frac{j\omega {\mu }_0\eta }{\rho }}};D=2\alpha \mathit{tanh}{\displaystyle \frac{\alpha h}{2}};M=\alpha h\mathit{coth}\alpha h$$

where D is the core coupling function; ρ is the resistivity; l_T is the mean turn length; N_l is the number of turns per layer; a is the conductor breadth; b is the winding breadth; h is the height of a conductor; m is the number of whole layers in a winding portion; μ₀ is the free air magnetic permeability; ωis the angular frequency.

The two terms of the equation representing the resistance ratio relating the resistance caused by the skin effect R_skin to the DC resistance ratio and the resistance caused by the proximity effect R_prox to the DC resistance ratio are, respectively, F_Rskin and F_Rprox.

$${\displaystyle \frac{R_{skin}}{R_{dc}}}={\displaystyle \frac{R_{prox}}{R_{dc}}}={F_R}_{skin}+{F_R}_{prox}$$

(10)

The core structure-winding model for the used inductor design is presented in Figure 2. As illustrated in the accompanying diagram, the windings are wound on the inner leg of the EE32 core, with an equal air gap.

Figure 2. The core structure winding model of the magnetic part of the converter: (a) Coupled inductor with Litz-wire-based core inductor; (b) reluctance network model of the inductor core; (c) symmetric equivalent circuit of the inverted coupled inductor; (d) real built Litz-wire-based inversely coupled inductor.

Here, R_i is the reluctance of the inner leg of the core while R is the reluctance of the outer legs of the core, hence:

$$N_1{i}_1={\phi }_1 Ri+{\phi }_2 R$$

(11)

$$N_2{i}_2={\phi }_2 Ri+{\phi }_{1}R$$

(12)

By taking the winding ratio between the two windings 1:1 with respect to N₁ = N₂ = N, the equations can be represented under the matrix form to obtain the flux in the inner leg as follows:

where Δ = R(R + 2R_i).

With respect to Faraday’s law, the voltage across the coupled inductor can be represented by the following equations:

$$\left[\begin{array}{c}{v}_{L_1}\\ v_{L2}\end{array}\right]=\left[\begin{array}{c}{\displaystyle \frac{N^2(R+R_i)}{\Delta }}\hspace{1em}{\displaystyle \frac{-N^2{R}_i}{\Delta }}\\ {\displaystyle \frac{-N^2{R}_i}{\Delta }}\hspace{1em}{\displaystyle \frac{N^2(R+R_i)}{\Delta }}\end{array}\right]\left[\begin{array}{c}{\displaystyle \frac{d{i}_1}{dt}}\\ {\displaystyle \frac{d{i}_2}{dt}}\end{array}\right]$$

(13)

The following section will present the output current and the different gate signals driving the switches for the circuits that were previously presented in Figure 1. The purpose of this presentation is to show the waveform of the conducted inductor currents (see Figure 3).

Figure 3. The different waveform signal driving the converter with the associated current for the coupled inductor on both phase 1 and phase 2.

For a given T on applied to the V_gQ1, the peak current defined by I_PK1 and I_Pk2, respectively crossing the two windings, could be given by:

$${i_p}_k={\displaystyle \frac{V_{in}}{L}}{T}_{on}$$

(14)

The equivalent inductor variation on each step for the given cycle, illustrated above concerning the switching state of the converter within the same cycle, is expressed by:

$${L_{eq}}_1={\displaystyle \frac{L^2-M^2}{L+\frac{D}{D^{\prime }}M}}$$

(15)

$${L_{eq}}_2=L+M$$

(16)

$${L_{eq}}_3={\displaystyle \frac{L^2-M^2}{L+\frac{D^{\prime }}{D}M}}$$

(17)

D′ illustrates the E-core outer diameter.

It has been demonstrated that the activation of the auxiliary ZCS circuit proposed for this topology affects the current slope during the final step of the switching state. Consequently, the converter exhibited the capacity to attain elevated switching frequencies during its operation. Consequently, switching losses are minimized, and the resonant period that could be present at the end of the cycle under a valley oscillation is avoided (Figure 4). The equivalent inductance during the activation of the ZCS for this case presented in the figure above under Leq₄ is expressed by:

$${L_{eq}}_4=L-\left({\displaystyle \frac{M^2}{L}}\right)$$

(18)

Figure 4. Low-side synchronous switch VDS and IDS waveform.

4. Operating Principle of the Proposed ZCS Cell

This section explains the operating mechanism of the proposed ZCS cell integrated into the interleaved boost converter. The converter operates in continuous conduction mode (CCM), and the auxiliary branch is activated to suppress the reverse-recovery current of the synchronous MOSFET and to minimize switching losses at a high switching frequency of approximately 300 kHz. The sequence of events within one switching period is divided into six stages, as illustrated in Figure 5.

Figure 5. ZCS circuit-triggering process in conjunction to the switching steps during a working cycle: (a) Q₂ and Q₅ are ON and energy is stored in L₁ and L₂, (b) ZCS turn-off of Q₂ and freewheeling through the corresponding diodes, (c) Conduction of Q₃ and resonant discharge in the auxiliary branch and (d) ZCS turn-on of Q₁ and energy transfer to the output; (e) Commutation of Q₆ and redistribution of current between the interleaved legs, (f) end of the switching period and reset of the circuit for the next cycle.

• Stage 1: Freewheeling Interval (Figure 5a)

At the beginning of the cycle, Q₂ is turned OFF. The inductor current continues flowing through the body diode of Q₂ toward the output capacitor and load. Since the converter operates in CCM, the inductor current remains above zero and maintain uninterrupted conduction through the diode.

• Stage 2: Activation of the Auxiliary Switch Q₃ (Figure 5b)

When Q₃ is switched ON, the current in the ZCS inductor L_zcs begins to rise according to:

$${\displaystyle \frac{di}{dt}}={\displaystyle \frac{V_{out}-V_{in}}{L_{zcs}}}$$

(19)

During this interval, Izcs progressively diverts the current flowing through the diode of Q₂, thereby reducing the diode current and preparing Q₂ for a zero-current transition.

• Stage 3: Zero-Current Condition of Q₂ (Figure 5c)

As the current in L_zcs continues to rise, it eventually reaches the value of the main inductor current I_L1. At this moment, the current through the body diode of Q₂ is fully canceled. This achieves zero-current turn-off of Q₂ and eliminates the reverse-recovery charge typically associated with diode conduction.

• Stage 4: Zero-Current Turn-On of Q₂ (Figure 5d)

Once the current through Q₂ becomes zero, Q₃ is turned OFF and Q₁ is immediately turned ON. Because Q₂ was brought to zero current beforehand, Q₁ turns ON under ideal ZCS conditions, significantly reducing switching losses.

Simultaneously, the drain–source voltage of Q₂ transitions toward:

$$V_{DS}=V_{in}+V_{out}$$

(20)

This transition is governed by the intrinsic output capacitances of the MOSFET.

• Stage 5: Decay of I_zcs and Turn-Off of D_zcs (Figure 5e)

After Q₃ is turned OFF, the current in the ZCS inductor decays naturally. When I_zcs reaches zero, the diode D_zcs becomes reverse-biased and turns OFF. At this moment, the auxiliary path is fully reset, ensuring that no circulating energy remains in the ZCS branch.

• Stage 6: Return to Steady CCM Operation (Figure 5f)

With the ZCS branch deactivated, Q₁ continues to conduct the inductor current in standard CCM mode. When Q₁ turns OFF later in the period, Q₂ resumes its synchronous conduction until the next ZCS activation. The switching cycle then repeats identically in the following period.

5. Peak Current Mode Control Integration

Figure 6 provides a synopsis of the control topology of the interleaved converter with CCM and peak current control mode. In order to guarantee the robustness and stability control of the entire system, including the current control, it is essential that the MCU controller is equipped with the requisite tools for this task. For the purpose indicated, the utilization of an Infineon XMC 4200 32-bit MCU has been determined to be the most suitable option [49].

Figure 6. Peak-current code controller for interleaved converter topologies.

The latter is responsible for the utilization of various hardware tools that facilitate the development of different power converter topologies.

The comparator and slope generator are of the utmost importance. The comparator and slope generator are equipped with a 30.106 sample/s digital-to-analog converter integrated with a 20 ns speed comparator. In this particular case, the peripheral assists in the control of the slope reference, which, in turn, controls the current limit by triggering the PWM unit with a generated interrupt to update the PWM duty cycle calculation.

The definition of slope control compensation for peak current control is such that it ensures that no damping is added to the system response beyond what is required. This is because such damping can considerably affect the PWM duty cycle limitation, especially at maximum load. The solution under consideration employs a 2P2Z compensator. Figure 7 presents the loop control diagram of the control block.

Figure 7. Interleaved converter control loop compensation diagram.

The digital controller illustrated in the above diagram is a type-II compensator. Its transfer function in discrete form can be expressed as follows:

$$H_C\left[Z\right]={\displaystyle \frac{\frac{{\omega }_{Cp0}}{2Z-1}}{T_Z+1}}\ast {\displaystyle \frac{1+\frac{\frac{2Z-1}{T_Z+1}}{{\omega }_{CZ1}}}{\frac{2Z-1}{1+\frac{T_Z+1}{{\omega }_{Cp1}}}}}$$

(21)

After equation adjustment and manipulation, standard terms of the compensator are defined by:

$$H_C\left[Z\right]={\displaystyle \frac{B_2+B_1+B_0{Z}^2}{-A_2-A_1-Z^2}}$$

(22)

Table 1 presents the constants defining the digital compensator transfer function, as specified in Equation (23). Each constant is accompanied by its corresponding hexadecimal value utilized in the control code implementation.

Table 1. Digital compensator coefficients and code constants.

Constant	Definition	Code Value (HEX)
B0	${\displaystyle \frac{\left(T{\omega }_{Cp0}{\omega }_{Cp1}\right(2+T{\omega }_{CZ1}\left)\right)}{2(2+T{\omega }_{Cp1}){\omega }_{CZ1}}}$	0 × 70A
B1	${\displaystyle \frac{T^2{\omega }_{Cp0}{\omega }_{Cp1}}{(2+T{\omega }_{Cp1})}}$	0 × 6F
B2	${\displaystyle \frac{T{\omega }_{Cp0}{\omega }_{Cp1}(-2+T{\omega }_{CZ1})}{2(2+T{\omega }_{Cp1}){\omega }_{CZ1}}}$	0 × F56D
A1	${\displaystyle \frac{4}{(2+T{\omega }_{Cp1})}}$	0 × 6E9E
A2	${\displaystyle \frac{(-2+T{\omega }_{Cp1})}{(2+T{\omega }_{Cp1})}}$	0 × D160

Figure 8 illustrates the stability of the designed digital compensator. The step response shows a fast transient with a steady state value of 2 and a very small overshoot of 0.6%, indicating a well-damped closed-loop behavior. The Bode magnitude and phase plots exhibit high low-frequency gain with adequate gain and phase margins over the relevant frequency range, confirming robust stability of the current mode control loop. The pole–zero map in the z-plane shows closed-loop poles located well inside the unit circle, which is consistent with an overdamped and stable response. Based on the given frequency response data, the system exhibits comfortable stability margins. At the gain intersection point—where the value is 0 dB—the phase is −98.7 degrees at 904.3 Hz, meaning the phase margin is approximately 81.3 degrees. This large positive phase margin indicates a highly stable, well-damped closed-loop response with minimal risk of oscillation. Conversely, when the phase approaches −180 degrees, the magnitude is extremely low (−138.1 dB) at a frequency of 3998 Hz, well below 0 dB. This means that the system never reaches −180 degrees of phase and unit gain simultaneously, giving it an infinite (or very large) gain margin. The large phase margin and large gain margin together confirm that the system is perfectly stable, resistant to transaction changes, and unlikely to experience any instability under normal operating conditions.

Figure 8. Stability analysis of the designed current mode compensator (step response, Bode magnitude/phase, and pole–zero map).

6. Efficiency and Loss Analysis

The efficiency and power losses of the proposed 12 V to 48 V, 1 kW two-phase interleaved boost converter with coupled inductors were evaluated using an analytical model that accounts for inductor copper losses, MOSFET conduction losses, switching losses, and auxiliary losses. The average and RMS currents in each element are first obtained from the converter operating conditions and are then used to compute the individual loss components.

The output and input currents are related to the output power by:

$$I_{IN}={\displaystyle \frac{P_{OUT}}{V_{IN}}}$$

(23)

$$I_{OUT}={\displaystyle \frac{P_{OUT}}{V_{OUT}}}$$

(24)

While the DC current per phase is:

$$I_{phase,dc}={\displaystyle \frac{I_{IN}}{N_{ph}}}$$

(25)

For the coupled inductor, the peak-to-peak ripple current is given by:

$${∆I}_{pp}={\displaystyle \frac{V_{IN}\ast D}{f_S\ast L_{diff}}}$$

(26)

The RMS value of the AC component is approximated as:

$$I_{ac,rms}={\displaystyle \frac{{∆I}_{pp}}{2\surd 3}}$$

(27)

The RMS current in each inductor phase therefore becomes:

$$I_{phase,rms}=\sqrt{{I^2}_{phase,dc}+{I^2}_{ac,rms}}$$

(28)

In coupled inductors, there are copper losses. Eddy currents, hysterical occurrences, and other changing magnetic field-related processes are responsible for the losses. A small amount of the energy may manifest as noise, but the majority of it is dissipated as heat [50,51]. Inductor copper losses are evaluated by splitting the Litz-wire resistance into a low-frequency DC part and a high-frequency AC part. The corresponding losses are:

$$P_{cu,dc}=N_{ph}\ast {I^2}_{phase,dc}\ast R_{dc,Litz}$$

(29)

$$P_{cu,ac}=N_{ph}\ast {I^2}_{ac,rms}\ast R_{ac,Litz}$$

(30)

So that the total copper loss is:

$$P_{cu}=P_{cu,dc}+P_{cu,ac}$$

(31)

Synchronous rectifier MOSFET conduction losses are obtained from the RMS currents of the high side and low side devices. With the duty cycle D, the RMS currents are

$$I_{HS,rms}=I_{phase,dc}\ast \sqrt{D}$$

(32)

$$I_{LS,rms}={\displaystyle \frac{I_{OUT}}{N_{ph}}}\sqrt{1-D}$$

(33)

And the total MOSFET conduction loss is:

$${ P}_{MOS}=N_{ph}\left({I^2}_{HS,rms}+{I^2}_{LS,rms}\right)\ast R_{ds\left(on\right)}$$

(34)

Since zero-current switching is implemented, the remaining switching losses can be represented by a nearly constant switching energy per cycle:

$${ P}_{SW}=N_{ph}\ast f_S\ast E_{sw}$$

(35)

where $E_{sw}$ is the switching energy per switch.

The MOSFET gate drive losses are given by:

$$P_{gate}=N_{ph}\ast f_S\ast Q_g\ast V_{GS}$$

(36)

where $R_{ds\left(on\right)}$ is the on-resistance, and $Q_g$ is the total gate drive. The MOSFET characteristics ($R_{ds\left(on\right)}$ and $Q_g$) are given in the datasheet of the MOSFET.

The equivalent capacitor resistance, which is often included in datasheets, is used to determine capacitor losses. The following formula is used to calculate capacitor losses as follows [52]:

$${ I}_{C\_rms}=I_{out}\ast 0.1$$

(37)

$${ P}_{C\_rms}={{ I}_{C\_rms}}^2\ast { ESR}_{out}$$

(38)

where ${ I}_{C\_rms}$ represents the capacitor’s RMS current value, and ${ ESR}_{out}$ represents the equivalent capacitor resistance.

And all residual contributions (gate drive, core losses, and capacitor ESR) are grouped as:

$${ P}_{other}={ P}_{gate}+{ P}_{core}+{ P}_{ESR}$$

(39)

The total converter loss is therefore

$${ P}_{loss,tot}={ P}_{CU}+{ P}_{MOS}+{ P}_{SW}+{ P}_{other}$$

(40)

And the efficiency as a function of output power is calculated as:

$$\eta ={\displaystyle \frac{{ P}_{OUT}}{{ P}_{OUT}+{ P}_{loss,tot}}}\ast 100\%$$

(41)

The Figure 9 shows the calculated efficiency of the interleaved 12 V to 48 V boost converter using synchronous rectification and Litz-wire coupled inductors over the output-power range from 0 to 1 kW. The converter reaches a maximum efficiency of about 98.6% at approximately 190 W and maintains efficiency close to 96% at 1 kW, demonstrating low total losses and high performance in the whole operating range.

Figure 9. Efficiency of the proposed 12 V to 48 V, 2-phase interleaved boost converter (SR + Litz, k = −0.475).

Figure 10 illustrates the power loss breakdown versus output power for the proposed 12 V to 48 V interleaved boost converter employing synchronous rectification and Litz-wire coupled inductors. The stacked areas depict inductor copper losses, MOSFET conduction losses, switching losses, and auxiliary losses (gate-drive, core, and capacitor ESR). At full 1 kW load, total losses reach approximately 40 W, predominantly from copper (≈17.4 W) and MOSFET conduction (≈21.3 W), while switching and other losses remain minimal (<2 W), confirming conduction dominance and effective ZCS suppression of switching losses.

Figure 10. Loss breakdown of the proposed 12 V to 48 V, 1 kW interleaved boost converter (SR + Litz, k = −0.475).

Table 2 compares the designed work with some existing topologies. This comparison aims to demonstrate the significance of the designed topology compared to other existing topologies. The comparison in Table 2 highlights that the proposed two-phase interleaved structure with the active ZCS cell achieves a superior combination of high step-up ratio, active ZCS operation, very-low-output current ripple, and high efficiency at a rated power of 1 kW, when compared with previously reported converters operating under similar conditions. This confirms that the proposed topology is a strong candidate for medium-power applications such as photovoltaic and energy-storage systems, where high power density, reduced current ripple and high conversion efficiency are essential requirements.

Table 2. Comparison between the proposed 2 phases IBC with other existing topologies.

Reference	Vin/Vout	Soft-Switching	Output Current Ripple	Switching Frequency	Rated Power	Efficiency
[53]	36 V/400 V	ZCS (Turn-on)	Small	50 KHz	1 KW	95.69% (max), 92.0% (full load)
[54]	24 V/400 V	ZCS (Turn-on)	Moderate	50 KHz	1 KW	95.52% (max), 87.36% (full load)
[55]	20 V/380 V	No	Low	50 KHz	150 W	96% (max), 90% (full load)
[56]	150 V/300 V	No	Small	40 KHz	2 KW	98.3%(max)
[57]	12 V/40 V	Yes	Very Low	100 K	285 W	98%(max)
Proposed	12 V/48 V	Yes (active ZCS cell)	Very Low (~120 mA)	300 KHz	1 KW	98.6% (max), 96% (full load)

7. Testing and Results Analysis

A comprehensive experimental testing program was conducted to evaluate the system’s performance characteristics, including its reliability and response time. The testing program also assessed the system’s compliance with safety regulations and manufacturing standards necessary for market certification.

In the initial phase of the experiment, a series of tests were conducted on the constructed inductor to assess its various parameters. As illustrated in Figure 11, the test procedure involved the measurement of resistance and inductance using an LCR meter under various frequencies and voltages. The experimental protocol entails the application of varying voltages (1 V, 3 V, and 5 V Limit) across a spectrum of frequencies ranging from 10 kHz to 500 kHz.

Figure 11. Litz wire inverse coupled inductor laboratory test.

Figure 12 shows the calculated copper loss of the 21.19 µH inductor as a function of frequency for a solid AWG16 winding and a 200 × AWG44 Litz winding, assuming 12 A RMS. At the nominal switching frequency of 300 kHz, the solid wire exhibits an AC resistance of about 97 mΩ and a copper loss of ≈14 W, whereas the Litz wire exhibits about 31 mΩ and ≈4.5 W, corresponding to a 68% reduction in copper loss. This demonstrates the benefit of using Litz wire for the interleaved converter in terms of reduced inductor losses and improved efficiency.

Figure 12. Calculated copper loss of the 21.19 µH inductor versus frequency for solid AWG16 wire and 200 × AWG44 Litz wire (12 A RMS).

As illustrated in Figure 13, the PWM signals are evident on the various switches for both phases 1 and 2. It is imperative to acknowledge that the utilized MCU (XMC4200 MCU) incorporates a configurable dead time option, which is managed through a predefined register. This feature is instrumental in the control of multiple converter topologies, a necessity in the proposed solution. The dead time is maintained between the PWM signal of the Q₁ and Q₂ gates of the first phase, in conjunction with the two other switches for phase 2, Q₄ and Q₅.

Figure 13. The four PWM switch provided by the XMC 4200 MCU with built-in dead time: (a) Experimental setup including the LCR meter, programmable DC source, programmable electronic load, oscilloscope, and the DUT, (b) PWM gate signals generated by the XMC4200 MCU with built-in dead time: the magenta and green traces correspond to the high-side switches Q₁ and Q₄ of phases 1 and 2, while the cyan and yellow traces correspond to the low-side switches Q₂ and Q₅, respectively.

The direct current resistance (DCR) circuit for high-side current sensing is a cost-effective solution that has been applied to the prototype for the inductors’ current sensing in conjunction with the main output device’s current consumption. The circuit has been simulated for the values of the components, checked for limitations, and implemented. The output of the operational amplifier (op amp) is a 165 mV conversion ratio for 1 A passing through the inductor. This value is determined in relation to the hardware requirements. The 32-bit ADC pin on the XMC 4200 MCU is constrained to 3.3 V for maximum analog inputs. For a 20 A current limitation on the device itself and a maximum power output of 1 kW, the perfect conversion ratio is approximately 165 mV. As illustrated in the above figure, the output of the operational amplifier (op amp) targeting the MCU ADC has been plotted. This figure demonstrates the various waveforms of each inductor current with reference to the PWM switching sequence previously discussed. It has been determined that, at a constant load of 20 A, the current ripple on each inductor (a single ferrite core Litz wire coupled) is approximately 120 mA. This calculation is based on a 300 kHz switching frequency and 48 V output voltage reference.

One important advantage of the proposed interleaved boost converter with a coupled inductor is the low-output current ripple. To quantify this effect, the theoretical peak to peak output current ripple (Δ_Iout,pp) is evaluated using the effective differential inductance L_diff. The differential inductance is obtained in the aiding configuration (opposing in operation due to reversed winding polarity) as L_aiding = L_diff = 2L(1 + ∣k∣) = 2 × 21.19 × (1 + 0.475) = 62.5 μH.

In the above configuration, L = 21.19 μH is the self-inductance of each winding, and k = −0.475 is the measured coupling coefficient. With Vin = 12 V, duty cycle D = 0.75, switching frequency f_s = 300 kHz, and L_diff = 62.5 μH, the analytical expression Δ_Iout,pp = Vin × D/(4 × fs × L_diff) gives ΔI_out, pp ≈ 120 mA. This value is in excellent agreement with the measured output current ripple shown in Figure 14, confirming that the low-output current ripple predicted by the interleaving and coupling theory is effectively achieved in the implemented prototype (Figure 14).

Figure 14. DCR phase’s inductor current output monitoring.

As demonstrated in Figure 15, the system stability response is depicted under constant output voltage reference (24 V) and variable constant load over a predetermined time interval.

Figure 15. System stability checks with constant voltage reference and 2 A load shutdown and start-up step configuration.

Initially, the converter is connected with a constant load with 2 A references. Subsequently, the programmable load is configured to deactivate the load and reactivate it within a time span of 2 milliseconds. The experimental results demonstrate the system’s capacity to maintain stability during periods of load variation, thereby ensuring that the voltage remains within the pre-set reference range.

As previously mentioned, under conditions of low demand, there is a possibility that the active ZCS circuit may be deactivated. As demonstrated by the findings of the conducted experiments, the deactivation of the active ZCS at low loads has been shown to enhance the efficiency of the converter. As illustrated in Figure 16, the ZCS circuit is activated during periods of high current demand. The DCR circuit previously illustrated in Figure 6, utilized for the inductor current sense, is employed in conjunction with a numerically integrated threshold limit of 5 A. Upon the occurrence of this limit during a fixed time interval (100 µs), the PWM signal intended for the regulation of Q₃ and Q₆ is activated on the PWM control unit.

Figure 16. ZCS circuit system triggering (ZCS is activated for 5 A load reference).

One of the tests performed involves the application of a full load test to the converter. The converter is subjected to a constant load of 20 A, in accordance with the technical requirements. As illustrated in Figure 17, the output current waveform was recorded during a 48 V output voltage reference with a 12 V input constant source and a constant programmable load of 20 A.

Figure 17. Full load 20 A output current with 48 V voltage reference.

Concurrently, thermal imaging was conducted to assess the temperature rise ratio during the test. This evaluation aimed to evaluate the hardware components’ layout from a lateral perspective and the thermal dissipation on the studied region of the high-power side of the converter from another (Figure 18).

Figure 18. FLIR thermal imaging for hardware temperature check.

An additional evaluation method employed to assess system stability involves the variation of both the output voltage and current. In this experiment, the converter is synchronized with the programmable load, whereby the variation in the current load is applied concurrently with the voltage output variation. As demonstrated in Figure 19, the behavior of the converter and its stability during the execution of this test are illustrated. As illustrated, the figure demonstrates the activation of the ZCS circuit. Initially, the programmable load is set to 0.5 A. Subsequently, an internal interrupt triggers the voltage reference linked to the ZCS circuit activation comparator with a 5 A load.

Figure 19. System stability check with load variation and voltage reference variation.

In accordance with applicable safety standards, the converter underwent various tests, in addition to the performance evaluations carried out in the laboratory. Specifically, the tests encompassed the standards for electromagnetic compatibility (EMC) applicable to household appliances, electric tools, and analogous equipment. The testing of emission requirements was conducted in accordance with the provisions stipulated in EN 55014-1, while the mitigation of interference phenomena was addressed by the guidelines outlined in EN 55014-2. The Electrostatic Discharge (ESD) test was conducted in accordance with the requirements of the EN 61000-4-2 standard. As illustrated in Figure 19, Figure 20, Figure 21 and Figure 22, the test reports for ESD, EMI, and EMI-click noise confirm the converter’s successful performance in various noise click frequency tests.

Figure 20. Interleaved converter EN 61000-4-2 ESD laboratory test. (a) Photo of the ESD test setup on the table (DUT, generator, ground plane, etc.), (b) EN 61000-4-2 standard test schematic (table, VCP, HCP, GRP, ESD gun), (c) pulse waveform diagram, (d) screenshot of the ESD generator display (showing test voltage and settings).

Figure 21. Interleaved converter EN 55014-1 EMI-Disturbance laboratory test report.

Figure 22. Interleaved converter EN 55014-1 EMI-click noise laboratory test report.

In Figure 21, the two red straight lines represent the EN 55014-1 radiated-emission limits, where the upper line is the quasi-peak (QP) limit and the lower line is the average (AV) limit over the 30–300 MHz range. The blue curve shows the measured quasi-peak emission of the interleaved converter, while the green curve corresponds to the measured average emission. Both measured curves remain below the respective limit lines across the entire frequency range, confirming that the proposed converter complies with the EN 55014-1 EMI radiated-disturbance requirements

8. Conclusions

This work demonstrated the development and experimental evaluation of a 1 kW two-phase interleaved boost converter incorporating a Litz-wire coupled inductor and an active ZCS cell. The prototype achieved 98.6% peak efficiency, 96% full-load efficiency, and ~120 mA output-current ripples at a high switching frequency of 300 kHz. Loss analysis indicated that total losses at 1 kW were approximately 40 W, dominated by conduction rather than switching losses due to effective ZCS activation above the 5 A threshold. Thermal characterization confirmed a maximum temperature rise below 80 °C during continuous 20 A operations. Dynamic tests showed output-voltage deviations of less than 1% during load steps, while EMI and ESD evaluations verified full compliance with EN 55014-1/2 and EN 61000-4-2 standards. These results confirm that the proposed converter meets the requirements for compact, high-efficiency power-conversion systems in photovoltaic, industrial, and embedded energy applications.

In the future, further experimental tests will be conducted on the topology designed in this paper to determine its operational performance and robustness compared to existing topologies. Additionally, this designed topology will be applied to other energy systems to assess its effectiveness in improving the characteristics of those systems.