Review Reports - A W-Band Bidirectional Switchless PALNA in SiGe BiCMOS Technology

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

At W-band bidirectional PALNA for mm-wave phased-array systems, is presented. The architecture eliminates the need for switches by directly integrating the PA and LNA through a simplified passive matching network. This approach ensures proper isolation and impedance matching between transmit and receive paths while minimizing area and insertion losses.

This work is interesting and into the journal scope. In addition it is solid with a stable theoretical background and competitive performance. However the work is combination of HW measurements and postlayout simulation results. On this aspect, and since in this frequency regime all metal routings are behaving as transmission lines the respective simulation work should be quite advanced. Therefore pls provide information or update the simulation work with advanced analysis - did you use 3D or 2.5D EM simulations ? How the non HW verified part was evaluated? HFSS, ADS Agilent, RaptorX - how did you evaluate the mmWave performance? Please elaborate more on the simulation work, since this is way limited into the document, and since the validity of this work and the related performance is dependent on the simulation work.

Author Response

Comment : This work is interesting and into the journal scope. In addition it is solid with a stable theoretical background and competitive performance. However the work is combination of HW measurements and postlayout simulation results. On this aspect, and since in this frequency regime all metal routings are behaving as transmission lines the respective simulation work should be quite advanced. Therefore pls provide information or update the simulation work with advanced analysis - did you use 3D or 2.5D EM simulations ? How the non HW verified part was evaluated? HFSS, ADS Agilent, RaptorX - how did you evaluate the mmWave performance? Please elaborate more on the simulation work, since this is way limited into the document, and since the validity of this work and the related performance is dependent on the simulation work.

Response : Thank you very much for taking the time to review this manuscript, for your thoughtful review and for highlighting this important point.

To obtain accurate post-layout predictions at W-band, we employed a hybrid EM/PEX co-simulation flow. Selected passive structures and interconnects (e.g., matching networks and transmission lines) were modeled with full-wave electromagnetic simulations using Keysight Momentum, a 2.5D planar EM solver, while active devices and resistors were back-annotated with parasitic extraction (Cadence PVS QRC). The combined datasets yield a back-annotated post-layout schematic that captures the circuit behavior with high fidelity and supports the measurements.

The reliability of this methodology and the design tools has been validated by measurements of two components operating around 100 GHz: an LNA and an SPDT switch, which have been added to the revised version of the manuscript.

Also, after establishing these measurements, we compared them with post-layout simulations obtained from two EM tools. In addition to Momentum, an independent EM model was generated with EMX. As shown in the revised manuscript (Figure 12), both tools track the measured S11 and S22 across the W-band, with Momentum showing slightly tighter agreement over frequency. This cross-validation supports the fidelity of the EM/PEX flow used in this work.

Reviewer 2 Report

Comments and Suggestions for Authors

The manuscript presents a W-band bidirectional switchless PALNA implemented in 130-nm SiGe BiCMOS technology, targeting high-frequency phased-array systems. The topic is relevant and addresses the critical challenge of minimizing insertion losses and area overhead in mm-wave front-end design by eliminating traditional T/R switches. The proposed architecture demonstrates promising simulation results, including a peak gain of 30 dB in TX mode and a minimum noise figure of 6 dB in RX mode. However, several important technical and presentation aspects require further clarification and enhancement to improve the completeness and rigor of the manuscript.
1. The manuscript claims that the PALNA achieves a small-signal gain of 30 dB in transmit mode. However, based on Figure 9(b), the curve appears to peak at a value below 30 dB, which raises concerns about the accuracy of the stated performance. The authors are encouraged to either revise the gain specification to match the simulated data or clarify whether the 30 dB figure was obtained under different conditions. Additionally, explicitly labeling all relevant S-parameter curves (e.g., S11, S21, S22) in Figure 9, and annotating key numerical values would help improve the clarity, transparency, and interpretability of the figure.

2. The current manuscript provides measurement results only for the first stage of the LNA, while the remainder of the PALNA—including the full LNA and PA—is supported solely by post-layout simulations. It would greatly enhance the credibility and impact of the work if the authors could clarify whether full-chip (LNA + PA) measurements are planned or already in progress. If not, it is recommended to provide additional discussion or justification regarding the expected consistency between simulated and measured results at the system level. Without such validation, the practical applicability of the proposed architecture remains somewhat limited.

3. The abstract mentions “reverse isolation better than 40 dB,” but no corresponding discussion or supporting data is provided in the main text.

4. The manuscript provides a useful comparison with prior W-band PALNA implementations (e.g., references [13]–[15]); however, it lacks citations to more recent works from the past three years. To better position the contribution within the current state of this work, the authors are encouraged to include and discuss more up-to-date references published. This would help highlight the novelty and relevance of the proposed design.

Author Response

Thank you very much for taking the time to review this manuscript, for your thoughtful review and for highlighting these important points.

Comment 1 :The manuscript claims that the PALNA achieves a small-signal gain of 30 dB in transmit mode. However, based on Figure 9(b), the curve appears to peak at a value below 30 dB, which raises concerns about the accuracy of the stated performance. The authors are encouraged to either revise the gain specification to match the simulated data or clarify whether the 30 dB figure was obtained under different conditions. Additionally, explicitly labeling all relevant S-parameter curves (e.g., S11, S21, S22) in Figure 9, and annotating key numerical values would help improve the clarity, transparency, and interpretability of the figure.

Response 1 : You are correct that there was a confusion in the earlier version of the manuscript: the gain specification was mistakenly associated with results from a related PALNA design integrating a T/R switch with the PA and LNA matching networks, which we are developing in parallel and currently under review elsewhere. We have corrected this error in the revised version of the manuscript. The actual gain of the proposed design is consistent with the reported performance.

Comment 2 : The current manuscript provides measurement results only for the first stage of the LNA, while the remainder of the PALNA—including the full LNA and PA—is supported solely by post-layout simulations. It would greatly enhance the credibility and impact of the work if the authors could clarify whether full-chip (LNA + PA) measurements are planned or already in progress. If not, it is recommended to provide additional discussion or justification regarding the expected consistency between simulated and measured results at the system level. Without such validation, the practical applicability of the proposed architecture remains somewhat limited.

Response 2 : At present, we are awaiting a manufacturing budget to continue this work with a full PALNA implementation. To ensure reliable post-layout predictions at W-band, we employed a hybrid EM/PEX co-simulation methodology: key passive structures and interconnects (e.g., matching networks and transmission lines) were modeled using full-wave electromagnetic simulations (Keysight Momentum, a 2.5D planar solver), while active devices and resistors were back-annotated through parasitic extraction (Cadence PVS QRC). The resulting back-annotated schematic captures circuit behavior with high fidelity and underpins our current measurements.

Also, measured results were compared against post-layout simulations performed with two independent EM tools (Momentum and EMX). As shown in the revised manuscript (Figure 12), both models closely follow the measured S11 and S22 across the W-band, with Momentum showing slightly tighter agreement. This cross-validation reinforces the reliability of the EM/PEX methodology used, and provides confidence that the system-level PALNA performance will be consistent once full-chip measurements are completed.

Comment 3 : The abstract mentions “reverse isolation better than 40 dB,” but no corresponding discussion or supporting data is provided in the main text.

Response 3 : Thank you for pointing that out. The isolation was extracted using the inverse transmission parameter S₁₂ in both operating modes, and the simulation plots were added and commented on.

Comment 4 : The manuscript provides a useful comparison with prior W-band PALNA implementations (e.g., references [13]–[15]); however, it lacks citations to more recent works from the past three years. To better position the contribution within the current state of this work, the authors are encouraged to include and discuss more up-to-date references published. This would help highlight the novelty and relevance of the proposed design.

Response 4 :

We acknowledge the importance of positioning our contribution with respect to the most recent state-of-the-art. However, we note that relatively few works have been published on PALNA architectures in the W-band. Nevertheless, following the reviewer’s suggestion, we have updated our manuscript to include a recent publication from 2025. As a result, the comparison table now covers works published in 2025, 2024, 2020, and 2019, which situates our contribution within both the latest advances and prior developments. This update further highlights the novelty and relevance of the proposed design.

Reviewer 3 Report

Comments and Suggestions for Authors

The submission proposes a switchless bidirectional PALNA at W-band in IHP’s SG13G2 SiGe BiCMOS. The architecture relies on impedance-transformation networks and bias-controlled states to isolate Tx/Rx without T/R switches. Reported post-layout simulations show approx. 30dB Tx gain, 26dB Rx gain, NF ≈ 6dB @ 100GHz, Psat ≈ 10.3dBm, and PAEmax ≈ 12%, with 78mW (Tx) / 22mW (Rx) power and 0.7 mm² of chip area. Reverse isolation >40dB is claimed. The approach hinges on driving the upper cascode base–collector junction toward forward bias in the inactive path so that an output network transforms the impedance toward a high value (~500 Ω), providing isolation.

The topic is relevant since the manuscript addresses an important integration challenge for phased-array front-ends by removing active switches and using passive matching with bias control. However the paper has many technical drawbacks.

Major weaknesses in my opinion are:

- lack of functional prototype and quantitative evidence limited to postlayout simulations for the full PALNA. Full-chip PALNA results are simulations whereas the first LNA stage is measured but the chip hasn't been shown. Was it possible to fabricate the prototype and perform the measurements? The technology is rather old and MPW is not expensive, so it should be present at this level of journal, in my opinion especially because switchless bidirectional PALNA claim (gain, NF, isolation, and large-signal metrics need measurement at W-band) needs to be experimentally backed up;

- the method intentionally pushes the cascode B-C junction toward forward bias in the OFF path; Table 1 reports Cμ rising from fF to pF level when Vb ≈ 0.9–1.0 V, with collector current reaching mA even though other biases are off. The authors should justify device reliability, leakage paths, and startup/overshoot risks under this bias condition and explain how such bias is practically generated and sequenced on-chip;

- with shared paths and bias-dependent terminations, stability (K-factor/μ for both modes), sensitivity to PVT and layout parasitic spread, and Monte-Carlo are essential and mandatory but are completely absent in the presented article;

- reverse isolation is claimed >40dB in the abstract, but no measured/simulated isolation plots are provided. Rx linearity (IIP3), noise figure measurement method and de-embedding, and Tx AM/AM-AM/PM characteristics are missing. Load-pull is mentioned, but on-chip load-pull setup and resulting optimum impedances are not described;

- why is bandwidth omitted from comparison with state-of-the-art in Table 2?

- reference [12] citing https://www.academia.edu upload is ridiculous. The authors should use proper textbook or journal citations and not arbitrary document sharing websites!

If the authors would like their paper to be published they should at least:

- Fabricate and measure the full PALNA, reporting: S-parameters (both modes), reverse isolation (S12/S21), NF with method and calibration, Psat/OP1dB/PAE across frequency, and mode-switching transients. (the present submission only measures the first LNA stage)

- provide stability analysis (K, μ) and robustness over PVT/Monte-Carlo.

- document the biasing network that sets Vb ≈ 0.9 V in the inactive path: current paths, leakage, device reliability limits, and ESD/protection strategy given the near-forward-biased junction.

- detail the EM modeling (tool, ports, mesh, de-embedding) for TL8–TL10 and quantify how TL10 yields ~500 Ω in the OFF state; show Smith charts with frequency annotations.

- provide axis labels, frequency markers, and absolute reference impedances on all Smith charts; include a chip micrograph with pad labeling (not just layout which if provided should be annotated with vertical and horizontal dimensions, pad signal pins, etc.)

- Clarify measurement setup for the first-stage LNA (VNA model, calibration, probe/fixture losses, NF method, etc.)

- redraw Figure 2 schematic in some professional schematic tool such as for example CircuiTikZ https://ctan.org/pkg/circuitikz

Comments on the Quality of English Language

Page 4, last sentence: "To analyzing the output impedance..." has a gerund error and should be "To analyze the output impedance..."

Page 9, last paragraph: "an input (IP1dB) of −20 dBm have been achieved" should be with subject-verb agreement as "an input (IP1dB) of −20 dBm has been achieved"

Define VBIC and TL abbreviations on their first use as Vertical Bipolar Intercompany Model and Transmission Line...

Author Response

Thank you very much for taking the time to review this manuscript, for your thoughtful review and for highlighting these important points.

Comment 1: lack of functional prototype and quantitative evidence limited to postlayout simulations for the full PALNA. Full-chip PALNA results are simulations whereas the first LNA stage is measured but the chip hasn't been shown. Was it possible to fabricate the prototype and perform the measurements? The technology is rather old and MPW is not expensive, so it should be present at this level of journal, in my opinion especially because switchless bidirectional PALNA claim (gain, NF, isolation, and large-signal metrics need measurement at W-band) needs to be experimentally backed up;

Response 1 : We sincerely thank the reviewer for this valuable comment. At present, we are awaiting a manufacturing budget to continue this work with a full PALNA implementation.

To ensure reliable post-layout predictions at W-band, we employed a hybrid EM/PEX co-simulation methodology: key passive structures and interconnects (e.g., matching networks and transmission lines) were modeled using full-wave electromagnetic simulations (Keysight Momentum, a 2.5D planar solver), while active devices and resistors were back-annotated through parasitic extraction (Cadence PVS QRC). The resulting back-annotated schematic captures circuit behavior with high fidelity and underpins our current measurements.

Furthermore, measured results were compared against post-layout simulations performed with two independent EM tools (Momentum and EMX). As shown in the revised manuscript (Figure 12), both models closely follow the measured S11 and S22 across the W-band, with Momentum showing slightly tighter agreement. This cross-validation reinforces the reliability of the EM/PEX methodology used and provides confidence that the system-level PALNA performance will be consistent once full-chip measurements are completed.

Comment 2 : the method intentionally pushes the cascode B-C junction toward forward bias in the OFF path; Table 1 reports Cμ rising from fF to pF level when Vb ≈ 0.9–1.0 V, with collector current reaching mA even though other biases are off. The authors should justify device reliability, leakage paths, and startup/overshoot risks under this bias condition and explain how such bias is practically generated and sequenced on-chip;

Response 2 :

We thank the reviewer for this important question. In the revised manuscript, we have clarified how the cascode bias is generated and why it remains safe under all operating conditions. Specifically, the bases of the cascode devices are biased through a cascoded current mirror and fed via ~3.2 kΩ resistors (Fig. 14), which strongly limit the base current and maintain the base–collector junction at a near-forward bias around 0.9 V in the inactive path. This avoids the multi-mA conduction that would otherwise occur, keeps Vbc well below 1 V across all PVT corners and startup transients, and still provides the intended enhancement of the Miller capacitance Cμ.

We validated this strategy over 243 PVT corners (HBT, resistors, capacitors; ±20% supply; −40/25/125 °C), where both Vbc and Ib remained safe, with base currents only in the few-µA range. Monte-Carlo simulations including process variation and mismatch further confirmed that both Vbc and Ib distributions remain tightly clustered near their nominal values (Figs. 15–16). These results demonstrate that the cascode biasing scheme ensures device reliability, avoids leakage or destructive conduction, and guarantees robust startup sequencing while achieving the desired Cμ increase.

Comment 3 : reverse isolation is claimed >40dB in the abstract, but no measured/simulated isolation plots are provided. Rx linearity (IIP3), noise figure measurement method and de-embedding, and Tx AM/AM-AM/PM characteristics are missing. Load-pull is mentioned, but on-chip load-pull setup and resulting optimum impedances are not described;

Response 3 :

Thank you for pointing that out. The isolation was extracted using the inverse transmission parameter S₁₂ in both operating modes, and the simulation plots were added and commented on.

The S-parameters were measured twice. First, at the XLIM research laboratory using a Keysight PNA-X equipped with W-band frequency extenders up to 115 GHz. The data were then independently re-measured at MC2 Technologies, a recognized mmWave laboratory, to cross-validate the results. The noise figure was also measured at MC2 using a W-band cold-source method with full vector correction, a setup they use to obtain accurate results up to 110 GHz.

Comment 4 : why is bandwidth omitted from comparison with state-of-the-art in Table 2?

Response 4 : Thank you for pointing that out. The 3-dB bandwidth has now been added to the comparison table with the state of the art, and it highlights the advantage of the proposed work over prior implementations.

Comment 5: redraw Figure 2 schematic in some professional schematic tool such as for example CircuiTikZ https://ctan.org/pkg/circuitikz

Response 5 : Thank you for pointing that out. It's true that Figure 2 was less clear.

Figure 2 has been improved to enhance its clarity. We use Inkscape to produce high-resolution vector diagrams in SVG format, which ensures that the figure maintains its quality under zooming and scaling.

Comment 6 : provide axis labels, frequency markers, and absolute reference impedances on all Smith charts; include a chip micrograph with pad labeling (not just layout which if provided should be annotated with vertical and horizontal dimensions, pad signal pins, etc.)

Response 6 : We thank the reviewer for this helpful remark. In the revised manuscript, absolute impedance values corresponding to the Smith chart traces have been added in the text. Furthermore, the electrical schematic of the proposed switchless PALNA is now included, together with both the schematic and layout of the fabricated single-stage LNA, as well as the schematic and layout of a realized SPDT switch.

Comment 7 : Comments on the Quality of English Language

Response 6 : Thank you for your helpful comments regarding my English and for pointing out the mistakes. I have corrected them in the revised manuscript.

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

Nice Work! And thank you for addressing my comments.

Author Response

Dear Reviewer,

Thank you very much for your positive feedback and encouraging comments. In addition to the revisions already made, we have also included 3-D layout views for the different components in the new version of the manuscript.

Best regards,

Reviewer 2 Report

Comments and Suggestions for Authors

My concerns regarding the nature of the proposed approach were addressed. The explanation was very detailed and helpful. However, a few formatting details still require attention. Here are my suggestions on formatting:

On page 5 (“Cμ”) and page 9 (“S₂₂”), the subscript formatting is inconsistent with the rest of the manuscript and should be unified. Please check the entire manuscript carefully.
In Fig. 19(b) and Fig. 20(a), (b), the x-axis label should be “Frequency” instead of “Fré”
On page 13, second paragraph, in the sentence “The noise figure of PALNA in the RX mode at 100 GHz is about 6 and remains below 6.5dB over the entire 3dB band.” the expressions “5dB” and “3dB” should be corrected to either “6.5 dB” and “3 dB” (with spaces) or “6.5-dB” and “3-dB” (with hyphens).

Author Response

Coments:

On page 5 (“Cμ”) and page 9 (“S₂₂”), the subscript formatting is inconsistent with the rest of the manuscript and should be unified. Please check the entire manuscript carefully.
In Fig. 19(b) and Fig. 20(a), (b), the x-axis label should be “Frequency” instead of “Fré”
On page 13, second paragraph, in the sentence “The noise figure of PALNA in the RX mode at 100 GHz is about 6 and remains below 6.5dB over the entire 3dB band.” the expressions “5dB” and “3dB” should be corrected to either “6.5 dB” and “3 dB” (with spaces) or “6.5-dB” and “3-dB” (with hyphens).

Response :

Dear Reviewer,

We sincerely thank you for your constructive feedback and careful review of our manuscript. We have carefully implemented all your suggestions regarding formatting: the subscript notations have been unified throughout the manuscript, the x-axis labels in Figures 19(b) and 20(a),(b) have been corrected to “Frequency,” and the dB expressions have been standardized as recommended. In addition, we have also included 3-D layout views for the different components in the new version of the manuscript.

We appreciate your valuable comments, which helped us improve the clarity and consistency of our paper.

Best regards,

Reviewer 3 Report

Comments and Suggestions for Authors

The authors responded as good as they could. However, "we are awaiting a manufacturing budget to continue this work with a full PALNA implementation" should not be a valid argument. I could equally say, once you get the budget and obtain the prototype, measure it and then include it in your manuscript, alternatively satisfy yourself with some lower-ranked journal. Nevertheless I leave these to the @editors to decide, since they are taking care of this journal's metrics.

If you already decided to use simulations, please at least include your 3-D layout views of the key structures as extracted from EMX and/or Momentum as done, for example, in publications: https://ieeexplore.ieee.org/document/8392547 or https://ieeexplore.ieee.org/document/8834792 or https://link.springer.com/article/10.1007/s10470-016-0910-2 or https://www.tandfonline.com/doi/abs/10.1080/00207217.2022.2062793 This will ensure at least somewhat valid absence of the measurement results.

Include in Figure 8 and Figure 10 dimensions (like you did for the layout in Figure 18.) and annotate pads (at least to the "GND, Signal, GND" or "GSG") level.

Figure 19b and Figure 20 have an x-axis label "Fréquence" in French, instead of "Frequency" in English.

Author Response

Coments :

Include in Figure 8 and Figure 10 dimensions (like you did for the layout in Figure 18.) and annotate pads (at least to the "GND, Signal, GND" or "GSG") level.

Figure 19b and Figure 20 have an x-axis label "Fréquence" in French, instead of "Frequency" in English.

Response :

Dear Reviewer,

We thank you for your detailed review and for the constructive comments provided. We understand your concern regarding the absence of full PALNA measurement results. While the continuation of this work indeed depends on the availability of a manufacturing budget, we have strengthened the manuscript to better support our simulation-based validation. In particular, we have now included 3-D layout views of the key structures as extracted from EMX and Momentum, following practices from the referenced literature.

Furthermore, we have revised Figure 8 and Figure 10 to include dimensions and added pad annotations to improve clarity. We have also corrected the x-axis labels in Figures 19(b) and 20 to “Frequency” in English.

We hope these revisions address your concerns and improve the technical soundness and clarity of the manuscript.

Best regards,

Round 3

Reviewer 3 Report

Comments and Suggestions for Authors

The authors have sufficiently improved their manuscript to overcome the publication threshold. Good luck.

Author Response

Thank you for the time and effort you devoted to reviewing our manuscript. Your constructive remarks and suggestions were invaluable in improving the quality and clarity of our work and strengthening the final version of the paper. We are sincerely grateful for your consideration.