Research on the Evaluation Method of Electrical Stress Limit Capability Based on Reliability Enhancement Theory
Round 1
Reviewer 1 Report
Comments and Suggestions for AuthorsThe manuscript presents a well-structured and detailed study on the evaluation of electrical stress limit capability in 3D-packaged DDR3 memory. The topic is timely and relevant, and the experimental setup is generally well documented. However, there are several important issues—both technical and editorial—that must be addressed before the manuscript can be considered for publication.
1. Although the study claims to be guided by Reliability Enhancement Theory (RETh), the manuscript does not clearly explain how this theory influences the experimental design or the interpretation of results. The operational and failure limits are defined solely by binary functional outcomes, with no discussion of intermediate degradation behavior or reliability modeling. A deeper theoretical connection and more refined failure criteria are needed.
2. The sample size used in key experiments is too small (e.g., n=3 or fewer), which limits the statistical reliability of the findings. Additionally, no statistical metrics—such as averages, standard deviations, or confidence intervals—are reported. The authors should include these and provide more information on test repeatability and environmental control.
3. The manuscript contains multiple typographical errors and inconsistent terminology (e.g., “pa erns” instead of “patterns”). More importantly, several figures, particularly those illustrating voltage and frequency limit tests (e.g., Figure 4-1, Figure 4-2), are of very poor image quality and are difficult to interpret. These graphs should be replotted and replaced with high-resolution versions. Additionally, figure/table numbering and referencing should be carefully checked throughout.
Author Response
See attachment.
Author Response File: 
Author Response.pdf
Reviewer 2 Report
Comments and Suggestions for AuthorsThis study evaluates the electrical stress limit capability of 3D packaged memory using Reliability Enhancement Theory. It presents a comprehensive test profile, including stress parameters like supply voltage, input clock frequency, and ESD sensitivity. The study also conducts extreme-condition experiments to quantify operational and destructive limits.
Following are my comments :
- Enhance the clarity of the figures.
- The operational limits for voltage were determined to be -1.2V to +2.3V, while failure occurred at -1.1V to +2.4V. What explains this narrow margin between operational and failure thresholds
- In the electrical durability test, no failures were observed after 2000 hours. What is the statistical confidence level in the extrapolated 25 year lifespan, given only three samples were tested?
- How were the activation energy (Ea) and acceleration factor (A) derived? Were these values empirically measured or based on literature for similar devices? If empirical, how was it measured?
- Were any thermal effects observed during voltage/frequency limit testing? If so, how were they mitigated to isolate electrical stress impacts?
- Did you performed any tests repeated to assess reproducibility, especially near the failure thresholds? If so, what variance was observed?
- The tests evaluate voltage, frequency, ESD, and endurance independently. Did you performed any tests under combined stresses such voltage + temperature to better replicate real-world operating conditions?
- The paper reports leakage current values in µA in Tables 4-5/4-6. How did these measured at multiple bias points to confirm ohmic vs. non-ohmic failure modes?
- The test PCBs use 10-12 layers with strict length matching of 50 mil tolerance. Was signal integrity like crosstalk and impedance control, simulated or measured to ensure stress tests were not influenced by PCB artifacts.
Author Response
See attachment.
Author Response File: Author Response.pdf
Round 2
Reviewer 2 Report
Comments and Suggestions for Authorsall my comments have been addressed by the authors.
