An All-Digital Timing Mismatch Calibration Algorithm Based on Reference Channel for TIADC

Abstract

This paper proposes an all-digital calibration algorithm that utilizes a reference channel to suppress the timing mismatch in the Time-Interleaved Analog-to-Digital Converter (TIADC). The output of the reference channel is aligned with each sub-channel in turn, therefore enabling the simultaneous sampling and conversion of the same input signal. First, the statistical characteristics across the channels are employed for estimating the timing mismatch; then, by comparing the output difference between the reference channel and the sub-channels that are sampled simultaneously, the deviation of the derivator can be calibrated. Finally, combining both calibration results yields an accurate final output. This proposed algorithm provides an effective solution to improve TIADC performance in high-speed data acquisition systems. The proposed architecture is applied to a 12-bit 2.4 GS/s four-channel TIADC model, and then its effectiveness is verified. The simulation results exhibit that the Effective Number Of Bits (ENOB) at an input signal frequency of 984 MHz shows a remarkable improvement from 6.88 bits to 11.92 bits. The effectiveness of this technique is also demonstrated through the off-chip calibration of a commercial 12-bit four-channel 2 GS/s TIADC using a 680 MHz input signal that is based on the actual chip results.

1. Introduction

The analog-to-digital converter is a bridge that is applied to convert analog signals into discrete signals [1]. It is widely used in various fields, such as wireless communication, electronic radar, medical equipment, etc. With the progress of the time, the demand for ADC is growing. The essential criteria for ADC are higher precision, higher speed, lower power consumption, etc. It is difficult for a single-structure ADC to incorporate all these three factors in the existing technologies. Fortunately, TIADC can solve this problem effectively [2]. The TIADC can double the sampling rate of the whole ADC, and it can easily reach the sampling rate of 1 GS/s [3].

The TIADC is composed of M sub-channels. Due to the manufacturing process, layout routing, temperature, voltage, and other such factors, mismatches between the sub-channels will occur, such as offset mismatch, gain mismatch, and timing mismatch [3]. Indeed, the degradation of the Signal-to-Noise Ratio (SNR) and Spurious Free Dynamic Range (SFDR) of the output signal are most probably connected to these mismatches. The system as a whole cannot satisfy the demands for high precision and high speed unless these errors are calibrated accurately. The common calibrations for offset and gain mismatches involve the accumulation and averaging of the input signal, and this is followed by its subtraction from the original signal. This approach is both straightforward and efficient [4]. The calibration of timing mismatch is the most challenging compared to other mismatches [2]. Therefore, the architecture proposed in this paper was mainly designed to solve the timing mismatch problem.

The calibration of timing mismatches can be accomplished through methodologies that are akin to those employed in analog loop calibration. The analog loop calibration method primarily involves filtering the TIADC sampling clock, and it is coupled with the adjustment of clock phases through the observation of output discrepancies in the digital domain for each sub-ADC channel. This procedure serves to effectively eliminate sampling timing mismatches [5,6]. Ref. [5] introduced a kind of foreground calibration technology based on an analog auxiliary circuit, which predominantly depended on the filtration efficacy of the analog domain filter circuit with respect to the clock signal. However, this method exhibited significant limitations, and its calibration performance was greatly influenced by temperature variations, process variations, and voltage fluctuations. Ref. [6] introduced a coarse adjustment technique for an analog variable delay line. Nonetheless, the fixed and coarse step sizes in this method imposed limitations on its effective adjustment range, as discerned from experimental analysis.

In contrast, all-digital calibration technology offers high reliability and powerful portability advantages, therefore effectively addressing the aforementioned issues. Several methodologies have been developed to address timing mismatch calibration within an all-digital domain. The investigations of all-digital calibration structures are mainly focused on two parts: the estimation method and the compensation method.

Thereinto, the predominant error estimation methodologies entail the utilization of the cross-correlations among sub-channels [2,3,7,8,9,10,11,12], or the introduction of a reference channel [13,14,15,16]. Based on the correlations among sub-channels, a complex computational matrix is commonly constructed. For example, Ref. [9] introduced an estimation methodology that employs signal modulation for the construction of an error coefficient matrix. Nevertheless, a notable limitation was observed in terms of the sluggish convergence rates (110 k) and constraints associated with finite input bandwidths. Please note that these methods that are predicated on signal modulation or Hadamard matrix operations are infrequently employed in practical applications due to their elevated computational intricacy. Calibration structures that are predicated on reference channels commonly exhibit relative simplicity. The estimation process can be construed as the assessment between a designated sub-channel and the reference channel. The calibration procedure can be delineated as a specialized form of a dual-channel calibration structure, i.e., one that is impervious to the influence of channel count expansion. Notably, this configuration is frequently characterized by diminished hardware consumption. In the paradigm of sub-channel cross-correlation, the escalation in the number of channels engenders an exponential amplification in the complexity of the formulated system of error functions. This not only augments the intricacy of design but also imparts a substantial inefficiency in terms of hardware utilization. Ref. [14] proposed an estimation methodology, one which entailed the application of a high-pass filter for the processing of input slopes that pertained to both the sub-ADC and the reference ADC. However, the reference channel necessitated a significant degree of precision, thus resulting in substantial hardware consumption with many multiplication–addition units in the usage of a high-precision filter case. Additionally, the calibration performance gradually deteriorates with increasing frequency, which is a common issue faced by most calibration structures [3,13,14,15]. Typically, increasing the order of the filter and parallel correlation derivative [6] was employed to mitigate this deterioration, but it inevitably led to an increase in hardware consumption. Ref. [16] proposed an innovative split-based structure. This design segregated an M-channel TIADC into two segments that featured mutually co-prime operating frequencies. At each sampling instance, each segment actively provides a sub-ADC channel as a reference for the other. The utilization of the difference in the outputs from the dual paths serves as a new thought for actively extracting the temporal misalignment information between channels. Ref. [17] proposed a methodology for error computation based on the detection of the monotonic trends in the sampled data from sub-channels and reference channels, whereby they then subsequently applied cumulative difference accumulation. It is noteworthy that this structural approach eliminates the necessity for any multiplication or division operations. However, there have only been a few reports about timing mismatch calibration techniques based on reference channels, and their effectiveness needs further verification and improvement.

Most compensation methods rely on either filtering techniques [18,19,20,21] or Taylor expansion [11,22,23]. Numerous structures of the commonly employed filter are subjects of the study, with a substantial portion of researchers directing their investigations toward fractional-delay filters and perfect-reconstruction filters. Ref. [19] introduced a methodology that employed fractional filters for the phase adjustment in the input signal. Ref. [20] introduced a methodology that utilized the perfect reconstruction filters to efficaciously rectify errors in reconstructed signals. However, this approach consumed high hardware and substantial power. In addition, the structures based on Taylor series expansion are highly regarded for their low complexity, rapid convergence, and notable efficacy, which make them equally popular. Ref. [11] utilized a Taylor series expansion to approximate the error terms within the output signal. The calibration of the errors in the output signal was achieved through the consideration of the time misalignment errors and the derivatives of the input signal. The conventional approach to optimizing the output performance and the input signal bandwidth in calibration algorithms typically relies on the degree of differentiation or the second-order differential term. However, the exponential increase in the hardware consumption has not been positively linked to the commensurate improvements in the input bandwidth.

In this paper, an all-digital calibration structure is proposed to address the aforementioned issues. A reference channel is used to extract the timing mismatch of each sub-channel. The compensation structure is formulated based on the expansion of the first-order Taylor series. The derivator which is optimized with the Richardson extrapolation is based on the first-order numerical differential of the Lagrange interpolation polynomial of the 5-point formula. The optimization of the derivator circuit’s structure, as is outlined in this paper, aims to minimize the hardware consumption and the overall resource utilization. In addition, an auxiliary circuit is introduced to further enhance the output precision and performance, which improves the overall accuracy and efficiency. This design manifests attributes including the expeditious convergence, the compact hardware footprint, and the straightforward architectural framework. This paper is organized as follows. Section 2 describes the construction of the TIADC module and the merits of the proposed calibration technique. Section 3 shows the simulation results which verify the effectiveness of the technique. Section 4 is mainly used to discuss the advantages and disadvantages of the proposed algorithm as well as the direction of the future work. Finally, the conclusions are drawn in Section 5.

2. Timing Mismatch Model and Proposed Timing Mismatch Calibration Structure

Assuming that the prior calibrations with the help of a reference ADC [24] have been made for other mismatches (i.e., offset and gain mismatches), we only need to focus on the calibration of the timing mismatch. Figure 1 shows the structure of the M-channel TIADC with the reference channel. The output of the optimal M-channel TIADC system can be expressed as

$$y_i\left(n\right)=x(n·M{T}_s+i{T}_s+\Delta t_i), i=0,\cdots ,M-1.$$

(1)

Figure 1. The structure of the M channel TIADC. $cl{k}_{M-1}$ is the sample clock of the sub-ADC. $cl{k}_{ref}$ is the sample clock of the reference ADC. S/H stands for the sample holder.

In (1), $y_i\left(n\right)$ is the sampled value of the input signal $x\left(n\right)$ at the time $t=n·M{T}_s+i{T}_s+\Delta t_i$, where $\Delta t_i$ represents the timing mismatch of the $i^{th}$ sub-channel and $T_s$ represents the sampling period. The signal $y\left(n\right)$ of the entire TIADC can be expressed as

$$y\left(n\right)=\sum _{i=0}^{M-1}{y}_i\left(n\right)=\sum _{i=0}^{M-1}x(n·M{T}_s+i{T}_s+\Delta t_i).$$

(2)

In the actual circuit, the timing mismatch is much smaller than $T_s$, $\Delta t_i=r_i{T}_s, r_i\ll 1\%$. $r_i$ represents the timing mismatch coefficient of the $i^{th}$ sub-channel.

2.1. Timing Mismatch Compensation

In practice, the timing mismatch is typically negligible in comparison to the sampling period. As a result, the first-order Taylor series is employed for approximation [6]. The function of the timing mismatch compensation ${\widehat{y}}_i\left(n\right)$ on the $i^{th}$ sub-channel is expressed as

$$\begin{array}{c}\hfill {\widehat{y}}_i\left(n\right)\approx y_i\left(n\right)-\Delta t_i{y}_i^{\prime }\left(n\right),\end{array}$$

(3)

where $y_i^{\prime }\left(n\right)$ represents the differential value of the output from the $i^{th}$ sub-channel. The deviation coefficients of the derivator exhibit frequency-dependent variations during the execution of the differentiation operation [25]. Therefore, the relationship between the output of the derivator ($D_i\left(n\right)$) and the ideal derivative ($y_i^{\prime }\left(n\right)$) can be mathematically expressed as

$$\begin{array}{c}\hfill D_i\left(n\right)=g_D·y_i^{\prime }\left(n\right),\end{array}$$

(4)

where $g_D$ represents the deviation coefficient of the derivator. (3) is rewritten as

$$\begin{array}{c}\hfill {\widehat{y}}_i\left(n\right)\approx y_i\left(n\right)-\frac{1}{g_D}·\Delta t_i·D_i\left(n\right).\end{array}$$

(5)

The deviation coefficient of the derivator is solely dependent on the frequency. Figure 2 shows the implementation architecture of the timing mismatch calibrations.

Figure 2. Proposed calibration system of the timing mismatch and the derivator deviation coefficient with the reference channel.

2.2. Estimation Architecture

In this sub-section, this paper presents an adaptive estimation method that utilizes the first-order statistics to address the timing mismatches. The estimation model is based on a four-channel model with an additional channel for reference. The sampling frequency of TIADC is $f_s$. The sampling frequency of the sub-channel is $f_s/4$. The sampling frequency of the reference channel is $f_s/5$. The sampling values of the reference channel are aligned with each sub-channel in turn. The sampling timing of each sub-channel ADC and the reference channel ADC is illustrated in Figure 3.

Figure 3. TIADC calibration sampling timing.

The specific sampling sequences are extracted through down-sampling. The output sequence $y_{i\_d}\left(n\right)$ of the $i^{th}$ sub-channel after down-sampling is expressed as

$$\begin{array}{cc}\hfill y_{i\_d}\left(n\right)& =y_i(5n-5+i)\hfill \\ \hfill & =x(n·20T_s-(20-5i)T_s+\Delta t_i).\hfill \end{array}$$

(6)

The corresponding output sequence $y_{ref\_di}\left(n\right)$ of the reference channel needs to be extracted accordingly, which can be formulated as

$$\begin{array}{cc}\hfill y_{ref\_di}\left(n\right)& =y_{ref}(4n-4+i)\hfill \\ \hfill & =x(n·20T_s-(20-5i)T_s),\hfill \end{array}$$

(7)

where $y_{ref}\left(n\right)$ represents the output of the reference channel, which can be expressed as

$$\begin{array}{c}\hfill y_{ref}\left(n\right)=x(n·5T_s).\end{array}$$

(8)

The estimation of the timing mismatch requires the utilization of the cross-correlation function between the sub-channel and the reference channel. The reference channel output sequence $y_{ref\_dk}\left(n\right)$ ($k=mod(i+2,4)$ for $i=0,\cdots ,3$, $mod\left(\right)$ stands for modulus function) of the corresponding sub-channel can be denoted as

$$\begin{array}{c}\hfill y_{ref\_dk}\left(n\right)=\left\{\begin{array}{c}{y}_{ref\_d\left\{mod\right(i+2,4\left)\right\}}(n-1),i=0,1\\ y_{ref\_d\left\{mod\right(i+2,4\left)\right\}}(n-0),i=2,3,\end{array}\right.\end{array}$$

(9)

the cross-correlation function $R_{y_{i\_d}(n-1)y_{ref\_dk}(n-1)}$ between the sub-channel and the reference channels after down-sampling, i.e., $y_{i\_d}(n-1)$ and $y_{ref\_dk}(n-1)$, respectively, is expressed as

$$\begin{array}{cc}\hfill R_{y_{i\_d}(n-1)y_{ref\_dk}(n-1)}& =E(y_{i\_d}(n-1)·y_{ref\_dk}(n-1))\hfill \\ \hfill & =R_{xx}(10T_s-\Delta t_i),\hfill \end{array}$$

(10)

where $E\left(·\right)$ expresses the mathematical expectation. It is realized through Modified Moving Average (MMA) [23], which is shown in Figure 4. It is expressed as

$$\begin{array}{c}\hfill y\left[n\right]=(1-\mu )y[n-1]+\mu x\left[n\right],\end{array}$$

(11)

where $y\left[n\right]$ and $x\left[n\right]$ are the output and the input, and $\mu$ represents a constant smoothing factor. The recursive calculation of the average output $y\left[n\right]$ relies on both the preceding result $y[n-1]$ and the current input term $x\left[n\right]$. The (11) is commonly utilized in Digital Signal Processing (DSP), and the recursive calculation of the computing moving averages. In terms of the hardware implementation, opting for a $2^{-k}$ sample period—with k being any positive integer is proved to be advantageous since multiplying the signal by $\mu$ can be efficiently accomplished via the proper arithmetic shifting by k bits instead of employing a hardware multiplier. $R_{xx}(10T_s-\Delta t_i)$ expresses the cross-correlation of $x(n+\Delta t_i)$ and $x(n+10T_s)$. By the first-order Taylor series approximation, it could be approximately expressed as

$$\begin{array}{c}\hfill R_{xx}(10T_s-\Delta t_i)\approx R_{xx}\left(10T_s\right)-\Delta t_i·R_{xx}^{\prime }\left(10T_s\right),\end{array}$$

(12)

where $R_{xx}^{\prime }\left(10T_s\right)$ is the derivative of the autocorrelation of the input signal. It could be expressed as

$$\begin{array}{cc}\hfill R_{xx}^{\prime }\left(10T_s\right)& =E\left(x^{\prime }\left(n\right)x(n-10T_s)\right)\hfill \\ \hfill & =E\left(y_{ref}^{\prime }\left(n\right)y_{ref}(n-2)\right),\hfill \end{array}$$

(13)

where $y_{ref}^{\prime }\left(n\right)$ is the derivative of the reference signal. From (10) and (12), the cross-correlation value between $y_{i\_d}(n-1)$ and $y_{ref\_dk}(n-1)$ is expressed as

$$\begin{array}{c}\hfill R_{y_{i\_d}(n-1)y_{ref\_dk}(n-1)}\approx R_{xx}\left(10T_s\right)-\Delta t_i·R_{xx}^{\prime }\left(10T_s\right).\end{array}$$

(14)

Figure 4. The Modified Moving Average (MMA) filter. $z^{-1}$ stands for the D flip-flop.

Obviously, the cross-correlation value $R_{y_{i\_d}(n-1)y_{ref\_dk}\left(n\right)}$ between $y_{i\_d}(n-1)$ and $y_{ref\_dk}\left(n\right)$ is expressed as

$$\begin{array}{c}\hfill R_{y_{i\_d}(n-1)y_{ref\_dk}\left(n\right)}\approx R_{xx}\left(10T_s\right)+\Delta t_i·R_{xx}^{\prime }\left(10T_s\right).\end{array}$$

(15)

To obtain the timing mismatch, the difference of the cross-correlation values ${\lambda }_{cor\_i}$ can be derived by subtracting the two equations that is mentioned above (i.e., (14) and (15)):

$$\begin{array}{c}\hfill {\lambda }_{cor\_i}=2\Delta t_i·R_{xx}^{\prime }\left(10T_s\right),\end{array}$$

(16)

which is in direct proportion to $\Delta t_i$.

Approximately, the timing mismatch $\Delta t_i$ can be represented as

$$\begin{array}{c}\hfill \Delta t_i=\frac{{\lambda }_{cor\_i}}{2R_{xx}^{\prime }\left(10T_s\right)}.\end{array}$$

(17)

The implementation architecture of (17) is shown in Figure 5.

Figure 5. Proposed architecture of the timing mismatch.

2.3. Derivator Architecture

The traditional derivator is essentially a filter, which consists of the multiplier and the delay register units. Considering that the differentiation effect of the derivator increases with its order, it inevitably consumes a large amount of the aforementioned filters to obtain a sufficiently high order (e.g., [2,6]) and meet the requirements of the design. This paper proposes a simplified structure of the derivator. According to the Lagrange interpolation polynomial, the first-order numerical differentiation can be expressed as [26]

$$\begin{array}{c}\hfill D_0\left(n,1\right)=\frac{y\left(n-2\right)-8y\left(n-1\right)+8y\left(n+1\right)-y\left(n+2\right)}{12},\end{array}$$

(18)

where $D_0\left(n,1\right)$ represents the output of the derivator. By the usage of the Taylor series expansion, the terms $y(n-2)$, $y(n-1)$, $y(n+1)$, and $y(n+2)$ can be effectively expanded. Consequently, (18) can be elegantly reformulated as

$$\begin{array}{c}\hfill D_0(n,1)\approx y^{\prime }\left(n\right)-\frac{3}{5!}{y}^{\left(5\right)}\left(n\right)-\frac{15}{7!}{y}^{\left(7\right)}\left(n\right)+\cdots ,\end{array}$$

(19)

where $y^{\prime }\left(n\right)$ is the derivative of $y\left(n\right)$, similarly, $y^{\left(5\right)}\left(n\right)$ and $y^{\left(7\right)}\left(n\right)$ are the fifth-order and seventh-order derivative of $y\left(n\right)$, respectively. To enhance the differentiation effect of the derivator, the Richardson extrapolation is employed to construct the higher-order approximation formulas [27]. It estimates the value of the target function by approximation with different step lengths. The first order numerical differential formula $D_m(n,h)$ from a higher-precision extrapolation can be expressed as

$$\begin{array}{c}\hfill D_m(n,h)=\frac{4^{m+1}{D}_{m-1}(n,\frac{h}{2})-D_{m-1}(n,h)}{4^{m+1}-1},\end{array}$$

(20)

where h represents the sampling step and m represents the number of the iterations. As the number of the iterations increases, the output of the derivator gradually converges to the ideal derivative value. The following expression for the output of the derivator $D_1(n,2)$ can be derived by the single iteration:

$$D_1(n,2)=\frac{16D_0(n,1)-D_0(n,2)}{15},$$

(21)

where $D_0(n,2)$ is expressed as [26]

$$\begin{array}{c}\hfill D_0(n,2)=\frac{y(n-4)-8y(n-2)+8y(n+2)-y(n+4)}{24}.\end{array}$$

(22)

Subsequently, $D_1(n,2)$ can be obtained from the Taylor series expansions of $D_0(n,1)$ and $D_0(n,2)$, as is described below.

$$\begin{array}{c}\hfill D_1(n,2)\approx y^{\prime }\left(n\right)+\frac{3}{7!}{y}^{\left(7\right)}\left(n\right)+....\end{array}$$

(23)

By comparing (19) and (23), the application of the Richardson extrapolation formula eliminates a certain amount of higher-order derivatives (e.g., $y^{\left(5\right)}\left(n\right)$) and enhances the accuracy of the derivator so that the compensation performance can be improved effectively. By substituting (18) and (22) into (21), the expression can be derived as follows:

$$\begin{array}{cc}\hfill D_1(n,2)=& \{2^4·[(y(n-2)-y(n+2))\hfill \\ \hfill & -2^3·(y(n-1)-y(n+1))]\hfill \\ \hfill & -\left[y\right(n-4)-y(n+4\left)\right)\hfill \\ \hfill & -2^3·(y(n-2)-y(n+2))\left]\right\}·\frac{1}{180}.\hfill \end{array}$$

(24)

The implementation architecture of (24) is shown in Figure 6.

Figure 6. Proposed architecture of the derivator.

2.4. Derivator Calibration

The linearity of the derivator gradually deteriorates with the increase of the frequency. The non-negligible deviation between the actual and ideal output of the derivative significantly impacts the accuracy of the final compensation and calibration. To compensate for the output deviation at the high-frequency cases, this paper presents a straightforward structure for the calibration of the derivator.

The deviation coefficient of the derivator is solely dependent on the frequency and is unrelated to any channel. Take Channel 3, for example. The sequence $y_{ref\_d3}\left(n\right)$ after down-sampling is selected. It is aligned with Channel 3, which is written as

$$\begin{array}{c}\hfill y_{ref\_d3}\left(n\right)=y_{ref}(4n-1)=x(n·20T_s-5T_s).\end{array}$$

(25)

Similarly, the sampling sequence $y_{3\_d}\left(n\right)$ that is corresponding to Channel 3 is expressed as

$$\begin{array}{c}\hfill y_{3\_d}\left(n\right)=y_3(5n-2)=x(n·20T_s-5T_s+\Delta t_3).\end{array}$$

(26)

The timing mismatch has been rectified after the compensation with the Taylor series, whereas the derivator still exhibits a frequency-dependent bias coefficient. The corresponding output of the derivator $D_{3\_d}\left(n\right)$ is written as

$$\begin{array}{c}\hfill D_{3\_d}\left(n\right)=g_D·y_{3\_d}^{\prime }\left(n\right)=g_D·x^{\prime }(n·20T_s-5T_s+\Delta t_3).\end{array}$$

(27)

Using Taylor series expansion and combining (25) and (27), the following results can be derived as

$$\begin{array}{c}\hfill y_{ref\_d3}\left(n\right)=y_{3\_d}\left(n\right)-\Delta t_3·\frac{D_{3\_d}\left(n\right)}{g_D}.\end{array}$$

(28)

The expectation of the deviation coefficient can be expressed as

$$\begin{array}{cc}\hfill \frac{1}{g_D}& =\frac{1}{N}·\sum _{n=1}^N\left(\frac{y_{3\_d}\left(n\right)-y_{ref\_d3}\left(n\right)}{\Delta t_3·D_{3\_d}\left(n\right)}\right)\hfill \\ \hfill & =\frac{E\left(y_{3\_d}\left(n\right)\right)-E\left(y_{ref\_d3}\left(n\right)\right)}{E\left(\Delta t_3·D_{3\_d}\left(n\right)\right)},\hfill \end{array}$$

(29)

where the expectation of $E\left(y_{3\_d}\left(n\right)\right)$, $E\left(y_{ref\_d3}\left(n\right)\right)$ and $E\left(\Delta t_3·D_{3\_d}\left(n\right)\right)$ are constants on account of the input signal $x\left(n\right)$ that is band-limited. The calibration architecture of the derivator’s deviation according to (29) is shown in Figure 7.

Figure 7. Proposed architecture of the derivator calibration.

3. Performance Verification

To verify the validity of the technology, the ideal output of the TIADC is systematically generated through the MATLAB. Different timing mismatches are deliberately introduced to the outputs of each channel, and conventional simulations are strictly conducted using the MATLAB environment. The TIADC output signals, deviations across all channels, and the comprehensive calibration architecture are synthesized through the MATLAB 2023a software (Section 3.1). To enhance the validation of the algorithm’s reliability, this paper employs a commercial TIADC from our company as the data source for evaluating the proposed calibration algorithm (Section 3.2). The design of this TIADC is accomplished through the Cadence Virtuoso ic617 software. The effective calibration results also serve to illustrate the reliability of the algorithm.

3.1. Simulation

In this section, a 12-bit 2.4 GS/s four-channel TIADC model with the timing mismatches is constructed to verify the effectiveness of the proposed estimation and the compensation architecture. The sampling frequency of each subchannel is 600 MS/s and the reference channel is 480 MS/s.

Figure 8 shows the spectra of a single-tone signal with a frequency of 0.41f_s. The timing mismatches of the four channels $[\Delta t\text{\_0},\Delta t\text{\_1},\Delta t\text{\_2},\Delta t\text{\_3}]$ are set as [1‰, −2‰, 3‰, −4‰]. After calibration, the harmonics that are caused by the timing mismatches decrease substantially. The SFDR and SNR increase from 43.81 dB and 43.17 dB to 89.39 dB and 73.50 dB, respectively.

Figure 8. The spectra of four-channel TIADC output for a single-tone signal input of 0.41$f_s$ (a) before calibration and (b) after calibration.

Near the boundary of the Nyquist frequency band, the performance of the derivator significantly decreases, which contributes to a substantial drop in the output efficiency (Figure 9a). Compared to the uncalibrated case, the SFDR (SNR) after all-digital timing mismatch calibration without the derivator calibration module increased from 42.85 dB (42.21 dB) to 64.08 dB (62.93 dB), indicating a modest improvement. In contrast, the circuit that introduces the derivator-assisted calibration (Figure 9) raises the SFDR and SNR to 86.96 dB and 73.67 dB, as illustrated in Figure 9b. This brings substantial improvements to derivative calibration.

Figure 9. The spectra of four-channel TIADC output for a single-tone signal input of 0.45$f_s$ (a) without the derivator calibration and (b) with the derivator calibration.

Figure 10a shows the convergence rate of the timing mismatches. In the actual simulation, the channel rotation method is used to estimate the timing mismatch of each channel. It can be observed that the typical channel switches after approximately 300 samples. The convergence rate of the derivator’s deviation coefficient is shown in Figure 10b, and the convergence samples are approximately 2000. The entire system reaches convergence at approximately 3200 samples. The deviation value $1/g_D$ is around 1.075 when the $f_{in}$ is 0.41$f_s$.

Figure 10. (a) The convergence rate of the time mismatch error. (b) The convergence rate of the derivator’s deviation coefficient.

Figure 11 shows a significant improvement of the SNR and SFDR under different frequencies. The output performance shows little difference at the low frequencies, but the unmodified structure exhibits a noticeable decrease in performance at the higher frequencies. Moreover, the proposed calibration architecture effectively maintains a stable and high level of the SNR and SFDR in almost the entire Nyquist domain.

Figure 11. (a) The SNR and (b) SFDR performance versus different input frequencies.

Figure 12 shows the spectra of the four-channel TIADC output for the multi-tone signal input. The frequencies in Figure 12 are $[0.088f_s, 0.161f_s, 0.222f_s, 0.283f_s]$. As can be seen, the spurs from the timing mismatches are effectively suppressed.

Figure 12. The spectra of four-channel TIADC output for multi-tone signal input (a) before calibration and (b) after calibration. (The red line signifies the signal, and the blue line signifies the spur).

3.2. Hardware Implementation and Validation

The Verilog design is synthesized to a gate-level netlist by Synopsys Design Compiler (DC) tool that targets the 28 nm technology. The design target of Application Specific Integrated Circuit (ASIC) for the calibration structure is a 12-bit 2.4 GS/s four-channel TIADC. The synthesis result shows that the area of the proposed structure is 0.03 mm².

The off-chip calibration of a commercial four-channel 12-bit TIADC is performed on the Field Programmable Gate Array (FPGA). The JESD204B interface is also applied for the high-speed signal transmission between the TIADC and the FPGA (VCU108 from Xilinx). The input signal is a 680 MHz sine wave sampled at the frequency of 2 GS/s. Figure 13 shows the test platform that is comprised of the TIADC chip, the clock chip, the Serial Peripheral Interface (SPI) controller, and the FPGA circuit board.

Figure 13. Experimental setup for the off-chip timing mismatch calibration of the four-channel 2 GS/s TIADC.

Based on the measured data from the 2 GS/s four-channel 12-bits TIADC, the proposed method is used for the off-chip calibration. The input is a single-tone signal with a frequency of 680 MHz (=$0.34f_s$). Figure 14 shows the off-chip calibration results of the commercial TIADC. It can be seen that the spurs caused by the timing mismatch at the frequencies of 0.09$f_s$, 0.16$f_s$ and 0.41$f_s$ are reduced by 15.09 dB, 26.67 dB, and 12.65 dB, respectively.

Figure 14. The off-chip calibration results of the commercial TIADC with the input signal being 680 MHz and the sampling rate being 2 GS/s (a) before calibration and (b) after calibration.

4. Discussion

Table 1 presents the other four works on the all-digital calibration techniques that have been proposed in recent years. Compared to the works of other groups [9,12], this paper presents several significant advantages over the structure with the reference channel, especially in the area consumption and the convergence speed. Compared to Ref. [28], it achieves superior calibration results while maintaining the same level of the accuracy. A significant improvement in calibration performance for the multi-frequency signals is also observed. Compared to Ref. [9], this paper presents a faster convergence speed and wider effective bandwidth. As mentioned, the techniques in Refs. [9,28,29] fail to maintain high-precision output at the high frequencies, which result in a noticeable degradation in the calibration performance. By contrast, the proposed technique solves this issue.

Table 1. Simulation Performance Comparison.

	[9]	[28]	[29]	[30]	[31]	This Work
Channels	4	4	4	4	4	4
Resolution	12 bits	12 bits	6 bits	12 bits	14 bits	12 bits
Timing mismatch	$-0.012$·$T_s$	$-0.025$·$T_s$	$-0.018$·$T_s$	$-0.031$·$T_s$	$-0.015$·$T_s$	$-0.004$·$T_s$
Sample frequency	3 GS/s	∖	32 GS/s	2 GS/s	3 GS/s	2.4 GS/s
Input frequency	$0.282$·$f_s$	$0.410$·$f_s$	$0.495$·$f_s$	$0.437$·$f_s$	$0.435$·$f_s$	$0.459$·$f_s$
Multi-tone input	Yes	No	No	No	No	Yes
Convergence time (samples)	15 k	110 k	24 k	1.2 k	600	3.2 k
SFDR	77.69 dB	64.10 dB	37.24 dB	85.69 dB	109.30 dB	86.96 dB
SNR	71.00 dB	62.21 dB	31.28 dB	67.96 dB	79.95 dB	73.63 dB
ENOB	11.50 bits	10.04 bits	5.44 bits	11.00 bits	12.98 bits	11.93 bits
Area	0.047 mm2	∖	0.695 mm2	0.02 mm2	∖	0.03 mm2

Relative to the calibration methodologies that have been recently reported by our group, the algorithm in this article shows significant advantages [30,31]. In contrast to the approach in Ref. [30], the feedback architecture is employed to approximate the parameters to the actual values, despite inherent stability concerns. By utilizing a feedforward calibration structure, this paper systematically enhances the stability and improves the entire performance of the calibration process. Relative to the framework in Ref. [31], the proposed structure is characterized by its simplicity, low computational complexity, rapid convergence, and superior performance. The calibration structures in Refs. [30,31] present limited efficacy in the multi-frequency signals calibration, therefore imposing significant constraints on their practical applications. In contrast, the calibration architecture in this paper demonstrates the superior effectiveness in the context of the multi-frequency signals calibration.

Although the inclusion of the reference channel is a notable drawback in comparison to the structure without one, it has been demonstrated to be a strong-expansible and straight structure. The application of the method from Ref. [2] to systems with more than 8 channels generates an exponential increase in hardware resource consumption at both the estimation module for derivative poly-phase filters and the matrix processing unit. However, the proposed structure in this paper can be expanded to accommodate additional channels without incurring any extra hardware consumption within the estimation module.

Given all that, this paper sufficiently validates the effectiveness of the algorithm by the co-simulation of the MATLAB and off-chip measured data. Compared with other literature [9,28,29], the all-digital calibration framework in this paper demonstrates the notable advantages in terms of convergence speed, SFDR, SNR, hardware resource efficiency, and multi-frequency signals calibration. However, the approaches involve additional channels, necessitating a more complex layout, especially concerning the clock tree. In the context of the future endeavors, the forthcoming work will involve the refinement of the existing algorithmic framework, with a particular emphasis on optimizing both the area utilization and the performance. Our calibration methodology is slated for the implementation leveraging an ASIC library.

5. Conclusions

This paper has proposed an all-digital calibration structure of the four-channel TIADC. It effectively addresses the frequency-dependent challenges in compensating for the timing mismatch calibration. Herein, we present a novel estimation method that exploits statistical regularities among individual sub-channels and a reference channel to accurately determine time mismatches. This methodology presents a streamlined architecture with swift convergence rates and robust stability, rendering it exceptionally well-suited for integration into the commercial TIADC. Additionally, an innovative compensation framework we proposed is grounded in the first-order Taylor series expansion. The derivator is refined through the utilization of the Richardson extrapolation, employing the first-order numerical differentiation of the Lagrange interpolation polynomial. The derivator auxiliary circuit is incorporated to improve the accuracy of the derivator and optimize hardware consumption. The simulation that is applied to the 12-bits 2.4 GS/s TIADC demonstrates its effective calibration performance at both the single and the multiple frequencies. The SFDR and SNR at a specific frequency ($0.41f_s$) present an increase of 45.58 dB and 30.33 dB, respectively. Furthermore, the effectiveness of this approach is further substantiated through the off-chip calibration based on the actual TIADC. Moreover, its versatility is manifested in having freedom from the objective restraints, such as the number of channels, input signal amplitude, input frequency, etc. The system possesses the remarkable ability to consistently maintain optimal performance even at high frequencies.