Next Article in Journal
Threat Modeling of a Smart Grid Secondary Substation
Next Article in Special Issue
Evaluating Cu Printed Interconnects “Sinterconnects” versus Wire Bonds for Switching Converters
Previous Article in Journal
Selected Energy Consumption Aspects of Sensor Data Transmission in Distributed Multi-Microcontroller Embedded Systems
Previous Article in Special Issue
Simulation of TSV Protrusion in 3DIC Integration by Directly Loading on Coarse-Grained Phase-Field Crystal Model
Article

Die-Level Thinning for Flip-Chip Integration on Flexible Substrates

1
Silicon Austria Labs GmbH, Europastrasse 12, A-9524 Villach, Austria
2
Institute for Smart Systems Technologies, Alpen-Adria-Universität Klagenfurt, A-9020 Klagenfurt, Austria
3
School of Engineering, Institute for Integrated Micro and Nano Systems, University of Edinburgh, Edinburgh EH9 3FF, UK
4
Alpen-Adria-Universität Klagenfurt-Silicon Austria Labs, Ubiquitous Sensing Systems Lab, A-9020 Klagenfurt, Austria
*
Author to whom correspondence should be addressed.
Academic Editor: Matteo Meneghini
Electronics 2022, 11(6), 849; https://doi.org/10.3390/electronics11060849
Received: 2 February 2022 / Revised: 28 February 2022 / Accepted: 4 March 2022 / Published: 8 March 2022
Die-level thinning, handling, and integration of singulated dies from multi-project wafers (MPW) are often used in research, early-stage development, and prototyping of flexible devices. There is a high demand for thin silicon devices for several applications, such as flexible electronics. To address this demand, we study a novel post-processing method on two silicon devices, an electrochemical impedance sensor, and Complementary Metal Oxide Semiconductor (CMOS) die. Both are drawn from an MPW batch, thinned at die-level after dicing and singulation down to 60 µm. The thinned dies were flip-chip bonded to flexible substrates and hermetically sealed by two techniques: thermosonic bonding of Au stud bumps and anisotropic conductive paste (ACP) bonding. The performance of the thinned dies was assessed via functional tests and compared to the original dies. Furthermore, the long-term reliability of the flip-chip bonded thinned sensors was demonstrated to be higher than the conventional wire-bonded sensors. View Full-Text
Keywords: ultra-thin-chips; multi-project wafers; hybrid integration; thermoconic flip chip; anisotropic conductive adhesives; flexible electronics; flip chip bonding ultra-thin-chips; multi-project wafers; hybrid integration; thermoconic flip chip; anisotropic conductive adhesives; flexible electronics; flip chip bonding
Show Figures

Figure 1

MDPI and ACS Style

Malik, M.H.; Tsiamis, A.; Zangl, H.; Binder, A.; Mitra, S.; Roshanghias, A. Die-Level Thinning for Flip-Chip Integration on Flexible Substrates. Electronics 2022, 11, 849. https://doi.org/10.3390/electronics11060849

AMA Style

Malik MH, Tsiamis A, Zangl H, Binder A, Mitra S, Roshanghias A. Die-Level Thinning for Flip-Chip Integration on Flexible Substrates. Electronics. 2022; 11(6):849. https://doi.org/10.3390/electronics11060849

Chicago/Turabian Style

Malik, Muhammad H., Andreas Tsiamis, Hubert Zangl, Alfred Binder, Srinjoy Mitra, and Ali Roshanghias. 2022. "Die-Level Thinning for Flip-Chip Integration on Flexible Substrates" Electronics 11, no. 6: 849. https://doi.org/10.3390/electronics11060849

Find Other Styles
Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.

Article Access Map by Country/Region

1
Back to TopTop