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Article
Peer-Review Record

Die-Level Thinning for Flip-Chip Integration on Flexible Substrates

Electronics 2022, 11(6), 849; https://doi.org/10.3390/electronics11060849
by Muhammad Hassan Malik 1,2, Andreas Tsiamis 3, Hubert Zangl 2,4, Alfred Binder 1, Srinjoy Mitra 3 and Ali Roshanghias 1,*
Reviewer 1: Anonymous
Reviewer 2: Anonymous
Electronics 2022, 11(6), 849; https://doi.org/10.3390/electronics11060849
Submission received: 2 February 2022 / Revised: 28 February 2022 / Accepted: 4 March 2022 / Published: 8 March 2022
(This article belongs to the Special Issue Interconnects for Electronics Packaging)

Round 1

Reviewer 1 Report

The core value of this work is its comparative study on three different bonding/integration methods. This touches down a fundamental technical challenge in flexible electronics and the results are of great interest to readers. I suggest the authors to tweak several places before publication. 

  1. Reconsider its title. The current one seems focus on "thinning" rather than "flipchip integration", whereas the manuscript highlights the later.
  2. Introduction and Figure 1: more references/background knowledge is helpful to understand why "thinner" chips is favored on a flexible substrate: is it a result of the increasing flexibility of the chip itself, or because of a reduced mechanical mismatch at the chip/substrate interface upon bending?
  3. Cavity. More dimensional information is required, particular interest is the depth. 
  4. Impedance results. None of integration methods ensures a same exposure area of the IDE electrode. This is likely to be one cause for impedance variations, and should be pointed out in the discussion. 
  5. Failure bonding. In figure 9 c, providing a similar cross-sectional SEM of the Sensor-Epoxy interface before the immersion study can be straightforward to assess contamination issues. 
  6.  

Author Response

Please see the attachment 

Author Response File: Author Response.pdf

Reviewer 2 Report

The manuscript reports the die-level thinning for flip-chip integration on flexible substrates. The results are interesting. However, The chips are not easy to handle. Some of comments have to address as following:

  1. I-V characteristics are required to discuss the leakage current after thinning treatment.
  2. Pictures of IDE and surface of die in magnification before and after thinning treatment are required. Any peeling, damage, and scratch?
  3. How about yield for die-level thinning?
  4. For flexible substrate, how about the electrical characteristics in bending situation?

Therefore, I recommend it as major revision to publish.

Author Response

Pleases see the attachment 

Author Response File: Author Response.pdf

Round 2

Reviewer 2 Report

The manuscript has revised well. Therefore, in my opinion, the article be accepted to publish.

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