Article Versions Notes

Hsieh T-Y, Hsieh P-Y, Yang C-C, Shen C-H, Shieh J-M, Yeh W-K, Wu M-C. Correction: Hsieh et al. Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits. Micromachines 2020, 11, 741. Micromachines. 2025; 16(5):537. https://doi.org/10.3390/mi16050537

Hsieh, Tung-Ying, Ping-Yi Hsieh, Chih-Chao Yang, Chang-Hong Shen, Jia-Min Shieh, Wen-Kuan Yeh, and Meng-Chyi Wu. 2025. "Correction: Hsieh et al. Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits. Micromachines 2020, 11, 741" Micromachines 16, no. 5: 537. https://doi.org/10.3390/mi16050537

Hsieh, T.-Y., Hsieh, P.-Y., Yang, C.-C., Shen, C.-H., Shieh, J.-M., Yeh, W.-K., & Wu, M.-C. (2025). Correction: Hsieh et al. Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits. Micromachines 2020, 11, 741. Micromachines, 16(5), 537. https://doi.org/10.3390/mi16050537