Structure Optimization of Planar Nanoscale Vacuum Channel Transistor
Abstract
:1. Introduction
2. Materials and Methods
2.1. Simulation
2.2. Fabrication of NVCT
2.3. Characterization
3. Results and Discussion
3.1. Optimization of Emitter Morphology
3.2. Device Performance Measurement
3.3. Optimization of Back-Gate NVCT
3.4. Optimization of Side-Gate NVCT
4. Conclusions
Author Contributions
Funding
Data Availability Statement
Acknowledgments
Conflicts of Interest
References
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Xu, J.; Lin, C.; Li, Y.; Zhao, X.; Shi, Y.; Zhang, X. Structure Optimization of Planar Nanoscale Vacuum Channel Transistor. Micromachines 2023, 14, 488. https://doi.org/10.3390/mi14020488
Xu J, Lin C, Li Y, Zhao X, Shi Y, Zhang X. Structure Optimization of Planar Nanoscale Vacuum Channel Transistor. Micromachines. 2023; 14(2):488. https://doi.org/10.3390/mi14020488
Chicago/Turabian StyleXu, Ji, Congyuan Lin, Yu Li, Xueliang Zhao, Yongjiao Shi, and Xiaobing Zhang. 2023. "Structure Optimization of Planar Nanoscale Vacuum Channel Transistor" Micromachines 14, no. 2: 488. https://doi.org/10.3390/mi14020488