An Averaged-Value Model of an Asymmetrical Hybrid Multi-Level Rectifier

Abstract

The development and the validation of an averaged-value mathematical model of an asymmetrical hybrid multi-level rectifier is presented in this work. Such a rectifier is composed of a three-level T-type unidirectional rectifier and of a two-level inverter connected to an open-end winding electrical machine. The T-type rectifier, which supplies the load, operates at quite a low switching frequency in order to minimize inverter power losses. The two-level inverter is instead driven by a standard sinusoidal pulse width modulation (SPWM) technique to suitably shape the input current. The two-level inverter also plays a key role in actively balancing the voltage across the DC bus capacitors of the T-type rectifier, making unnecessary additional circuits. Such an asymmetrical structure achieves a higher efficiency compared to conventional PWM multilevel rectifiers, even considering extra power losses due to the auxiliary inverter. In spite of its advantageous features, the asymmetrical hybrid multi-level rectifier topology is a quite complex system, which requires suitable mathematical tools for control and optimization purposes. This paper intends to be a step in this direction by deriving an averaged-value mathematical model of the whole system, which is validated through comparison with other modeling approaches and experimental results. The paper is mainly focused on applications in the field of electrical power generation; however, the converter structure can be also exploited in a variety of grid-connected applications by replacing the generator with a transformer featuring an open-end secondary winding arrangement.

1. Introduction

Multi-level converters have proved in the last decades to be a viable alternative to conventional topologies in medium-voltage, high-power, industrial applications, but today, their field of applications is rapidly spreading toward low-power and low-voltage ranges. Main advantages of multi-level converters are basically those of an improved harmonic content of AC voltages and currents and of a reduction of power switch voltage ratings [1,2], the main drawback being a greater complexity. Open-winding (OW) configurations, consisting of an AC machine fed by two power converters [3,4,5,6], can be deemed as a special kind of multi-level converter [7]. Different configurations, control schemes, and modulation techniques dealing with OW systems have been discussed in the literature [8,9,10]. Some OW configurations embedding multi-level converters have also been recently developed [11,12,13]. Among them, a high efficiency asymmetrical hybrid multilevel inverter for motor drives has been presented and analyzed in [12] featuring a particular asymmetrical structure where two different kinds of converters are connected at the two sides of an OW AC machine with different functions. Specifically, a main multilevel converter supplies the load, and an auxiliary two-level inverter acts as an active power filter. Such an approach has also been used in [13] to realize an asymmetrical hybrid unidirectional T-type rectifier (AHUTR) for gen-set applications, tailored around an open-end winding permanent magnet synchronous generator (PMSG), as shown in Figure 1. According to the AHUTR topology, the open-end winding PMSG on one side supplies the electrical load through the main converter, a T-type rectifier (TTR), also commonly known as a Vienna rectifier, and on the other side, it is connected to an auxiliary two-level inverter (TLI). The main converter processes the whole power delivered to the load, and thus, it is operated at the fundamental frequency in order to minimize the switching power losses. The TLI is instead driven by a high switching frequency PWM technique to suitably shape the phase currents. Therefore, a stable output DC voltage and almost sinusoidal input currents are obtained, achieving a higher efficiency than comparable conventional PWM rectifiers [12]. The AHUTR structure is also of general applicability, being exploitable in grid-connected applications by replacing the generator with a transformer featuring an open-end secondary winding, as shown in Figure 1, but it is more complex than conventional rectifiers, requiring suitable mathematical tools for control and optimization purposes. The aim of this work is thus to provide an essential tool for the design of the control system of an AHUTR by developing an averaged-value model (AVM) of the system. In general, averaged-value techniques approximate the model of a switching converter to a continuous system by considering the values taken by the variables along a switching period as constant. They are useful when designing and testing control algorithms, as well as to develop efficiency optimization techniques, because a high frequency dynamic analysis is not required, differently than power circuits and filters design. Specifically, an AHUTR AVM has been developed with the aim to support the design of effective solutions to maximize system efficiency, to provide a stable DC output voltage, to cancel low-order undesired harmonics from the phase currents, to equalize the Vienna rectifier DC bus capacitor voltages, and to control the TLI DC bus voltage. Furthermore, the developed model is valuable in tuning voltage and current regulators.

2. Asymmetrical Hybrid Unidirectional T-Type Rectifier

According to Figure 1, an AHUTR supplies the load through a Vienna rectifier switching at fundamental frequency. In electricity generation applications, this rectifier is connected to one end of an open winding electrical generator, very often a PMSG. For grid-connected applications, the electrical generator is replaced by a transformer with an open-end secondary winding. While remarkably reducing the switching power losses, low switching frequency operations would, however, produce highly distorted phase currents. This is prevented by an active power filter based on a conventional TLI, which is connected to the other end of the electrical machine winding. Such an inverter features a lower DC bus voltage compared to the Vienna rectifier and exploits a floating capacitor to reduce the complexity of the system and to prevent the occurrence of zero sequence currents [11,12,13]. The efficiency of the Vienna rectifier can be increased by using low on-state voltage drop power devices, thus optimizing the design of this converter for low conduction power losses. On the other hand, the design of the TLI can be optimized for high switching frequency operation, by using fast power devices with lower voltage ratings. A key feature of the AHUTR topology is that the voltages of the two Vienna rectifier DC bus capacitors can be independently regulated through the TLI, thus making unnecessary additional power converters or special PWM strategies.

In the AHUTR topology, three bidirectional switches S_ij, (i = a, b, c and j = 1, 2) are connected between the midpoint n′ of the Vienna rectifier and the rectifier poles [14]. The generic i-phase voltage V_iTTR between the rectifier input terminal i_M and the mid-point n″ of the Vienna rectifier DC bus is given by

$$V_{iTTR}=\frac{{l_i}^{\prime }-1}{2}{V_{DC}}^{\prime },\hspace{1em}{l_i}^{\prime }=0,\hspace{0.17em}1,\hspace{0.17em}2$$

(1)

where V_DC′ is the DC bus voltage. Hence, three different levels can be taken by the Vienna rectifier input voltage, namely: −V_DC′/2, V_DC′/2, and 0, according to the rectifier i-pole state l_i′.

On the TLI side, the voltage between the TLI i-phase output terminal i_T and the mid-point n′ of the TLI DC bus is given by:

$$V_{iTLI}=\frac{2{l_i}^{″}-1}{2}{V_{DC}}^{″},\hspace{1em}{l_i}^{″}=0,\hspace{0.17em}1$$

(2)

providing two voltage levels, namely, −V_DC″/2 and V_DC″/2, according to the inverter i-pole state l_i″.

The voltage across a phase winding is given by

$$V_{ig}=V_{iTTR}-V_{iTLI}-V_{n^{\prime }{n}^{″}}=\frac{{l_i}^{″}-1}{2}{V_{DC}}^{\prime }-\frac{{{2l}_i}^{″}-1}{2}{V_{DC}}^{″}-V_{n^{\prime }{n}^{″}}$$

(3)

where V_DC′ and V_DC″ are the DC bus voltages of the Vienna rectifier and the TLI, respectively, and V_n′n″ is the voltage between the mid points n′ and n″ of the two DC buses, which can be expressed as

$$V_{n^{\prime }{n}^{″}}=\frac{1}{3}\left(V_{aTTR}+V_{bTTR}+V_{cTTR}\right)-\frac{1}{3}\left(V_{aTLI}+V_{bTLI}+V_{cTLI}\right).$$

(4)

According to (2) and (3), the OW structure of Figure 1, featuring twelve power switches, is equivalent to a six-level neutral point clamped (NPC) or flying capacitor (FC) converter, which would, however, encompass thirty power switches [12]. As shown in Figure 2, the AHUTR requires a complex control system to suitably coordinate the operations of the two converters in order to regulate the DC output voltage, to cancel low-order harmonics from phase currents, to equalize the Vienna rectifier DC bus capacitor voltages, and to control the TLI DC bus voltage [14,15].

3. Averaged-value Model of the System

The averaged-value mathematical model of the system includes three sub-models: of the electrical machine, of the Vienna rectifier, and of the TLI.

3.1. Open-Winding PMSG Model

It is assumed that the stator windings produce sinusoidal magnetomotive forces; moreover, effects of the saturation of the magnetic core are neglected. Under these assumptions, the surface-mounted PMSG model in an orthogonal qd reference frame synchronous to the rotor flux is given by the following sets of Equations:

$$\begin{array}{l}{V}_{qs}=R_s{i}_{qs}+\frac{d}{dt}{\lambda }_{qs}+{\omega }_{re}{\lambda }_{ds}\\ V_{ds}=R_s{i}_{ds}+\frac{d}{dt}{\lambda }_{ds}-{\omega }_{re}{\lambda }_{qs}\end{array}$$

(5)

$$\begin{array}{l}{\lambda }_{qs}=L_s{i}_{qs}\\ {\lambda }_{ds}=L_s{i}_{ds}+{\lambda }_{pm}\end{array}$$

(6)

$$\begin{array}{l}{T}_e=\frac{3}{2}pp({\lambda }_{ds}{i}_{qs}-{\lambda }_{qs}{i}_{ds})\\ T_e-T_L=J\frac{d}{dt}{\omega }_r+F{\omega }_r\end{array}$$

(7)

where i_qs, i_ds, V_qs, V_ds, λ_qs, and λ_ds are the components of stator current, voltage, and flux in the qd axis; L_s is the stator inductance; λ_pm is the linkage flux of permanent magnets; T_e is the electromagnetic torque; J is the total mechanical inertia; F is the rotor friction; ω_re = ppω_r is the rotor speed; and pp is the amount of pole pairs. The rotational terms ω_reλ_ds and ω_reλ_qs account for the qd axis back-emf E_q and E_d, respectively.

The averaged-value PMSG phase voltage V_ig is obtained as the difference between the fundamental harmonic ${\overline{V}}_{iTTR}$ of the Vienna rectifier input voltage and the fundamental harmonic ${\overline{V}}_{iTLI}$ of the TLI output voltage. The voltage V_n′n″ between the mid points of the two DC buses can be neglected for averaged-value analysis, since it only includes high frequency harmonics [13].

PMSG phase voltages can be expressed in a qd synchronous reference frame to the back-EMF vector as a function of qd components of voltages ${\overline{V}}_{iTTR}$ and ${\overline{V}}_{iTLI}$ by:

$$\left|\begin{array}{c}{\overline{V}}_{qTTR}\\ {\overline{V}}_{dTTR}\end{array}\right|=\frac{2}{3}\left|\begin{array}{ccc}\cos ({\omega }_{re}t)& \cos ({\omega }_{re}t-\frac{2}{3}\pi )& \cos ({\omega }_{re}t+\frac{2}{3}\pi )\\ \sin ({\omega }_{re}t)& \sin ({\omega }_{re}t-\frac{2}{3}\pi )& \sin ({\omega }_{re}t+\frac{2}{3}\pi )\\ \frac{1}{2}& \frac{1}{2}& \frac{1}{2}\end{array}\right|\left|\begin{array}{c}{\overline{V}}_{aTTR}\\ {\overline{V}}_{bTTR}\\ {\overline{V}}_{cTTR}\end{array}\right|$$

(8)

$$\left|\begin{array}{c}{\overline{V}}_{qTLI}\\ {\overline{V}}_{dTLI}\end{array}\right|=\frac{2}{3}\times \left|\begin{array}{ccc}\cos ({\omega }_{re}t)& \cos ({\omega }_{re}t-\frac{2}{3}\pi )& \cos ({\omega }_{re}t+\frac{2}{3}\pi )\\ \sin ({\omega }_{re}t)& \sin ({\omega }_{re}t-\frac{2}{3}\pi )& \sin ({\omega }_{re}t+\frac{2}{3}\pi )\\ \frac{1}{2}& \frac{1}{2}& \frac{1}{2}\end{array}\right|\times \left|\begin{array}{c}{\overline{V}}_{aTLI}\\ {\overline{V}}_{bTLI}\\ {\overline{V}}_{cTLI}\end{array}\right|$$

(9)

$${\overline{V}}_{qg}={\overline{V}}_{qTTR}-{\overline{V}}_{qTLI},{\overline{V}}_{dg}={\overline{V}}_{dTTR}-{\overline{V}}_{dTLI}$$

(10)

A block scheme of the PMSG model is shown in Figure 3.

Similarly, a three-phase open secondary winding transformer (OSWT) can be modeled in an orthogonal qd reference frame synchronous to the primary voltage vector according to:

$$\begin{array}{l}{V}_{q1}=R_1{i}_{q1}+\frac{d}{dt}{\lambda }_{q1}+{\omega }_e{\lambda }_{d1}\\ V_{d1}=R_1{i}_{d1}+\frac{d}{dt}{\lambda }_{d1}-{\omega }_e{\lambda }_{q1}\\ V_{q2}=R_2{i}_{q2}+\frac{d}{dt}{\lambda }_{q2}+{\omega }_e{\lambda }_{d2}\\ V_{d2}=R_2{i}_{d2}+\frac{d}{dt}{\lambda }_{d2}-{\omega }_e{\lambda }_{q2}\end{array}$$

(11)

$$\begin{array}{l}{\lambda }_{q1}=L_{s1}{i}_{q1}+L_m{i}_{q2}\\ {\lambda }_{d1}=L_{s1}{i}_{d1}+L_m{i}_{d2}\\ {\lambda }_{q2}=L_{s2}{i}_{q2}+L_m{i}_{q1}\\ {\lambda }_{d2}=L_{s2}{i}_{d2}+L_m{i}_{d1}\\ L_{s1}=L_{l1}+L_m\\ L_{s2}=L_{l2}+L_m\end{array}$$

(12)

where i_q1, i_d1, i_q2, and i_d2 are the q- and d-axis components of the primary and secondary winding currents, while V_q1, V_d1, V_q2, V_d2 and λ_q1, λ_d1, λ_q2, λ_d2, are the q- and d-axis components of the primary and secondary winding voltages and fluxes. L_s1 and L_s2 are the self-inductances and L_m is the magnetization inductance. The angular frequency of the grid voltage is indicated as ω_e. The secondary windings are connected to the TTR and TLI, and thus, the phase winding voltages are given by:

$${\overline{V}}_{q2}={\overline{V}}_{qTTR}-{\overline{V}}_{qTLI}, {\overline{V}}_{d2}={\overline{V}}_{dTTR}-{\overline{V}}_{dTLI}$$

(13)

3.2. Vienna Rectifier Model

The Vienna rectifier switches at the fundamental frequency, according to

Table 1. Vienna rectifier switching table.

Phase a	0 < θe < α π − α < θe < π + α 2π − α < θe < 2π	if iag > 0 => Sa1 ON Sa2 OFF if iag < 0 => Sa1 OFF Sa2 ON
Phase b	2/3π < θe < α + 2/3π 5/3π − α < θe < 5/3π + α 2/3π − α < θe < 2/3π	if ibg > 0 => Sb1 ON Sb2 OFF if ibg < 0 => Sb1 OFF Sb2 ON
Phase c	4/3π < θe < α + 4/3π 1/3π − α < θe < 1/3π + α 4/3π − α < θe < 4/3π	if icg > 0 => Sc1 ON Sc2 OFF if icg < 0 => Sc1 OFF Sc2 ON

, where θ_e is the angular displacement of the fundamental harmonic of the winding phase voltage and α is the switching angle of S_ij, (i = a, b, c and j = 1, 2).

Assuming the output voltage V_DC′ is constant, actual values of Vienna rectifier input phase voltages V_iTTR are thus given by:

$$V_{iTTR}=S_{ij}\frac{l_{ij}-1}{2}{V_{DC}}^{\prime }, \begin{array}{l}-\alpha <{\phi }_{TTR}<\alpha \\ l_{ij}=0,\hspace{0.17em}1,\hspace{0.17em}2.\end{array}$$

(14)

To avoid improper operations leading to extra power losses and voltage distortion, the angular displacement φ_TTR between the fundamental harmonics of voltage V_iTTR and current must be set lower than $\left|\alpha \right|$. Dealing with an electrical power generation application, a vector diagram of AC variables is shown in Figure 4a, where φ is the phase displacement between the PMSG back-EMF ${\overline{E}}_g$ and the current $\overline{I}$. δ represents the angle between the voltage ${\overline{V}}_{TTR}$ and the q axis, and is set to allow a reactive power flow between the Vienna rectifier and PMSG, associated to the inductive elements of the electrical machine.

Neglecting, for simplicity, the voltage V_TLI generated by the auxiliary inverter, which is an independent variable and whose amplitude is significantly lower than V_i1TTR, the amplitude of the fundamental harmonic of the TTR input voltage V_i1TTR is obtained as a function of the switching angle α and DC bus voltage V_DC′ as follows:

$$|{\overline{V}}_{i1TTR}|=\frac{2}{\pi }{V_{DC}}^{\prime }\cos (\alpha ),m_{TTR}=\frac{\left|V_{i1TTR}\right|}{{V_{DC}}^{\prime }}$$

(15)

where m_TTR is the modulation index of the Vienna rectifier. According to the vector diagram of Figure 4b, qd components of the voltage can be written as:

$$\begin{gathered} \{\begin{array}{l}{\overline{V}}_{qTTR}=\left|{\overline{V}}_{i1TTR}\right|\cos (\delta )\\ {\overline{V}}_{dTTR}=\left|{\overline{V}}_{i1TTR}\right|\sin (\delta )\end{array},\hspace{1em}\{\begin{array}{l}{\overline{i}}_q=\left|\overline{I}\right|\cos (\phi )\\ {\overline{i}}_d=\left|\overline{I}\right|\sin (\phi )\end{array},\hspace{1em}\{\begin{array}{l}{\overline{E}}_{qg}=\left|{\overline{E}}_g\right|\\ {\overline{E}}_{dg}=0\end{array} \\ \{\begin{array}{l}X{\overline{i}}_q=-\left|X_s\overline{I}\right|\sin (\phi )\\ X{\overline{i}}_d=+\left|X_s\overline{I}\right|\cos (\phi )\end{array},\hspace{1em}\{\begin{array}{l}R{\overline{i}}_q=-\left|R\overline{I}\right|\cos (\phi )\\ R{\overline{i}}_d=-\left|R\overline{I}\right|\sin (\phi )\end{array} \end{gathered}$$

(16)

while the active and reactive powers are given by:

$$\{\begin{array}{l}{P}_{TTR}=\frac{3}{2}\left|{\overline{V}}_{i1TTR}\overline{I}\right|\cos (\delta -\phi )\\ Q_{TTR}=\frac{3}{2}\left|{\overline{V}}_{i1TTR}\overline{I}\right|\sin (\phi -\delta )\end{array},\hspace{1em}\{\begin{array}{l}{P}_R=-\frac{3}{2}R|\overline{I}{|}^2\\ Q_X=-\frac{3}{2}X|\overline{I}{|}^2\end{array},\hspace{1em}\{\begin{array}{l}{P}_g=\frac{3}{2}\left|{\overline{E}}_{qg}\overline{I}\right|\cos (\phi )\\ Q_g=\frac{3}{2}\left|{\overline{E}}_{qg}\overline{I}\right|\sin (\phi )\end{array}$$

(17)

where P_TTR and Q_TTR are the active and reactive power, respectively, processed by the Vienna rectifier, P_R and Q_X are the active power wasted in the stator resistance R and the reactive power due to the PMSG synchronous reactance X_s, respectively, while P_g and Q_g are the active and reactive power delivered by the PMSG, respectively.

Neglecting the rectifier power losses, the AC power generated by the PMSG is equal to the sum of the power dissipated in the DC bus capacitor resistances R_C1 and R_C2 and the power delivered to the load R_L. In the Laplace domain, V_DC′ and the capacitor voltages V_C1 and V_C2 are thus given by

$$\{\begin{array}{l}{V_{DC}}^{\prime }(s)=\sqrt{R_L\left(P_{AC}(s)-\frac{V_{C1}^2(s)}{R_{C1}}-\frac{V_{C2}^2(s)}{R_{C2}}\right)}\\ V_{C1}(s)={V_{DC}}^{\prime }(s)\frac{{sR}_{C1}({1+R}_{C2}{C}_2)}{R_{C1}+R_{C1}+{sR}_{C1}{R}_{C2}(C_1+C_2)}\\ V_{C2}(s)={V_{DC}}^{\prime }(s)-V_{C1}(s)\\ P_{AC}(s)=\frac{3}{2}\left(V_{qTTR}(s)i_q(s)+V_{dTTR}(s)i_d(s)\right)\end{array}$$

(18)

where i_n is mainly given by the difference between the currents flowing through the two DC bus capacitors and it can be also computed as the sum of the currents flowing through the three branches of the Vienna rectifier:

$$i_n=S_{aj}{i}_{ag}+S_{bj}{i}_{bg}+S_{cj}{i}_{cg}$$

(19)

The averaged-value of i_n during a switching period T is given by

$${\overline{i}}_n=\frac{1}{T}\left(T_{ONaj}{i}_{ag}+T_{ONbj}{i}_{bg}+T_{ONcj}{i}_{cg}\right)=\left(d_{aj}{i}_{ag}+d_{bj}{i}_{bg}+d_{cj}{i}_{cg}\right)$$

(20)

where d_ij = T_ONij/T are the duty cycles of the bidirectional switches S_ij, according to

Table 2. d_aj, d_bj and d_cj.

Sector I Va1TTR > 0 Vb1TTR < 0 Vc1TTR < 0	Sector II Va1TTR > 0 Vb1TTR > 0 Vc1TTR < 0	Sector III Va1TTR < 0 Vb1TTR > 0 Vc1TTR < 0	Sector VI Va1TTR < 0 Vb1TTR > 0 Vc1TTR > 0	Sector V Va1TTR < 0 Vb1TTR < 0 Vc1TTR > 0	Sector IV Va1TTR > 0 Vb1TTR < 0 Vc1TTR > 0
$d_{aj}=\frac{V_{a1TTR}}{{V_{DC}}^{\prime }}$	$d_{aj}=-\frac{V_{a1TTR}}{{V_{DC}}^{\prime }}$	$d_{aj}=-\frac{V_{a1TTR}}{{V_{DC}}^{\prime }}$	$d_{aj}=-\frac{V_{a1TTR}}{{V_{DC}}^{\prime }}$	$d_{aj}=\frac{V_{a1TTR}}{{V_{DC}}^{\prime }}$	$d_{aj}=\frac{V_{a1TTR}}{{V_{DC}}^{\prime }}$
$d_{bj}=\frac{V_{b1TTR}}{{V_{DC}}^{\prime }}$	$d_{bj}=\frac{V_{b1TTR}}{{V_{DC}}^{\prime }}$	$d_{bj}=-\frac{V_{b1TTR}}{{V_{DC}}^{\prime }}$	$d_{bj}=-\frac{V_{b1TTR}}{{V_{DC}}^{\prime }}$	$d_{bj}=-\frac{V_{b1TTR}}{{V_{DC}}^{\prime }}$	$d_{bj}=-\frac{V_{b1TTR}}{{V_{DC}}^{\prime }}$
$d_{cj}=-\frac{V_{c1TTR}}{{V_{DC}}^{\prime }}$	$d_{cj}=-\frac{V_{c1TTR}}{{V_{DC}}^{\prime }}$	$d_{cj}=\frac{V_{c1TTR}}{{V_{DC}}^{\prime }}$	$d_{cj}=\frac{V_{c1TTR}}{{V_{DC}}^{\prime }}$	$d_{cj}=\frac{V_{c1TTR}}{{V_{DC}}^{\prime }}$	$d_{cj}=-\frac{V_{c1TTR}}{{V_{DC}}^{\prime }}$

. Figure 5 shows some simulations dealing with balanced and unbalanced DC bus voltages operations, while a block diagram of the Vienna rectifier mathematical model is shown in Figure 6.

A non-null average $i_n$ leads to unbalanced DC bus voltages [16,17,18]; moreover, the mean value of fundamental voltages V_a1TTR becomes negative if V_C1 < V_C2 or positive if V_C2 < V_C1. This is included in the TTR model by adding the term ΔV_DC′ = V_C1 − V_C2:

$$\{\begin{array}{l}{V}_{a1TTR}=\left|V_{a1TTR}\right|\sin ({\theta }_e)+\mathsf{\Delta }{V_{DC}}^{\prime }\\ V_{b1TTR}=\left|V_{b1TTR}\right|\sin ({\theta }_e-\frac{2}{3}\pi )+\mathsf{\Delta }{V_{DC}}^{\prime }\\ V_{c1TTR}=\left|V_{c1TTR}\right|\sin ({\theta }_e+\frac{2}{3}\pi )+\mathsf{\Delta }{V_{DC}}^{\prime }\end{array}$$

(21)

According to Table 2, by replacing (21) into (20), ${\overline{i}}_n$ is given by

$${\overline{i}}_n=\{\begin{array}{l}{m}_{TTR}0.5I\left[-\cos ({\phi }_{TTR})-2\cos (2{\theta }_e-\frac{4\pi }{3}-{\phi }_{TTR})\right]-2I\frac{\mathsf{\Delta }{V_{DC}}^{\prime }}{{V_{DC}}^{\prime }}\sin ({\theta }_e-\frac{2\pi }{3}-{\phi }_{TTR}),\hspace{1em}\hspace{1em}0<{\theta }_e<\frac{\pi }{3}\\ m_{TTR}0.5I\left[\cos ({\phi }_{TTR})+2\cos (2{\theta }_e-{\phi }_{TTR})\right]-2I\frac{\mathsf{\Delta }{V_{DC}}^{\prime }}{{V_{DC}}^{\prime }}\sin ({\theta }_e-{\phi }_{TTR}),\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\frac{\pi }{3}<{\theta }_e<\frac{2\pi }{3}\\ m_{TTR}0.5I\left[-\cos ({\phi }_{TTR})-2\cos (2{\theta }_e-\frac{2\pi }{3}-{\phi }_{TTR})\right]-2I\frac{\mathsf{\Delta }{V_{DC}}^{\prime }}{{V_{DC}}^{\prime }}\sin ({\theta }_e+\frac{2\pi }{3}-{\phi }_{TTR}),\hspace{1em}\hspace{1em}\frac{2\pi }{3}<{\theta }_e<\pi \\ m_{TTR}0.5I\left[\cos ({\phi }_{TTR})+2\cos (2{\theta }_e-\frac{4\pi }{3}-{\phi }_{TTR})\right]+2I\frac{\mathsf{\Delta }{V_{DC}}^{\prime }}{{V_{DC}}^{\prime }}\sin ({\theta }_e-\frac{2\pi }{3}-{\phi }_{TTR}),\hspace{1em}\hspace{1em}\hspace{1em}\pi <{\theta }_e<\frac{4\pi }{3}\\ m_{TTR}0.5I\left[-\cos ({\phi }_{TTR})-2\cos (2{\theta }_e-{\phi }_{TTR})\right]-2I\frac{\mathsf{\Delta }{V_{DC}}^{\prime }}{{V_{DC}}^{\prime }}\sin ({\theta }_e-{\phi }_{TTR}),\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\frac{4\pi }{3}<{\theta }_e<\frac{5\pi }{3}\\ m_{TTR}0.5I\left[\cos ({\phi }_{TTR})+2\cos (2{\theta }_e-\frac{2\pi }{3}-{\phi }_{TTR})\right]+2I\frac{\mathsf{\Delta }{V_{DC}}^{\prime }}{{V_{DC}}^{\prime }}\sin ({\theta }_e+\frac{2\pi }{3}-{\phi }_{TTR}),\hspace{1em}\hspace{1em}\hspace{1em}\frac{5\pi }{3}<{\theta }_e<\pi \end{array}$$

(22)

3.3. TLI Model

A key task of the TLI present in the AHUTR topology is to compensate all low-order voltage harmonics generated by the step-modulated Vienna rectifier [12]. For this reason, the TLI reference phase voltage is equal to the difference between the AC side input voltage V_iTTR and its fundamental component V_i1TTR, as shown in Figure 7.

$$V_{iTLI}{}^{*}=V_{iTTR}-V_{i1TTR}$$

(23)

Phase voltages V_iTTR encompass some zero sequence components, such as the 3^rd, 9^th, 27^th, and 81^st, that will not result in corresponding currents in the PMSG because the considered open-end winding topology is composed by two isolated converters. Hence, these harmonics can be neglected in the TLI reference voltages V_iTLI^*. This leads to a reduction of TLI DC bus voltage and, accordingly, to a positive impact on TLI losses. TLI reference voltages V_abcTLI^* are thus given by

$$\{\begin{array}{l}{V_{aTLI}}^{*}(n,{\theta }_e)={\displaystyle \sum _{n=5,7,11,13}{b}_{an}\times \sin (n{\theta }_e-{\phi }_n)}\\ {V_{bTLI}}^{*}(n,{\theta }_e)={\displaystyle \sum _{n=5,7,11,13}{b}_{bn}\times \sin (n{\theta }_e-{\phi }_n-\frac{2\pi }{3})}\\ {V_{cTLI}}^{*}(n,{\theta }_e)={\displaystyle \sum _{n=5,7,11,13}{b}_{cn}\times \sin (n{\theta }_e-{\phi }_n+\frac{2\pi }{3})}\end{array}$$

(24)

Figure 8 shows the V_aTLI^* waveform when considering a different set of zero sequence components. For each case, the minimum V_DC″/V_DC′ requirement has been computed as shown in Figure 9, while current and voltage THDs are provided in Figure 10. At medium-high values of the modulation index m_TTR, a proper suppression of the effects of the low-order voltage harmonics produced by the Vienna rectifier is simply achieved by compensating the 5^th and 7^th harmonics. However, at low m_TTR, additional harmonics must be considered to keep the THDs suitably low.

As shown in Figure 2, a closed loop input current control system is added to the predictive filter in order to cope with unmodeled non-linearities and improve the input current waveform as well as the system dynamic response. By equaling the active power generated by the PMSG to the output DC power, the reference q-axis current i_q^* is computed from actual values of α, δ and the output DC current i_DC as:

$$i_q^{*}=\frac{\pi i_{DC}}{3\cos (\alpha )\cos (\delta )},i_d^{*}=0$$

(25)

The d-axis reference current i_d^* can be simply set to zero or suitably determined in case of interior permanent magnet structures in order to operate the PMSG according to a maximum power per ampere strategy.

Another key function of the TLI is to balance the voltage across the DC bus capacitors of the Vienna rectifier, making unnecessary additional circuits. As shown in Figure 2, this goal is obtained by acting on the q-axis component of the TLI reference current in order to control the amplitude of i_n, which is given by the difference between the currents flowing through the two DC bus capacitors.

The DC side of the TLI is modeled by balancing the AC and DC side power, neglecting the power switches losses (Equation (26)). The TLI DC-link includes the resistance R_CT representing the floating capacitor losses, while V_qTLI and V_dTLI are the voltage components of TLI V_jTLI in the qd axis, as shown in Figure 11.

$$\{\begin{array}{l}{P}_{AC}=P_{DC2}=\frac{3}{2}\left(V_{qTLI}{i}_q+V_{dTLI}{i}_d\right)\\ P_{DC2}={V_{DC}}^{″}{i_{DC}}^{″}+\frac{{V_{DC}}^{″2}}{R_{CT}}={V_{DC}}^{″}{C}_{T}s{V_{DC}}^{″}+\frac{{V_{DC}}^{″2}}{R_{CT}}=\frac{3}{2}\left(V_{qTLI}{i}_q+V_{dTLI}{i}_d\right)\end{array}$$

(26)

4. Model Validation

An electric power generation application has been considered for validating the value-averaged model. Specifically, the proposed model represented with the blocks scheme of Figure 12 has been implemented in a Simulink environment and compared to a detailed model of the system developed in the same environment exploiting the SimPower System Toolbox, which is a circuit-based modeling platform widely used for the simulation of power electronic converters, electromechanical systems, and their control systems. The last model includes both converter topologies. The control scheme used on both models is shown in Figure 2, including low-order harmonic compensation and DC bus capacitor voltages balancing [14]. Simulation settings are summarized in

Table 3. System parameters.

PMSG		Vienna		TLI	Control Gains
Power Rating	3 kW	IGBT Ratings	600 V, 20 A	200 V, 10 A	KPα = 0.1, KIα = 10
Rated Voltage	575 VDC	DC-Link Voltage	200 V	100 V	KPiqg = 80, KIiqg = 1000
Rated Current	6.5 A	DC Bus Capacitors	470 μF (C1, C2)	470 μF (CT)	KPidg = 80, KIidg = 1000
Phase Inductance	20 mH	Load	50 Ω	//	KPin = 0.2, KIin = 2
Stator Resistance	4.3 Ω	Capacitors Resistance	1000 Ω (RC1, RC2)	600 Ω (RCT)	KPTLI = 2, KITLI = 30
PM Flux	0.57 Wb	Switching Frequency	50 Hz	40 kHz

, where k_Pα and k_Iα are the proportional and integral gains of the output DC voltage controller, while k_Piq, k_Iiq, k_Pid, and k_Iid are the proportional and integral gains of qd PMSG current regulators; k_Pin and k_Iin are the proportional and integral gains of the Vienna rectifier DC bus voltage equalization system; and k_PTLI and k_ITLI are the proportional and integral gains of the TLI DC Bus voltage controller. Figure 13 and Figure 14 show simulation results obtained with the SimPower System model and the averaged-value model, showing a purposely generated Vienna rectifier DC bus voltage unbalance with the balance system not activated. Specifically, capacitor voltages V_C1 and V_C2, which at the beginning are equal because R_C1 and R_C2 are both set to 1000 Ω, diverge after t = 3 s because R_C2 is changed to 600Ω in order to generate the voltage unbalance. The i_n current is zero when capacitor voltages are balanced and greater than zero after t = 3 s, while DC bus voltages V_DC′ and V_DC″ do not vary. A zoomed-in view of the balanced and unbalanced steady-state operations of Figure 13 and Figure 14 are shown in Figure 15 and Figure 16, confirming a good matching between the results obtained with the two models. Figure 15d and Figure 16d show the instantaneous Vienna rectifier power losses P_TTR, TLI power losses P_TLI, and PMSG power losses P_Lg during balanced DC bus capacitors. A one-time variation of the references of the output voltage and the TLI DC bus voltage is considered in Figure 17 and Figure 18, while a load variation is shown in Figure 19 and Figure 20. The results achieved with the two models are very close, but using the averaged-value model, the simulation time is roughly one third. In particular, all simulations have been accomplished on an Intel® CoreTM i7 CPU with 2.60 GHz and 16 GB RAM running a 64-bit Windows 10 operating system. Simulation results shown in Figure 13, Figure 14, Figure 15, Figure 16, Figure 17, Figure 18, Figure 19 and Figure 20 required three minutes computing time using the SimPower System model with a 10⁻⁶ s time step. A 10⁻⁵ s time step can be used with the averaged-value model, because high frequency voltage and current harmonics are neglected, leading to only ten seconds to accomplish the same simulation.

Figure 21 displays the maximum errors between the quantities carried out by the two models, confirming a good accuracy of the proposed average model in a wide range of load conditions.

5. Experimental Assessment

The accuracy of the AHUTR analytical model has also been verified comparing the results from the model with those from an experimental test rig consisting of 1kW AHUTR supplying an open-end-winding PMSG, mechanically coupled to a 2.6 kW PM synchronous motor drive used as a prime mover. Technical specifications of the PMSG are given in

Table 4. PMSG technical data.

Pn (kW)	Ls (mH)	Vs (V)	Rs (Ω)	Is (A)	λPM (Wb)	ωr (krpm)	Pole Pairs
1	20	565	4.8	6.5	1.53	2	3

. This AHUTR supplied DC loads at 400V through the Vienna rectifier equipped with insulated gate bipolar transistors (IGBTs) whose technical data are listed in

Table 5. Technical specifications of STGW30NC60KD IGBT.

Vce (V)	Vce(on) (V)	iRMS (A)	trise (ns)	tfall (ns)
600	2.1	30	27	160

. The TLI was realized with low-voltage power metal-oxide-semiconductor field-effect transistor (MOSFETs) and operated at 40 kHz, V_DC″ = 100 V. Technical data of the power MOSFETs are reported in

Table 6. Technical specifications of IRFB5615PBF MOSFET.

VDS (V)	RDS (m)	ID (A)	trise (ns)	tfall (ns)
150	32	35	8.9	17.2

. The TLI floating capacitor and both capacitors C₁, C₂ were equal to 470µF. The DC load was modified using a variable power resistor. A single dSPACE DS1103 control board was used to control the Vienna rectifier and the TLI, while a 2048 ppr encoder was used to measure the rotor position θ_r of the PMSG. The experimental setup is shown in Figure 22. The currents and voltages were measured by using a dedicated sensing board equipped with the current transducer LEM LA 55-P and voltage transducer LEM LV 25-P.

The experimental results shown in Figure 23 were obtained by imposing a transient voltage to V_DC′ from 400 V to 320 V by keeping a constant resistor value R_L = 80 Ω and with the PMSG spinning at ω_r = 200 rad/s. Note a satisfying accuracy in the mechanical and electrical quantities estimated by the model. The voltage V_DC″ was properly modified by the control algorithm in order to keep the optimal ratio between the DC bus voltages V_DC′ and V_DC″. A different test is displayed in Figure 24 in which a speed transient was forced by acting on the prime mover. More specifically, the rotational speed ω_r was changed from 200 rad/s to 260 rad/s while the resistive load was still kept constant. Even in this case, the model accurately predicted the behavior of the drive, both at steady-state and transient. The DC bus voltages were both affected by the speed variation, but the feedback control loops restored the reference values. A step load variation was imposed in the test of Figure 25, where the DC load was purposely doubled by switching from T_L = 2 Nm to T_L = 4 Nm. In this case, a more remarkable difference was observed between the model and the experimental results. Finally, the effectiveness of the model to predict the balancing of the voltages across the DC bus capacitors is shown in Figure 26. Initially, the balancing algorithm described in the previous sections was inactive, and thus, the voltages at the terminals of C₁ and C₂ were significantly different. At the instant t*, the voltage-balancing approach was activated, nullifying V_C1 − V_C2. The results of Figure 26 confirm the capability of the model to accurately simulate even this critical issue of the AHUTR. Maximum percentage errors between the outputs of the SimPower System and the averaged-value model are summarized in

Table 7. Errors between experimental results and those obtained with the averaged-value model.

Test	ΔVDC′ (%)	Δωr (%)	ΔTe (%)	ΔVDC″ (%)	Δin′ (%)	ΔVC1 (%)	ΔVC2 (%)
Figure 22	2.2	1.9	3.7	4.7	/	/	/
Figure 23	2.1	2.6	5	7.7	/	/	/
Figure 24	4.5	4.9	6	5	/	/	/
Figure 25	/	/	/	/	6.6	10	4

, where the quantities with the suffix Δ are the errors in estimating V_DC^′, ω_r, T_e, V_DC^’’, i_n, V_c1, and V_c2.

6. Conclusions

The asymmetrical hybrid unidirectional T-type rectifier is more efficient than a conventional PWM rectifier, mainly due to line frequency operation of the main converter, a T-type rectifier. However, it features a more complex structure composed of three main components, namely a TTR, a TLI, and an open winding electric machine, all interacting. The development of an accurate averaged-value mathematical model of the AHUTR topology aimed to optimally design control and management algorithms has been faced in the paper. Simulations and experimental results show that the proposed model is able to reproduce the static and dynamic behavior of the AHUTR with good accuracy. Furthermore, the obtained mathematical representation made a fast analysis of the system during TTR DC bus voltage unbalance operations possible. This has been exploited to design an active balancing system acting on the TLI side—a task which would be time-consuming with circuit-oriented simulator models. Furthermore, the averaged-value model has been used to define the entire AHTUR control and management system tasked to deal with efficiency maximization, input power factor control, TTR DC bus capacitor voltage balance, and the control of TLI floating DC bus voltage.