1. Introduction
The involvement of modern power electronics converters in the emerging technology is essential for the electrical system in the current era. Very particularly, in the overall power electronics segment, the voltage source two-level inverters are very popular and demanding, due to their application encroachment in industrial, commercial and non-conventional energy conversion systems [
1]. Compared with two-level inverters, multilevel inverters (MLIs) have substantial rewards, which are intensive in the enhancement of the voltage and current waveform quality, reduction of harmonic contents, and increment of power handling capability. Nabae et al. invented the first MLI based on two-level inverter structure called neutral-point clamped (NPC) topology in 1981 [
2] which was followed by the development of cascaded H-bridge (CHB), flying capacitor (FC), and hybrid MLIs in later years. Even though these MLIs are capable of producing the multi-stepped output voltages with reduced dv/dt and harmonics for improved power qualities. But, considering the DC-link capacitors balancing and common mode voltage (CMV) reduction, the MLIs are widely still investigated with different modulation strategies [
3] for compensation methods. Among them, space vector modulation (SVM) offers better-quality voltage and current output with higher DC-link utilization. In addition, SVM provides a switching state selection opportunity to improve the performance of the MLI [
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15]. Particularly, the SVM contributions in NPC-MLI are widely researched and applied in the various fields of drives and renewable energy integration applications [
5]. The switching selections in the multilevel SVM are mainly associated with the space vector diagram (SVD) synthesization and switching states on-time calculation. The multilevel SVM using two-level concepts are widely explored than the other MLI SVM methods [
4,
9,
12,
13,
14,
15,
16]. However, these methods include complex mathematics to calculate the target reference voltage vector and recognize inner sub-triangle etc. The Zhang et al. has introduced a method for finding switching states on-time using direct two-level SVM approach. In this method, the three-level SVD has fragmented to a six, equal, two-level SVD, and its location of the centre of six virtual hexagons originated through segregation of the SVD [
17]. Similar to this method, in the literature, many papers have been reported in which shifting the origin to one of the six centres, and αβ-axes are rotated by 60° to use two-level on-time calculations [
12,
13,
14,
15,
16,
18,
19,
20,
21]. Even though these methods are calculating the individual switch on-times from segregated two-level SVM, while extending to higher levels that need complex mathematical functions to calculate the sub-triangle. Seo et al. [
18] proposed a scheme for an MLI SVM for three-level NPC similar to Zhang et al. where the origin is shifted to 60° which sorts six sub-hexagons to compute on-times, thereby involving additional computations. The three-level SVD based two-level SVD with reduced math function is proposed and implemented for NPC-MLI [
9]. The similar idea is extended to linear modulation (LM) and over modulation (OVM) region with field programmable gate array (FPGA) implementation for NPC-MLI [
19,
20,
21,
22,
23].
In [
19], the multilevel SVD is divided into six equal two-level SVDs and switching vector on- time calculations are made through direct transformations from three neighboring switching vectors. However, the estimation of the on-time calculation is done by extending a set of matrix transformations, which includes complex computations. Extending the inverter modulation index more than 0.907 is called as OVM. It requires non-linear mathematical functions to synthesis their reference vector outside SVD hexagon [
24,
25,
26]. The industrial drives, such as direct torque and field-oriented controller need OVM region operations, since linear modulation range operation restricts the inverter modulation index, and hence, the drives produce limited constant torque as it utilizes only 90% of input DC-link voltage. Hence, the inverter drive covering OVM is beneficial by means of entire exploitation of the installed input source capacity, which results in the increased cumulative speed-torque characteristics, as well as the operating boundary of the traction drives. However, OVM leads to complexities in hardware implementations, due to non-linearity switching equations [
20]. Due to this complexity in the OVM region synthesization and on-time calculations, many studies are not preferred to include OVM region operation. Very few implementations have performed in the OVM region operation [
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31]. These implementations are using complex mathematical functions to realize the OVM non-linear region and on-time calculations. To realize the OVM region, the non-linear trigonometric functions are used to find the modified on-times. These methods are relatively complex to implement [
24,
25]. Most of the OVM region studies in MLI SVM have been done by charging the reference vector position [
23,
24,
26,
27,
28,
29,
30]. The on-time switching calculations of OVM using virtual vectors were recognized by using modifying hexagonal trajectory. However, in these methods, there would be portions of the line cycle, where the preferred reference vector could not be synthesized [
28], [
30]. Few algorithms were developed which use additional switching time derived from the outside hexagonal boundary projection [
26,
29]. However, these methods are introducing lower frequency harmonics, which are affecting the output waveform quality.
The rapid developments in high-performance microcontrollers, DSPs and FPGAs, have encouraged the research of work on digital PWM for rapid prototyping. Due to the development of ASIC technology, the FPGA based implementations have become popular, since it has an ability to implement custom hardware solutions and reprogramming flexibility. The SVM implementations on FPGA are showing a higher interest in the current era [
6,
12,
14,
32,
33,
34,
35,
36,
37,
38,
39,
40,
41,
42,
43,
44]. These implementations are mainly done through Altera and Xilinx Spartan family. The first successful single chip FPGA implementation of SVM has been presented by Tzou et al. [
33], and followed by a variety of single chip FPGA IP core three-level SVM implementation and reported the validation [
34,
35,
36,
40]. These implementations have been done through Altera Vertex and Spartan with large device utilization and computational time. These direct VHDL code based implementations have suffered from the drawbacks of computational burden (writing VHDL/Verilog coding), high device utilization, and higher time taken. Particularly at high modulation ranges, due to the higher mathematical burden, the processing time is being increased [
23,
29,
42]. These methods are very effective for implementation in terms of calculating the switching vectors and dwell times by means of simple addition and comparison operators without using any angles, trigonometric function and LUTs. However, the extension to OVM in n-level needed high mathematical operations and high hardware resources. The low complexity and fewer computation approaches make the SVM implementations very suitable for real-time application drive systems. The FPGA Spartan processors are developed on a VHDL code to carry out the implementation into FPGA. By the use of Xilinx system generator ISE tools, the SVM implementations have focused on increasing the processing speed, reduce the device utilization and the reconfiguration (partial and full) implementations [
37,
40]. In any implementation, the resource (FFs, LUTs) utilization is a major factor. Wang et al. [
45] deployed three-level SVM in Spartan-3 FPGA with the consumption of 3,584 slices. Few more attempts were made with the same FPGA, which were also found to have higher resource utilization [
14,
23,
40]. As an alternative, the same can be achieved using MATLAB/Simulink-Xilinx System generator tools with foundation ISE tools [
46].
From the wide range of literature in the MLI SVM design and FPGA implementations, the existing methods involve higher computational complications for finding reference vector location and the on-time calculations of switching states. Hence, the existing FPGA implementations occupy higher device utilization and processing time. The reference vector positions in the multilevel SVD sub-triangle and over modulation boundary on-time calculations need to be rethought. Subsequently, the FPGA digital implementations era facilitates the exploitation of control degree of freedom in both LM and OVM region. Therefore, in this paper, a reduced mathematical approach is developed for identifying the sub-triangles and over modulation boundary area for calculating switching on-times. The proposed SVM has a direct way for calculating the LM and OVM switching times using two-level SVM. The proposed SVM is simulated using MATLAB-Simulink ISE system generator and validated directly in Xilinx family SPARTAN-III-3A XC3SD1800A-FG676 DSP-FPGA processor board. The implementation is verified through a three-level NPC-MLI fed induction motor drive laboratory prototype, and the test is performed over a wide range of operating conditions. The proposed SVM and their FPGA implementations are compared with the other reported methods. The theoretical design, analysis, and experimentation results validate the advantages of the proposed PWM design and its implementation.
The organization of the paper is deliberate as follows:
Section 2 explains the space vector PWM theory for two-level and multilevel.
Section 3 deals with the proposed simplified MLI SVM, including both linear and over modulations.
Section 4 accomplishes the MATLAB-Simulink implementation, and
Section 5 discusses the FPGA collaborated experimentation setup of three-level MLI.
Section 6 and
Section 7 deal with the distributed implementation of MLI SVM in FPGA MATLAB XSG-ISE and experimental results. In conclusion, the rewards of the proposed MLI SVM and its implementation are presented in
Section 8. The list of abbreviations and references are given in the end.
3. Proposed Simplified MLI SVM for Entire Modulation Index
One of the important contributions of this paper is to propose the simple mathematical approach to find out the V* sub-triangle position of MLI SVM. The proposed MLI SVM is developed based on standard two-level SVM for three-level MLI, and it can be extended for n-level using simple additional equations. In addition to proposed sub-triangle calculation, the reduced mathematical functions for calculating OVM switching on-times is achieved by just adding the compensated on-time gain in over modulation region with LM on-time. Hence, the proposed SVM reduces the implementation burden, since the complex part of MLI SVM calculations of sub-triangle position and OVM on-times are minimized.
3.1. Procedure in Generating MLI SVM in Linear Modulation
Figure 3 shows the three-level MLI SVM generation flowchart. Like two-level SVM, the MLI SVM takes the three-phase signal to calculate two-phase voltage vectors stationary reference frame (V
α,V
β) [
20]. Then, the V
α, V
β are converted into reference voltage vector in polar form as V
* where ‘V
*’ is the voltage magnitude, and ‘θ’ is the angle of the V*.
Using V* and θ, the reference vector sector position is calculated. Here, based on the V* magnitude the SVD operation regions (either LM or OVM) are calculated. In
Figure 3, the flow chart is handling only LM MLI SVM, where the proposed sub-triangle calculations are the same for LM and OVM.
The V* sub-triangle location calculation with-in the sector is calculated through orthogonal time slope mathematical function in Vα, Vβ plane. The stationary plane of are calculated for every Ts and then mapping for the reference vector V* located in sub-triangle is done by comparing . These logical expressions can be applied for any level for identifying the V* sub-triangle. The next section explains the proposed sub-triangle calculations.
3.2. Proposed Sub-Triangle Calculations
Considering the three-level multilevel SVD, shown in
Figure 4, the sub-triangle 1 and 4 (type-1 triangles) can be directly calculated from the V* magnitude, sector number and its respective sector angle (γ),
However, this calculation does not support to calculate sub-triangle 2 and 3 (type-2 triangles). Hence, in order to handle type-1 and type-2 triangles searching progress, a simple look-up table and a searching process is developed directly from
. Once the V* sub-triangle is identified, that particular sub-triangle can be considered as a sector and then two-level SVM is applied to calculate the respective sub-triangle switching states on-time calculation. The same procedure is applied to all sectors in the particular M
a and f
s. The proposed sub-triangle calculation is explained through sector-1 (∆
1,j) as illustrated in
Figure 4.
The calculation of proposed sub-triangle involves two approaches: (1) Type-1 sub-triangles, (2) Type-2 sub-triangles. The V* position for Type-1 triangles Δ
1,1 and Δ
1,4 can be calculated directly from
. However, the calculation of Type-2 triangles Δ
1,3 and Δ
1,2 (orange colored area in
Figure 5b) portions are challenging.
Figure 5 shows the V* location identification for Type-1 and Type-2 triangles. According to that, the search process of the triangle of V* can be narrowed down using the two zones in SVD (Zone-1 and Zone-2). The coordinates (V
α0, V
β0) of these triangles are calculated using two integer calculations of Zone-1 and Zone-2 as follows,
In Equation (4), Zone-1 integer denotes the portion of the sector among the two lines joining the vertices divided by distance ‘h’ and inclined at 120
◦ with respect to α-axis. In
Figure 5b, Zone-1 is valued as zero, it indicates that the point V* is below the line B and C. The Zone-1 appears that the point V* lies between the points A and B and D and F. The Zone-2 denotes the part of the sector between the two lines joining the vertices separated by distance ‘h’ and parallel to α-axis. When the Zone-2 is valued as zero, it indicates that the reference vector tip V* is positioned between the lines A and D and C and E. When the Zone-2 is valued as integer one, it indicates that the point V* lies above the line C and D. Geometrically, the Zone-1 and Zone-2 values are acquired at an intersection of two rectangular regions (rhombus). Here, the V* may be positioned either in triangle Δ
1,2 or Δ
1,3.
Hence, the V* position in type -1 triangles (Δ1,1 and Δ14) is directly identified from Zone-1 and Zone-2 integer values. The Zone-1 and Zone-2 receipts zero integer, when the V* is located in a triangle Δ1,1. The Zone-1 and Zone-2 receipts integer one when the V* is located in triangle Δ1,4. However, the other options from the Zone-1 and Zone-2 (integers of Zone-1 is zero and Zone-2 is one or Zone-1 is one and Zone-2 is zero) are not assisting in identifying the Δ1,2 and Δ1,3.
Hence, the Type-2 sub-triangles (Δ1,2 and Δ1,3.) are calculated in rhombus using diagonal slope coordinate comparisons. The V* co-ordinates point with respect to rhombus point B can be written as,
Figure 6a shows the sub-triangle Δ
1,2 and Δ
1,
3 rhombus and its slope calculations. The sub-triangle, anywhere in reference vector V* is situated by relating the slope of B and slope of BE. The slope B and BE can be written as,
Now, comparing the Equation (8) inequality of the Type-2 sub-triangles (Δ1,2 and Δ1,3.) is identified.
3.3. Sub-Triangle Switching On-time Calculations
The flowchart (See
Figure 3) shows the complete interpretation of the sub-triangle lookup table (LUT) identification for Zone-1 and Zone-2. To simplify the switching on-time calculations, all sub-triangles are further considered into two categories based on their base position either bottom or top. The first category is called as group-1 triangles (Δ
1,1, Δ
1,2 and Δ
1,
4), where it has a base at the bottom. Similarly, group-1 triangle (Δ
1,3) is placed in SVD with the base side at the top.
Figure 7 shows the group-1 and group-2 triangle for the calculation of switching on-times. For the group-1 and group-2 triangle valuations, the proposed SVM uses simply the calculation by using Zone-1 and Zone-2 triangle positions.
The group-1 triangle is determined by solving the following Equations (9) and (10),
Else,
Thus the coordinates of group-1 triangle and group-2 triangles can be calculated as and 0.5 , h−.
From the individual sub-triangle α, β coordinates, the switching states on-time of each sub- triangle can be calculated similarly to two-level SVM.
This calculation can be used for n-level MLI by the accumulation of the group sub-triangles.
3.4. Extending to Over Modulation
To move the V* from LM to OVM region, the V* is moved to outside the hexagonal trajectory. During this circumstance, the M
a is valued more than 0.9 and the V* moves outside SVD hexagonal boundary. Thus, the synthetization of V* in the OVM region is unrealistic (non-linear nature movement). As a result, to achieve the OVM region operation and calculating its switching state on-times, the traditional approach used trigonometric functions to calculate the OVM voltage vector switching state on-times [
20,
24,
30]. These methods consume more mathematical and implementation complexity. In addition, these methods are producing higher low frequency harmonics. The proposed OVM method has a straightforward nature to realize switching on-time from the LM switching time. Hence the non-linearly can be minimized, which helps to avoid the additional lower frequency harmonics. The OVM region is operated in two zones as OVM-1 (V* is lies from 0.908 to 0.958) and OVM-2 (V* is lies from 0.958 to one).
In the OVM-1 region, as shown in
Figure 8, there would be portions of the OVM line cycle, which are placed partly within the SVD hexagon and partly outside the hexagon. Hence the two relations are derived for calculating the on-time for V* circular region and hexagonal region. To differentiate these two boundaries, the crossover angle (θ
C) is calculated from the reference vector M
a,
Now the V* angle θ fulfills the position ≤ θ < Π/3 − , the V* remains in hexagonal trajectory, and another portion follows the circular trajectory (0 ≤ θ < to Π/3 − ≤ θ < Π/3). Based on the V* position in SVD, the OVM-1 coordinates (Vα and Vβ) of V* can be calculated from θ and level (n),
From the Vα and Vβ, the and are calculated for deriving modified switching on-time,
To realize the circular trajectory and hexagonal trajectory switching on-times, the gain factor (Gt) can be calculated from the OVM-1 maximum boundary and its actual Ma values. The maximum volt-seconds loss in OVM-1 region is proportional to (0.9535 − 0.907). Hence, the Gt can be obtained from LM Ma as,
Adding and subtracting the Gt with T0, T1 and T2, the circular trajectory and hexagonal trajectory switching on-time can be calculated by modifying the V*.
Now from Equations (11), (12), and (17), the hexagonal trajectory switching on-time is derived as,
Similarly, the circular trajectory switching on-time is derived as,
When the V* modulation index M
a is more than 0.9535, then the V* is entered into OVM-2 region. During this time the V* is allowed only in the hexagonal trajectory (beyond the OVM-1 HT), and only six LVs are needed to operate. Hence, the holding angle
is derived using a similar strategy [
9] to keep the V* at one of the large vectors. The relations 0 ≤ θ <
and Π/3 −
≤ θ <
help to find one of the LV in the particular sector with changing V* position. The on-time equations of OVM-2 are obtained as,
The proposed LM and OVM do not change V* position. Hence, it allows simple implementations.
4. MATLAB-Simulink Implementation of Three-level SVM
The proposed MLI SVM design is established using MATLAB 13.b Simulink with five subsystems that are connected through In and Out Xilinx SG that helps to implement the MLI SVM directly from MATLAB-Simulink (.mdl) file to target FPGA.
Figure 9 illustrates the detailed MATLAB-Simulink design flow of proposed MLI SVM.
- 1)
The first block is the “Clarke’s transformation”, in which the three-phase reference rotating frame are converted into Vα, Vβ.
- 2)
The 2nd block named ‘Sector and γ identifier’ block holds four sub-systems namely reference vector Ma, θ, sector and γ.
- 3)
The next block is calculating the local vector reference frame ) and finding the sub-triangle. Then the switching on-times T1, T2, and T0 are calculated (based on two-level SVM).
- 4)
The fouth subsystem is calculating the LM and OVM boundary based on the reference vector Ma. The subsystem receives the sub-triangles, to sample switching pulse period for the Ts. The switching events of all 27 switching states are stored in LUT.
- 5)
Finally, based on the sector number, sub-triangle number, and Ma boundary, the switching on-times are calculated and mapped into the corresponding switching states.
The performance of the MLI SVM for 0˂ M
a ≤0.99 is simulated on a three-level NPC-MLI drive with 460V DC-link, two 470 μF DC-link capacitors, and 10 kHz switching frequency. The 2.45 kW, 1440 rpm, four poles, and 50 Hz induction motor is used as a load.
Figure 10 shows the inverter line voltage (V
uv) waveform for LM, OVM-1 and OVM-2 operations. Initially, the simulation studies are conducted for M
a = 0.5. Here the line voltage (V
uv) is measured as a 2-level output, because only the SVs and ZVs have participated in the switching sequence. Hence, the V
uv resulted in 2-level output was 147.8 V with THD value of 13.06 %. Next, the same simulation study is extended for the higher modulation ranges (more than 0.5) and resulting in increased voltage magnitude. When the inverter is operated at maximum LM range of 0.907, the V
uv resulted is 268.4 V, as shown in
Figure 10. As expected, the fundamental voltage is increasing linearly by increasing M
a. Here the line voltage at M
a = 0.950 and M
a = 0.990 is observed as 282 V and 295 V, respectively.
6. MATLAB-Simulink built FPGA Habitat for Hardware Implementation
The MATLAB-Simulink support Xilinx ISE project navigator system generator (SG) tool is used for the proposed SVM implementations as it allows the minimization of the time spent for design and cost of implementation.
The architecture of the proposed SVM FPGA implementation is shown in
Figure 12. The FPGA core contains the two main modules: (1) The processing unit; and (2) switching and its mapping unit, as shown in
Figure 13. These modules can perform in parallel that helps to minimize the processing time. The processing unit comprises functional blocks to calculate the V*, sector, sub-triangle, αβ coordinates for LM and OVM trajectory, and logical routes. The mapping unit consists of switching vectors for the corresponding sub-triangles. The switching vector-mapping unit uses memory (LUT). It maps the pre-stored switching sequence for the MLI based on sector, sub-triangle.
The core also considers some key design measures for improving computation accuracy and simplifying hardware design and the fixed-point arithmetic unit is adopted for implementing the calculations. The IP core is designed to operate at 20MHz clock frequency, and high switching frequency, as well as the td, is adjustable. The architecture of the proposed SVM sub-blocks is described, as follows:
3/2 axis converter block: It performs the abc to d-q conversion, which generates the V*and angle (θ).
Ma block: Depending upon the V* requirement, the Ma value of the inverter can be given through the Ma block.
Switching period block: It holds the sampling frequency for the inverter switches.
Sector identification block: This block finds the V* location based on the angle (θ) and V* magnitude.
Triangle identifier block: The block computes V* sub-triangle location.
Trajectory identifier block: This block measures the trajectory identifier (LM, OVM boundary) and V* location based on the Ma values. It also calculates θC and θH angles for OVM operation.
On-time calculation block: This block calculates the respective switching state on-times based on two-level SVM calculations. This unit uses the LUTs to store the switching states and the switching sequences. Lastly, SVM generator unit generates the pulses to the 3-level NPC-MLI after inserting the dead time (td).
Switching state unit: It holds the 27-switching event.
Dead time register block: Holds the timer to add or reduce the td.
SVM Generating Unit: This block produces the pulses to the NPC-MLI after inserting the td.
To simplify the interface with the processor, commands to these registers are routed through a decoder and interface circuit. The clock is acting as a base time for PWM generator and is operated at 100MHz. The overflow flag from PWM generator unit indicates the value of PWM counter when it reaches the maximum count, which can be used to trigger events for the inverter.
6.1. Implementation of the Proposed MLI SVM Scheme in FPGA
The XSG FPGA environment implementation is divided into five stages as follows: MATLAB code generation through XSG, VHDL code generation and its simulation, register transfer level (RTL) file and bit file generation, synthesis and download into target FPGA. Once the RTL file is generated, the proposed SMV architecture RTL view (shown in
Figure 14) and off-line simulation is done to view the generated inverter pulses using ModelSim 5.8e.
Figure 15 shows the ModelSim simulation results for the proposed MLI SVM. It ensures the desired pulse pattern, t
d values. After successful synthesis, the device utilization and power utilization report is generated. It provides the number of logical blocks, LUTs and FFs to be used in architecture. The proposed MLI SVM uses only 3.7% LUT memory space in the FPGA, since it uses simple 2-level SVM, and hence, does not require any additional calculations for calculating the switching on-time. It also minimizes the processing time for LM and OVM operations.
Figure 16a shows the internal structure based on the described SVM implementation design. After RTL synthesis, the net list is saved as an NGC file. Afterwards, the JTAG serial mode (“IEEE Standard 1149.1") configuration interface card is used to download the code to the Target FPGA SPARTAN-III-3A XC3SD1800A-FG676. The JTAG configuration is through the independent boundary scan selection. Then the regenerated bit file is generated. Finally, the developed RTL is converted to bit stream format, and then the UCF is written for pin assignment for the mapping process. Mapping is done to fit the design into the available resource of the target FPGA processor. Finally, placing the code in target FPGA is done.
6.2. MLI SVM FPGA Implementation Results
There are three types of floor views that are generated for the SVM IC, which are overall floor view of device utilization, input port assign view, and output port assign view. From
Figure 16a, it is observed that the proposed code occupies very less resource/area.
Figure 16b shows the input and output port of the proposed implementation. The proposed PWM design I/O’s are mapped properly using UCF based on reduction of the power losses. The implementation consumes only 0.13 W power utilization for one cyclic operation of pulse generation.
Due to the simplification of sub-triangle calculations and OVM-1 switching mapping, the overall device utilization of the proposed SVM implementation becomes 5.88%, which is less than the earlier implementations [
14,
23,
40,
45]. The simplified calculation to find the rhombus sub-triangles selection and OVM-1 on-time calculations are the primary reasons for the memory reduction (around 0.17%), while considering the implementation reported in [
23]. The additional reductions are achieved by way of reducing the LUT usage for operation by repeating switching states.
The processing time of the proposed implementation for LM OVM-1, and OVM-2 are calculated using [
37], and the values are 13.017 μs, 14.561 μs, and 15.532 μs, respectively. From the results, it can be understood that the proposed FPGA implementations are taking the same time for all LM values as 13.017 μs, since sub-system calculation is same for all the range of LM from 0.5 to 0.907. However, during over modulation operations, the processing time for the proposed implementation is increased. The increase in time is because of G
t calculation for the new on-times. Nevertheless, when compared to the early implementations, the time taken for OVM is less for the proposed method [
23], and it is expected while implementing with other family FPGAs. Similarly, considering the device utilization (memory occupied) on FPGA for the proposed implementations, it is considerably lesser. From the above analysis and results, it is clear that the proposed MLI SVM algorithm and its Sparten-3 FPGA implementation improved in terms of their owning mathematical complexity and implementation. Hence, due to this reduced mathematical burden, less device utilization and processing time, the proposed implementations fit to be considered as an IP core that can be incorporated into a System On-Chip with other IP cores and it can greatly reduce the area of a PCB and improve the immunity to interferences for the power converters design.
7. Experimental Results and Analysis
In order to validate the proposed MLI SVM FPGA implementation, the experimentation study is conducted for 2.3 kW three-phase induction motor supplied from three-phase three-level NPC-MLI. The DC-link voltage of the NPC-MLI is maintained at 560 V through an uncontrolled rectifier. The two 100 μF DC-link capacitors C1 and C2 are connected with DC-link to clamp the voltage. The switching frequency of 10 kHz and dead time of 6μsec is used between two complementary switches. The experiment study is performed with modulation index value from 0.7 to maximum over modulation range (Ma = 0.99). During the study, the speed of the motor is recorded using digital tacho-generator.
Figure 17a–d depicts the experimental results of MLI line-voltage (V
uv) and corresponding current (I
u) for M
a = 0.7, M
a = 0.9, M
a = 0.95, and M
a = 0.99, respectively. In the LM region, the inverter output voltage is obtained as 205.2 V and 262.4 V for M
a = 0.7 and M
a = 0.9, respectively. However, while increasing the M
a from LM to OVM, the fundamental voltage is increased linearly. The V
ab for M
a = 0.7 and M
a = 0.9 is obtained as 280.3 V and 292.5 V, respectively. From the results, it can be seen that the inverter voltage and current waveforms are changing based on the modulation index value.
However, the voltage and current waveforms are smooth in all the range of modulation indices. This demonstrates that the proposed SVM is working with full control degree of freedom in the linear and over modulation region.
Figure 18a–d shows the voltage and current harmonics spectrum. The voltage and its corresponding current harmonics in the LM are lesser when compared with those in the OVM regions. The line voltage percentage THD is observed as 10.2%, 12.9%, and 13.5% for M
a = 0.9, M
a = 0.95 and M
a = 0.99, respectively. This increase is due to the non-linearity in the switching on-times in the OVM region operation. Similarly, the current percentage THD in OVM is higher than that in LM. When compared with the other multicarrier and selective harmonics elimination PWM methods, the proposed SVM has lower current and voltage THD in both LM and OVM. In addition, while changing the inverter operation from one region to another region, the voltage and current waveforms are smooth, and there are no abrupt changes.
The induction motor speed variations for the modulation index range from M
a = 0.7 to M
a = 0.99 are measured and plotted in
Figure 19. From the results, it can be seen that the motor speed changes in linear with the SVM modulation index. This illustrates that the proposed SVM can be directly employed to open-loop drives. In closed-loop operation, depending on the control requirement, the proposed SVM voltage reference magnitude and frequency can be changed easily without any additional mathematical calculations.