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Open AccessArticle

Practical Guidelines for Approaching the Implementation of Neural Networks on FPGA for PAPR Reduction in Vehicular Networks

1
GECOS Lab, National School of Applied Sciences, Cadi Ayyad University, 40000 Marrakech, Morocco
2
Department of Signal Theory and Communications, University Carlos III of Madrid, Leganés, 28911 Madrid, Spain
*
Author to whom correspondence should be addressed.
Sensors 2019, 19(1), 116; https://doi.org/10.3390/s19010116
Received: 16 November 2018 / Revised: 12 December 2018 / Accepted: 25 December 2018 / Published: 31 December 2018
(This article belongs to the Special Issue Advances on Vehicular Networks: From Sensing to Autonomous Driving)
Nowadays, the sensor community has become wireless, increasing their potential and applications. In particular, these emerging technologies are promising for vehicles’ communications (V2V) to dramatically reduce the number of fatal roadway accidents by providing early warnings. The ECMA-368 wireless communication standard has been developed and used in wireless sensor networks and it is also proposed to be used in vehicular networks. It adopts Multiband Orthogonal Frequency Division Multiplexing (MB-OFDM) technology to transmit data. However, the large power envelope fluctuation of OFDM signals limits the power efficiency of the High Power Amplifier (HPA) due to nonlinear distortion. This is especially important for mobile broadband wireless and sensors in vehicular networks. Many algorithms have been proposed for solving this drawback. However, complexity and implementations are usually an issue in real developments. In this paper, the implementation of a novel architecture based on multilayer perceptron artificial neural networks on a Field Programmable Gate Array (FPGA) chip is evaluated and some guidelines are drawn suitable for vehicular communications. The proposed implementation improves performance in terms of Peak to Average Power Ratio (PAPR) reduction, distortion and Bit Error Rate (BER) with much lower complexity. Two different chips have been used, namely, Xilinx and Altera and a comparison is also provided. As a conclusion, the proposed implementation allows a minimal consumption of the resources jointly with a higher maximum frequency, higher performance and lower complexity. View Full-Text
Keywords: ECMA-368; peak to average power ratio; neural networks; FPGA implementation ECMA-368; peak to average power ratio; neural networks; FPGA implementation
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Louliej, A.; Jabrane, Y.; Gil Jiménez, V.P.; García Armada, A. Practical Guidelines for Approaching the Implementation of Neural Networks on FPGA for PAPR Reduction in Vehicular Networks. Sensors 2019, 19, 116.

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