Search Results (16)

The deployment of fifth-generation (5G) and beyond-5G wireless communication systems necessitates advanced transceiver architectures to support high data rates, spectrum efficiency, and energy-efficient designs. This paper presents a highly adaptive reconfigurable receiver front-end (HARRF) designed for 5G and satellite applications, integrating a switchable low noise amplifier (LNA) and a single pole double throw (SPDT) switch. The HARRF architecture supports both X-band (8–12 GHz) and K/Ka-band (23–28 GHz) operations, enabling seamless adaptation between radar, satellite communication, and millimeter-wave (mmWave) 5G applications. The proposed receiver front-end employs a 0.15 μ$\mathrm{m}$ pseudomorphic high electron mobility transistor (pHEMT) process, optimised through a three-stage cascaded LNA topology. A switched-tuned matching network is utilised to achieve reconfigurability between X-band and K/Ka-band. Performance evaluations indicate that the X-band LNA achieves a gain of 23–27 dB with a noise figure below 7 dB, whereas the K/Ka-band LNA provides 23–27 dB gain with a noise figure ranging from 2.3–2.6 dB. The SPDT switch exhibits low insertion loss and high isolation, ensuring minimal signal degradation across operational bands. Network analysis and scattering parameter extractions were conducted using advanced design system (ADS) simulations, demonstrating superior return loss, power efficiency, and impedance matching. Comparative analysis with state-of-the-art designs shows that the proposed HARRF outperforms existing solutions in terms of reconfigurability, stability, and wideband operation. The results validate the feasibility of the proposed reconfigurable RF front-end in enabling efficient spectrum utilisation and energy-efficient transceiver systems for next-generation communication networks. Full article

In this paper, a sub-1dB Low Noise Amplifier (LNA) with several gain modes, including amplification and attenuation modes required for the fifth and fourth generations (5G/4G) of mobile network applications, is proposed. Its current consumption is adaptive for every gain mode and varies to lower currents for lower amplifications due to the importance of current consumption for mobile network applications. The proposed LNA features an innovative architecture with a three-core input structure supporting multi-gain modes, achieving high gain and ultra-low noise performance. Additionally, the design integrates a cascade switching mechanism to ensure fast transitions between the gain modes and maintain operational stability. A reconfigurable input structure is introduced to support multiple input stages, enabling the proposed LNA to be compatible with both 5G and 4G applications. The proposed design demonstrates the implementation of seven distinct gain modes with a maximum current consumption of 11.68 mA, achieving proper input matching in each gain mode. The LNA delivers a maximum gain of 20.4 dB with a noise figure of 0.73 dB. Moreover, the most stringent mode switching condition achieved, the ON time, is as short as 1.295 µs, and the gain mode transition speed is an impressive 0.874 µs, ensuring extremely fast mode transitions. The proposed LNA occupies an area of 700 µm × 500 µm and is fabricated using a 65 nm FD-SOI process. Full article

In the literature, three-stage switching networks have been considered for nodes in elastic optical networks, where switches with spectrum conversion capability are placed in the first and third stages (wavelength–space–wavelength—WSW) or only in the second stage (space–wavelength–space—SWS). This paper proposes three-stage switching networks where the switches with spectrum conversion functions are located only in the first stage (wavelength–space–space—WSS) or only in the third stage (space–space–wavelength—SSW). For these networks, the strict-sense non-blocking conditions are derived and proved, and the number of elements required for their construction is assessed. It turns out that the proposed networks can be constructed with 50% fewer tunable spectrum converters than in the WSW networks, and this reduction is even greater in the case of the SWS networks. Full article

This paper presents a charging architecture for the Reconfigurable Cascaded Multilevel converter, which was specifically designed for electric vehicle (EV) powertrain applications. The RCMC topology is capable of executing power conversion and actively managing battery systems concurrently. The active battery management is achieved using the Reconfigurable Battery Module, which regulates the serial connection of cells via a switch pattern. In this paper, the RCMC is directly interfaced with an AC three-phase power system, facilitating the dynamic control over battery cells charging. Its inherent design allows for the implementation of various charging algorithms, customizable to specific requirements, without necessitating additional intermediary power stages. Firstly, an overview of the RCMC topology is given, and an analysis to define the optimal filter inductance is carried out. Subsequently, after the AC system characteristics are explained, two charging algorithms are presented and described: one prioritizes State of Charge (SOC) balancing among battery cells, while the other focuses on minimizing power losses. Moreover, a time estimation computation for the RCMC is carried out considering a two-level AC charging station. The result is compared with the time required for a conventional battery pack. The results show a reduction of 10 s in charging time for a mere 20% increase in SOC. Finally, the experimental setup is presented and used to validate the efficacy of the proposed algorithms. Full article

Currently, the main solution for braking systems for underground electric trackless rubber-tired vehicles (UETRVs) is traditional hydraulic braking systems, which have the disadvantages of hydraulic pressure crawling, the risk of oil leakage and a high maintenance cost. An electro-mechanical-braking (EMB) system, as a type of novel brake-by-wire (BBW) system, can eliminate the above shortcomings and play a significant role in enhancing the intelligence level of the braking system in order to meet the motion control requirements of unmanned UETRVs. Among these requirements, the accurate control of clamping force is a key technology in controlling performance and the practical implementation of EMB systems. In order to achieve an adaptive clamping force control performance of an EMB system, an optimized fuzzy proportional-integral-differential (PID) controller is proposed, where the improved fuzzy algorithm is utilized to adaptively adjust the gain parameters of classic PID. In order to compensate for the deficiency of single-close-loop control and adjusting the brake gap automatically, a cascaded three-closed-loop control architecture with force/position switch technology is established, where a contact point detection method utilizing motor rotor angle displacement is proposed via experiments. The results of the simulation and experiments indicate that the clamping force response of the proposed multi-close-loop Variable Universe Fuzzy–PID (VUF-PID) controller is faster than the multi-closed-loop Fuzzy–PID and cascaded three-close-loop PID controllers. In addition, the chattering of braking force can be suppressed by 17%. This EMB system may rapidly and automatically finish the operation of the overall braking process, including gap elimination, clamping force tracking and gap recovery, which can obviously enhance the precision of the longitudinal motion control of UETRVs. It can thus serve as a BBW actuator of mine autonomous driving electric vehicles, especially in the stage of braking control. Full article

This paper introduces two nonblocking switching fabric architectures designed for multicast connections. These connections are defined using the multislot connection approach, mainly applied in elastic optical networks. In contrast to earlier solutions, this approach assumes that multislot connections are consistently established in adjacent continuous slots. This implies that previously established solutions could not be applied. Our study presents a comprehensive theoretical framework applicable to the general case of three-stage switching fabrics. These fabrics feature external stages equipped with space switches, while the middle stage incorporates conversion switches that operate in the wavelength, time, or frequency domain. In addition, multicast capabilities are deliberately confined to the output-stage switch or switches. A fundamental contribution of this work lies in the formulation of the worst-case scenario, which serves as the foundational basis for deriving strict-sense nonblocking conditions governing such multicast switching fabrics. Our analysis formally demonstrates that the fundamental structure of the multicast nonblocking switching fabric aligns closely with that of the previously examined point-to-point fabric. The only difference is related to the ability to multicast within the output stage of the switching fabric. Full article

This paper presents a single-stage three-port isolated power converter that enables energy conversion among a renewable energy port, a battery energy storage port, and a DC grid port. The proposed converter integrates an interleaved synchronous rectifier boost circuit and a bidirectional full-bridge circuit into a single-stage architecture, which features four power conversion modes, allowing energy adjustment for both the renewable energy and the battery storage energy ports when power is supplied by the renewable energy port. It also features bidirectional functionality that allows the battery storage energy port to provide energy storage through the DC grid port, thereby providing uninterrupted power supply functionality. The converter uses four power switches and two inductors to boost and convert energy from the renewable energy port to the battery storage energy port or to the DC grid port through the bidirectional full-bridge circuit. The converter is also capable of 1 kW power energy conversion by utilizing an adjustable duty cycle with a fixed frequency of 100 kHz and phase-shift control through a built-in pulse width modulation control module of a TMS320F28 series digital signal processor. According to the experimental results, the converter developed in this study can achieve a conversion efficiency of up to 94%. Full article

This article proposes a single-stage, seven-level (7L), switched-capacitor-based grid-connected inverter architecture with a common ground feature. This topology has the ability to boost the output voltage up to three times the input voltage. The proposed topology can diminish the leakage current in grid-connected photovoltaic (GC-PV) applications, and its capacitor voltages are self-balanced without any additional control strategies. The different operating modes are described in detail with their related mathematical expressions. The design of passive components and a detailed power loss analysis are presented. The merits of the proposed structure are demonstrated using a detailed comparative assessment. The grid-connected operation of the proposed inverter structure is simulated in the MATLAB/Simulink environment, and the results are presented. The laboratory prototype of 935 W is built and analyzed to validate the performance of the proposed structure. Full article

In this paper, we investigate the three-stage, wavelength–space–wavelength switching fabric architecture for nodes in elastic optical networks. In general, this switching fabric has r input and output switches with wavelength-converting capabilities and one center-stage space switch that does not change the spectrum used by a connection. This architecture is most commonly denoted by the WSW1 (r, n, k) switching network. We focus on this switching fabric serving simultaneous connection routing. Such routing takes place mostly in synchronous packet networks, where packets for switching arrive at the inputs of a switching network at the same time. Until now, only switching fabrics with up to three inputs and outputs have been extensively investigated. Routing in switching fabrics of greater capacity is estimated based on routing in switches with two or three inputs and outputs. We now improve the results for the switching fabrics with four inputs and outputs and use these results to estimate routing in the switching fabric with an arbitrary number of inputs and outputs. We propose six routing algorithms based on matrix decomposition for simultaneous connection routing. For the proposed routing algorithms, we derive criteria under which they always succeed. The proposed routing algorithms allow the construction of nonblocking switching fabrics with a lower number of wavelength converters and the reduction of the overall switching fabric cost. Full article

The application of the nanosecond pulsed electric field (nsPEF) for biomedical treatments has gained more interest in recent decades due to the development of pulsed power technologies which provides the ability to control the electric field dose applied during tests. In this context, the proposed paper describes a new architecture of solid-state high-voltage pulse generators (SS-HVPG) designed to generate fully customised sequences of quasi-rectangular pulses. The idea is based on the combination of semiconductor switches (IGBT/MOSFET) known for their flexibility and controllability with special magnetic switches to build compact and modular generators. The proposed structure is inspired by the most known pulse generator of Marx, but mixes its two variants for negative and positive polarities. Thus, the polarity of the generated pulses can be freely selected. In addition to that, the use of IGBTs/MOSFET ensures a tunable repetition rate and pulse width. The capacitors are charged via a series of magnetic switches and a flyback DC–DC converter which provides fast and efficient charging and also an adjustable amplitude of the output pulses. The design can be easily simplified giving two other modified structures, based on the same idea, for mono-polar operating (only positive or only negative pulses) with a reduced number of switches. A SPICE simulation of the generator and results of experimental tests carried out on a three stages generator are presented. The obtained results confirm the operating principle and the claimed performances of the new structure. Full article

A dual-mode hybrid step-up circuit for electromagnetic energy harvesting (EVEH) is proposed in this paper, with the merits of continuous output power delivery with and without external vibrations, simple architecture, and no need for extra circuits to start up. The proposed hybrid converter combines a multi-stage voltage multiplier (VM) with a boost regulator, which utilizes the winding inductance of the electromagnetic energy harvester as a boost inductor. With external vibration, the proposed circuit powers the load and stores energy in the super-capacitor through VM mode. When external vibration disappears, it automatically switches to boost mode and powers the load using the energy stored in the supercapacitor. For hybrid mode operation, the number of VM stages is optimized considering the following three aspects: sufficient voltage gains when vibration is on, time durations to provide constant power when vibration is off for as long as possible, and low losses at VM stage. A GaN-based dual-mode hybrid converter is built to verify the output regulation capability with an in-house-designed electromagnetic energy harvester. The outputs of the hybrid circuit achieve 4.05 V and 1.64 mW at a 100-Hz external vibration frequency and an acceleration of 0.7 g. The peak efficiency of the proposed hybrid converter reaches 60.7%. When external vibration disappears, the circuit is able to maintain a stable output for 13 s with a super-capacitor of 0.1 F. Full article

This article proposes a holistic codesign optimization framework (COF) to simultaneously optimize a power conversion stage and a controller stage using a dual-loop control scheme for multiphase SiC-based DC/DC converters. In this study, the power conversion stage adopts a non-isolated interleaved boost converter (IBC). Besides, the dual-loop control scheme uses type-III controllers for both inner- and outer- loops to regulate the output voltage of the IBC and tackle its non-minimum phase issue. Based on the converter architecture, a multi-objective optimization (MOO) problem including four objective functions (OFs) is properly formulated for the COF. To this end, total input current ripple, total weight of inductors and total power losses are selected as three OFs for the power conversion stage whilst one OF called integral of time-weighted absolute error is considered for the controller stage. The OFs are expressed in analytical forms. To solve the MOO problem, the COF utilizes a non-dominated sorted genetic algorithm (NSGA-II) in combination with an automatic decision-making algorithm to obtain the optimal design solution including the number of phases, switching frequency, inductor size, and the control parameters of type-III controllers. Furthermore, compared to the conventional ‘k-factor’ based controller, the optimal controller exhibits better dynamic responses in terms of undershoot/overshoot and settling time for the output voltage under load disturbances. Moreover, a liquid-cooled SiC-based converter is prototyped and its optimal controller is implemented digitally in dSPACE MicroLabBox. Finally, the experimental results with static and dynamic tests are presented to validate the outcomes of the proposed COF. Full article

Elastic optical networks flexibly allocate bandwidth to a connection for improving utilization efficiency. The paper considers an optical node architecture that is similar to a three-stage Clos network for elastic optical networks. The architecture, which employs space switching in the first and the third stages and wavelength switching in the second stage, is called an S-W-S switching fabric. In this paper, we propose a graph-theoretic approach and different routing algorithms to derive the sufficient conditions under which an S-W-S switching fabric will be rearrangeable nonblocking and repackable nonblocking. The proposed rearrangeable and repackable nonblocking S-W-S switching fabrics for connections with limited bandwidths consume around half the number of middle wavelength switches compared to strictly nonblocking S-W-S switching fabrics. Full article

In future dc distributed power systems, high performance high voltage dc-dc converters with redundancy ability are welcome. However, most existing high voltage dc-dc converters do not have redundancy ability. To solve this problem, a wide load range zero-voltage switching (ZVS) three-level (TL) dc-dc converter is proposed, which has some definitely good features. The primary switches have reduced voltage stress, which is only V_in/2. Moreover, no extra clamping component is needed, which results simple primary structure. Redundancy ability can be obtained by both primary and secondary sides, which means high system reliability. With proper designing of magnetizing inductance, all primary switches can obtain ZVS down to 0 output current, and in addition, the added conduction loss can be neglected. TL voltage waveform before the output inductor is obtained, which leads small volume of the output filter. Four secondary MOSFETs can be switched in zero-current switching (ZCS) condition over wide load range. Finally, both the primary and secondary power stages are modular architecture, which permits realizing any given system specifications by low voltage, standardized power modules. The operation principle, soft switching characteristics are presented in this paper, and the experimental results from a 1 kW prototype are also provided to validate the proposed converter. Full article

This paper presents a multi-stage noise shaping (MASH) switched-capacitor (SC) sigma-delta (ΣΔ) analog-to-digital converter (ADC) composed of an analog modulator with an on-chip noise cancellation logic and a reconfigurable digital decimator for MEMS digital gyroscope applications. A MASH 2-1-1 structure is employed to guarantee an absolutely stable modulation system. Based on the over-sampling and noise-shaping techniques, the core modulator architecture is a cascade of three single-loop stages containing feedback paths for systematic optimization to avoid deterioration in conversion accuracy caused by capacitor mismatch. A digital noise cancellation logic is also included to eliminate residual quantization errors in the former two stages, and those in the last stage are shaped by a fourth-order modulation. A multi-rate decimator follows the analog modulator to suit variable gyroscope bandwidth. Manufactured in a standard 0.35 μm CMOS technology, the whole chip occupies an area of 3.8 mm². Experimental results show a maximum signal-to-noise ratio (SNR) of 100.2 dB and an overall dynamic range (DR) of 107.6 dB, with a power consumption of 3.2 mW from a 5 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 165.6 dB. Full article