Search Results (20)

In this study, we propose a bidirectional chemical sensor platform based on a reconfigurable ion-sensitive field-effect transistor (R-ISFET) architecture. The device incorporates Ni-silicide Schottky barrier source/drain (S/D) contacts, enabling ambipolar conduction and bidirectional turn-on behavior for both p-type and n-type configurations. Channel polarity is dynamically controlled via the program gate (PG), while the control gate (CG) suppresses leakage current, enhancing operational stability and energy efficiency. A dual-control-gate (DCG) structure enhances capacitive coupling, enabling sensitivity beyond the Nernst limit without external amplification. The extended-gate (EG) architecture physically separates the transistor and sensing regions, improving durability and long-term reliability. Electrical characteristics were evaluated through transfer and output curves, and carrier transport mechanisms were analyzed using band diagrams. Sensor performance—including sensitivity, hysteresis, and drift—was assessed under various pH conditions and external noise up to 5 V_pp (i.e., peak-to-peak voltage). The n-type configuration exhibited high mobility and fast response, while the p-type configuration demonstrated excellent noise immunity and low drift. Both modes showed consistent sensitivity trends, confirming the feasibility of complementary sensing. These results indicate that the proposed R-ISFET sensor enables selective mode switching for high sensitivity and robust operation, offering strong potential for next-generation biosensing and chemical detection. Full article

Mg-ion-implanted layers in a GaN substrate after annealing were investigated. Implanted Mg atoms precipitated along the edges of crystal defects were observed using 3D-APT. The breakdown characteristics of a GaN double-diffused vertical MISFET (DMISFET) fabricated via triple ion implantation are presented. A DMISFET with Si-ion-implanted source regions was formed in Mg-ion-implanted p-base regions, which were isolated from adjacent devices by N-ion-implanted edge termination regions. A threshold voltage of −0.5 V was obtained at a drain voltage of 0.5 V for the fabricated vertical MISFET with an estimated Mg surface concentration of 5 × 10¹⁸ cm⁻³. The maximum drain current and maximum transconductance in a saturation region of V_ds = 100 V were 2.8 mA/mm and 0.5 mS/mm at a gate voltage of 15 V, respectively. The breakdown voltage in the off-state was 417 V. The breakdown points were determined by the boundary regions between the N- and Mg-implanted regions. By improving heat annealing methods, ion-implanted GaN DMISFETs can be a promising candidate for future high-voltage and high-power applications. Full article

This paper proposes a circuit model of a cross-coupled CMOS AC–DC charge pump (XC–CP) operating in the subthreshold region. The aim is to improve the efficiency of designing XC–CPs with a variety of specifications, e.g., input and output voltages and AC input frequency. First, it is shown that the output resistance (Ro) of XC–CP is much higher than those of CPs with single diodes (SD–CP) and ultra-low-power diodes (ULPD–CP) as charge transfer switches (CTSs). Second, the reason behind the above feature of XC–CP, identified by a simple model, is that the gate-to-source voltages of CTS MOSFETs are independent of the output voltage of the CP. Third, the high but finite Ro of XC–CP is explainable with a more accurate model that includes the dependence of the saturation current of MOSFETs operating in the subthreshold region on the drain-to-source voltage, which is a function of the output voltage of CP. The model is in good agreement with measured and simulated results of XC–, SD–, and ULPD–CPs fabricated in a 250 nm CMOS. Full article

In this study, a frequency doubler that consists of a tunnel field-effect transistor (TFET) with dual pocket doping is proposed, and its operation is verified using technology computer-aided design (TCAD) simulations. The frequency-doubling operation is important to having symmetrical current characteristics, which eliminate odd harmonics and the need for extra filter circuitry. The proposed TFET has intrinsically bidirectional and controllable currents that can be implemented by pocket doping, which is located at the junction between the source/drain (S/D) and the channel region, to modify tunneling probabilities. The source-to-channel (I_SC) and channel-to-drain currents (I_CD) can be independently changed by managing each pocket doping concentration on the source and drain sides (N_S,POC and N_D,POC). After that, the current matching process was investigated through N_S,POC and N_D,POC splits, respectively. However, it was found that the optimized doping condition achieved at the device level (namely, a transistor evaluation) is not suitable for a frequency doubler operation because the voltage drop generated by a load resistor in the frequency doubler circuit configuration causes the currents to be unbalanced between I_SC and I_CD. Therefore, after symmetrical current matching was performed by optimizing N_S,POC and N_D,POC at the circuit level, it was clearly seen that the output frequency was doubled in comparison to the input sinusoidal signal. In addition, the effects of the S/D and pocket doping variations that can occur during process integration were investigated to determine how much frequency multiplications are affected, and these variations have the immunity of S/D doping and pocket doping length changes. Furthermore, the impact of device scaling with gate length (L_G) variations was evaluated. Based on these findings, the proposed frequency doubler is anticipated to offer benefits for circuit design and low-power applications compared to the conventional one. Full article

This paper examines the performance of a Gate-Engineered Gate-All-Around Charge Plasma Nanowire Field Effect Transistor (GAA-DMG-GS-CP NW-FET) and the implementation of a common source (CS) amplifier circuit. The proposed GAA-DMG-GS-CP NW-FET incorporates dual-material gate (DMG) and gate stack (GS) as gate engineering techniques and its analog/RF performance parameters are compared to those of the Gate-All-Around Single-Material Gate Charge Plasma Nanowire Field Effect Transistor (GAA-SMG-CP NW-FET) device. Both Gate-All-Around (GAA) devices are designed using the Silvaco TCAD tool. GAA structures have demonstrated good gate control because the gate holds the channel, which is an inherent advantage for both devices discussed herein. The charge plasma dopingless technique is used, in which the source and drain regions are formed using metal contacts and necessary work functions rather than doping. This dopingless technique eliminates the need for doping, reducing fluctuations caused by random dopants and lowering the device’s thermal budget. Gate engineering techniques such as DMG and GS significantly improved the current characteristics which played a crucial role in obtaining maximum gain for circuit designs. The lookup table (LUT) approach is used in the implementation of the CS amplifier circuit with the proposed device. The transient response of the circuit is analyzed with both the device structures where the gain achieved for the CS amplifier circuit using the proposed GAA-DMG-GS-CP NW-FET is 15.06 dB. The superior performance showcased by the proposed GAA-DMG-GS-CP NW-FET device with analog, RF and circuit analysis proves its strong candidature for future nanoscale and low-power applications. Full article

In this paper, a novel scheme for source/drain-first (S/D-first) full bottom dielectric isolation (BDI), i.e., Full BDI_Last, with integration of a sacrificial Si_0.5Ge_0.5 layer was proposed and demonstrated in a stacked Si nanosheet gate-all-around (NS-GAA) device structure using TCAD simulations. The proposed full BDI scheme flow is compatible with the main process flow of NS-GAA transistor fabrication and provides a large window for process fluctuations, such as the thickness of the S/D recess. It is an ingenious solution to insert the dielectric material under the source, drain and gate regions to remove the parasitic channel. Moreover, because the S/D-first scheme decreases the problem of high-quality S/D epitaxy, the innovative fabrication scheme introduces full BDI formation after S/D epitaxy to mitigate the difficulty of providing stress engineering in the full BDI formation before S/D epitaxy (Full BDI_First). The electrical performance of Full BDI_Last is demonstrated by a 4.78-fold increase in the drive current compared to Full BDI_First. Furthermore, compared to traditional punch through stoppers (PTSs), the proposed Full BDI_Last technology could potentially provide an improved short channel behavior and good immunity against parasitic gate capacitance in NS-GAA devices. For the assessed inverter ring oscillator (RO), applying the Full BDI_Last scheme allows the operating speed to be increased by 15.2% and 6.2% at the same power, or alternatively enables an 18.9% and 6.8% lower power consumption at the same speed compared with the PTS and Full BDI_First schemes, respectively. The observations confirm that the novel Full BDI_Last scheme incorporated into an NS-GAA device can be utilized to enable superior characteristics to benefit the performance of integrated circuits. Full article

A surface-potential-based analytical large-signal model, which is applicable to both ballistic and quasi-ballistic transport in InGaAs high electron mobility transistors, is developed. Based on the one-flux method and a new transmission coefficient, a new two-dimensional electron gas charge density is derived, while the dislocation scattering is novelly taken into account. Then, a unified expression for $E_f$ valid in all the regions of gate voltages is determined, which is utilized to directly calculate the surface potential. The flux is used to derive the drain current model incorporating important physical effects. Moreover, the gate-source capacitance $C_{gs}$ and gate-drain capacitance $C_{gd}$ are obtained analytically. The model is extensively validated with the numerical simulations and measured data of the InGaAs HEMT device with the gate length of 100 nm. The model is in excellent agreement with the measurements under I-V, C-V, small-signal conditions, and large-signal conditions. Full article

In this paper, a novel ferroelectric-based electrostatic doping (Fe-ED) nanosheet tunneling field-effect transistor (TFET) is proposed and analyzed using technology computer-aided design (TCAD) Sentaurus simulation software. By inserting a ferroelectric film into the polarity gate, the electrons and holes are induced in an intrinsic silicon film to create the p-source and the n-drain regions, respectively. Device performance is largely independent of the chemical doping profile, potentially freeing it from issues related to abrupt junctions, dopant variability, and solid solubility. An improved ON-state current and I_ON/I_OFF ratio have been demonstrated in a 3D-calibrated simulation, and the Fe-ED NSTFET’s on-state current has increased significantly. According to our study, Fe-ED can be used in versatile reconfigurable nanoscale transistors as well as highly integrated circuits as an effective doping strategy. Full article

Impacts of source/drain (S/D) recess engineering on the device performance of both the gate-all-around (GAA) nanosheet (NS) field-effect transistor (FET) and FinFET have been comprehensively studied at 5 nm node technology. TCAD simulation results show that the device off-leakage, including subthreshold leakage through the channel (I_sub) and punch-through leakage (I_PT) in the sub-channel, is strongly related to the S/D recess process. Firstly, device electrical characteristics such as current density distributions, On/Off-state current (I_on, I_off), subthreshold swing (SS), RC delay, and gate capacitance (C_gg) are investigated quantitatively for DC/AC performance evaluation and comparison according to S/D lateral recess depth (L_rcs) variations. For both device types, larger L_rcs will result in a shorter effective channel length (L_eff), so that the I_on and I_off simultaneously increase. At the constant I_off, the L_rcs can be optimized to enhance the device’s drivability by ~3% and improve the device’s RC delay by ~1.5% due to a larger C_gg as a penalty. Secondly, S/D over recess depth (H_rcs) in the vertical direction severely affects the punch-through leakage in the Sub-Fin or bottom parasitic channel region. The NSFET exhibits less I_off sensitivity provided that it can be well controlled under 12 nm since the bottom parasitic channel is still gated. Furthermore, with both H_rcs and L_rcs accounted for in the device fabrication, the NSFET still shows better control of the off-leakage in the intrinsic and bottom parasitic channel regions and ~37% leakage reduction compared with FinFETs, which would be critical to enable further scaling and the low standby power application. Finally, the S/D recess engineering strategy has been given: a certain lateral recess could be optimized to obtain the best drive current and RC delay, while the vertical over-recess should be in tight management to keep the static power dissipation as low as possible. Full article

We propose an ambipolar chitosan synaptic transistor that effectively responds to binary neuroplasticity. We fabricated the synaptic transistors by applying a chitosan electric double layer (EDL) to the gate insulator of the excimer laser annealed polycrystalline silicon (poly-Si) thin-film transistor (TFT) with Ni-silicide (NiSi) Schottky-barrier source/drain (S/D) junction. The undoped poly-Si channel and the NiSi S/D contact allowed conduction by electrons and holes, resulting in artificial synaptic behavior in both p-type and n-type regions. A slow polarization reaction by the mobile ions such as anions (CH₃COO⁻ and OH⁻) and cations (H⁺) in the chitosan EDL induced hysteresis window in the transfer characteristics of the ambipolar TFTs. We demonstrated the excitatory post-synaptic current modulations and stable conductance modulation through repetitive potentiation and depression pulse. We expect the proposed ambipolar chitosan synaptic transistor that responds effectively to both positive and negative stimulation signals to provide more complex information process versatility for bio-inspired neuromorphic computing systems. Full article

The electrical performance of the back-channel etched Indium–Gallium–Zinc–Oxide (IGZO) thin-film transistors (TFTs) with copper (Cu) source and drain (S/D) which are patterned by a selective etchant was investigated. The Cu S/D were fabricated on a molybdenum (Mo) layer to prevent the Cu diffusion to the active layer (IGZO). We deposited the Cu layer using thermal evaporation and performed the selective wet etching of Cu using a non-acidic special etchant without damaging the IGZO active layer. We fabricated the IGZO TFTs and compared the performance in terms of linear and saturation region mobility, threshold voltage and ON current (I_ON). The IGZO TFTs with Mo/Cu S/D exhibit good electrical properties, as the linear region mobility is 12.3 cm²/V-s, saturation region mobility is 11 cm²/V-s, threshold voltage is 1.2 V and I_ON is 3.16 × 10⁻⁶ A. We patterned all the layers by a photolithography process. Finally, we introduced a SiO₂-ESL layer to protect the device from external influence. The results show that the prevention of Cu and the introduced ESL layer enhances the electrical properties of IGZO TFTs. Full article

The fin field-effect transistor (FinFET) has been the mainstream technology on the VLSI platform since the 22 nm node. The silicon-on-insulator (SOI) FinFET, featuring low power consumption, superior computational power and high single-event effect (SEE) resistance, shows advantages in integrated circuits for space applications. In this work, a rad-hard design methodology for SOI FinFETs is shown to improve the devices’ tolerance against the Total Ionizing Dose (TID) effect. Since the fin height direction enables a new dimension for design optimization, a 3D Source/Drain (S/D) design combined with a gate dielectric de-footing technique, which has been readily developed for the 14 nm node FinFETs, is proposed as an effective method for SOI FinFETs’ TID hardening. More importantly, the governing mechanism is thoroughly investigated using fully calibrated technology computer-aided design (TCAD) simulations to guide design optimizations. The analysis demonstrates that the 3D rad-hard design can modulate the leakage path in 14 nm node n-type SOI FinFETs, effectively suppress the transistors’ sensitivity to the TID charge and reduce the threshold voltage shift by >2×. Furthermore, the rad-hard design can reduce the electric field in the BOX region and lower its charge capture rate under radiation, further improving the transistor’s robustness. Full article

Silicon german ium (SiGe) has attracted significant attention for applications in the source/drain (S/D) regions of p-type metal-oxide-semiconductor field-effect transistors (p-MOSFETs). However, in SiGe, as the Ge concentration increases, high-density defects are generated, which limit its applications. Therefore, several techniques have been developed to minimize defects; however, these techniques require relatively thick epitaxial layers and are not suitable for gate-all-around FETs. This study examined the effect of Ge concentration on the embedded SiGe source/drain region of a logic p-MOSFET. The strain was calculated through nano-beam diffraction and predictions through a simulation were compared to understand the effects of stress relaxation on the change in strain applied to the Si channel. When the device performance was evaluated, the drain saturation current was approximately 710 µA/µm at an off current of 100 nA/µm with a drain voltage of 1 V, indicating that the current was enhanced by 58% when the Ge concentration was optimized. Full article

Channel shape dependency on device instability for amorphous indium–gallium–zinc oxide (a-IGZO) thin film transistors (TFTs) is investigated by using various channel shape devices along with systematic electrical characterization including DC I-V characeristics and bias temperature stress tests. a-IGZO TFTs with various channel shapes such as zigzag, circular, and U-type channels are implemented and their vertical and lateral electric field stress (E-field) effects are systematically tested and analyzed by using an experimental and modeling study. Source and drain (S/D) electrode asymmetry and vertical E-field effects on device instability are neglibible, whereas the lateral E-field effects significantly affect device instability, particularly for zigzag channel shape, compared to circular and U-type TFTs. Moreover, charge trapping time (τ) for zigzag-type a-IGZO TFTs is extracted as 3.8 × 10⁴, which is at least three-times smaller than those of other channel-type a-IGZO TFTs, hinting that local E-field enhancement can critically affect the device reliability. The Technology Computer Aided Design (TCAD) simulation results reveal the locally enhanced E-field at both corner region in the channel in a quantitative mode and its correlation with hemisphere radius (ρ) values. Full article

Among various wearable health-monitoring electronics, electronic textiles (e-textiles) have been considered as an appropriate alternative for a convenient self-diagnosis approach. However, for the realization of the wearable e-textiles capable of detecting subtle human physiological signals, the low-sensing performances still remain as a challenge. In this study, a fiber transistor-type ultra-sensitive pressure sensor (FTPS) with a new architecture that is thread-like suspended dry-spun carbon nanotube (CNT) fiber source (S)/drain (D) electrodes is proposed as the first proof of concept for the detection of very low-pressure stimuli. As a result, the pressure sensor shows an ultra-high sensitivity of ~3050 Pa⁻¹ and a response/recovery time of 258/114 ms in the very low-pressure range of <300 Pa as the fiber transistor was operated in the linear region (V_DS = −0.1 V). Also, it was observed that the pressure-sensing characteristics are highly dependent on the contact pressure between the top CNT fiber S/D electrodes and the single-walled carbon nanotubes (SWCNTs) channel layer due to the air-gap made by the suspended S/D electrode fibers on the channel layers of fiber transistors. Furthermore, due to their remarkable sensitivity in the low-pressure range, an acoustic wave that has a very tiny pressure could be detected using the FTPS. Full article