Search Results (30)

As semiconductor manufacturing advances into the angstrom-scale era characterized by three-dimensional integration, conventional metrology technologies face fundamental limitations regarding accuracy, speed, and non-destructiveness. Although optical spectroscopy has emerged as a prominent research focus, its application in complex manufacturing scenarios continues to confront significant technical barriers. This review establishes three concrete objectives: To categorize AI–optical spectroscopy integration paradigms spanning forward surrogate modeling, inverse prediction, physics-informed neural networks (PINNs), and multi-level architectures; to benchmark their efficacy against critical industrial metrology challenges including tool-to-tool (T2T) matching and high-aspect-ratio (HAR) structure characterization; and to identify unresolved bottlenecks for guiding next-generation intelligent semiconductor metrology. By categorically elaborating on the innovative applications of AI algorithms—such as forward surrogate models, inverse modeling techniques, physics-informed neural networks (PINNs), and multi-level network architectures—in optical spectroscopy, this work methodically assesses the implementation efficacy and limitations of each technical pathway. Through actual application case studies involving J-profiler software 5.0 and associated algorithms, this review validates the significant efficacy of AI technologies in addressing critical industrial challenges, including tool-to-tool (T2T) matching. The research demonstrates that the fusion of AI and optical spectroscopy delivers technological breakthroughs for semiconductor metrology; however, persistent challenges remain concerning data veracity, insufficient datasets, and cross-scale compatibility. Future research should prioritize enhancing model generalization capability, optimizing data acquisition and utilization strategies, and balancing algorithm real-time performance with accuracy, thereby catalyzing the transformation of semiconductor manufacturing towards an intelligence-driven advanced metrology paradigm. Full article

The precise identification and non-destructive measurement of structural features and defects in semiconductor wafers are essential for ensuring process integrity and sustaining high yield in advanced manufacturing environments. Unlike conventional measurement techniques, scanning acoustic microscopy (SAM) is an advanced method that provides detailed visualizations of both surface and internal wafer structures. However, in practical industrial applications, the scanning time and image quality of SAM significantly impact its overall performance and utility. Prolonged scanning durations can lead to production bottlenecks, while suboptimal image quality can compromise the accuracy of defect detection. To address these challenges, this study proposes LinearTGAN, an improved generative adversarial network (GAN)-based model specifically designed to improve the resolution of linear acoustic wafer images acquired by the breakthrough rotary scanning acoustic microscopy (R-SAM) system. Empirical evaluations demonstrate that the proposed model significantly outperforms conventional GAN-based approaches, achieving a Peak Signal-to-Noise Ratio (PSNR) of 29.479 dB, a Structural Similarity Index Measure (SSIM) of 0.874, a Learned Perceptual Image Patch Similarity (LPIPS) of 0.095, and a Fréchet Inception Distance (FID) of 0.445. To assess the measurement aspect of LinearTGAN, a lightweight defect segmentation module was integrated and tested on annotated wafer datasets. The super-resolved images produced by LinearTGAN significantly enhanced segmentation accuracy and improved the sensitivity of microcrack detection. Furthermore, the deployment of LinearTGAN within the R-SAM system yielded a 92% improvement in scanning performance for 12-inch wafers while simultaneously enhancing image fidelity. The integration of super-resolution techniques into R-SAM significantly advances the precision, robustness, and efficiency of non-destructive measurements, highlighting their potential to have a transformative impact in semiconductor metrology and quality assurance. Full article

Rapid advancement in the nanotechnology and semiconductor industries has driven the demand for fast, precise measurement systems. Atomic force microscopy (AFM) is a standout metrology technique due to its high precision and wide applicability. However, when operated at high speeds, the quality of AFM images often deteriorates, especially in areas where sharp topographic features are present. This occurs because the feedback speed of the Z-scanner cannot keep up with the sample height changes during raster scanning. This study presents a simple variable scan speed control strategy for improving AFM imaging speed while maintaining the image quality obtained at low scan speeds. The proposed strategy aims to leverage the similarity in the height profiles between successive scan lines. The topographic information collected from the previous line scan is used to assess the surface complexity and to adjust the scan speed for the following line scan. The AFM system with this variable speed control algorithm was found to reduce the scan time needed for one AFM image by over 50% compared to the fixed-speed scanning while maintaining the similar level of accuracy. The calculated mean square errors (MSEs) show that the combination of speed adjustments and preemptive surface topography prediction has successfully allowed us to suppress the potential oscillations during the speed adjustment process, thereby enhancing the stability of the adaptive AFM system as well. Full article

This study proposes a novel framework integrating long short-term memory (LSTM) networks with Bayesian optimization (BO) to address process–device co-optimization challenges in trench-gate metal–oxide–semiconductor field-effect transistor (MOSFET) manufacturing. Conventional TCAD simulations, while accurate, suffer from computational inefficiency in high-dimensional parameter spaces. To overcome this, an LSTM-based TCAD proxy model is developed, leveraging hierarchical temporal dependencies to predict electrical parameters (e.g., breakdown voltage, threshold voltage) with deviations below 3.5% compared to physical simulations. The model, validated on both N-type and P-type 20 V trench MOS devices, outperforms conventional RNN and GRU architectures, reducing average relative errors by 1.78% through its gated memory mechanism. A BO-driven inverse optimization methodology is further introduced to navigate trade-offs between conflicting objectives (e.g., minimizing on-resistance while maximizing breakdown voltage), achieving recipe predictions with a maximum deviation of 8.3% from experimental data. Validation via TCAD-simulated extrapolation tests and SEM metrology confirms the framework’s robustness under extended operating ranges (e.g., 0–40 V drain voltage) and dimensional tolerances within industrial specifications. The proposed approach establishes a scalable, data-driven paradigm for semiconductor manufacturing, effectively bridging TCAD simulations with production realities while minimizing empirical trial-and-error iterations. Full article

In recent years, the semiconductor industry has embraced advanced artificial intelligence (AI) techniques to facilitate intelligent manufacturing throughout their organizations, with particular emphasis on virtual metrology (VM) systems. Nonetheless, the practical application of data-driven virtual metrology for product quality inspection encounters notable hurdles, such as annotating inspections in highly dynamic industrial environments. This leads to complexities and significant expenses in data acquisition and VM model training. To address the challenges, we delved into transfer learning (TL). TL offers a valuable avenue for knowledge sharing and scaling AI models across various processes and factories. At the same time, research on transfer learning in VM systems remains limited. We propose a novel parameter transfer learning (PTL) architecture for VM systems and examine its application in industrial process automation. We implemented cross-factory and cross-recipe transfer learning to enhance VM performance and offer practical advice on adapting TL to meet individual needs and use cases. By leveraging extensive data from Seagate wafer factories, known for their large-scale and high-dimensional nature, we achieved significant PTL performance improvements across multiple performance metrics, with the true positive rate (TPR) increasing by 29% and false positive rate (FPR) decreasing by 43% in the cross-factory study. In contrast, in the cross-recipe study, TPR increased by 27.3% and FPR decreased by 6.5%. With our proposed PTL architecture and its performance achievements, insufficient data from the new manufacturing sites, new production lines and new products are addressed with shorter VM model training time and smaller computational power with strong final quality prediction confidence. Full article

Semiconductor layers employed in fabricating advanced node devices are becoming thinner and their electrical properties are diverging from those established for highly crystalline standards. Since these properties also change as a function of depth within the film, accurate carrier profiling solutions are required. The Differential Hall Effect (DHE) technique has the unique capability of measuring mobility and carrier concentration (active carriers) through the depth of a semiconductor film. It comprises making successive sheet resistance and sheet Hall coefficient measurements as the thickness of the electrically active layer at a test region is reduced through successive material removal steps. Difference equations are then used to process the data and plot the desired depth profiles. The fundamentals of DHE were established in 1960s. Recently, the adaption of electrochemical processing for the material removal steps, and the integration of all other functionalities in a Differential Hall Effect Metrology (DHEM) tool, has made this technique more practical and accurate and improved its depth resolution to a sub-nm range. In this contribution, we review the development history of this important technique and present data from recent characterization work carried out on Si, Ge and SiGe layers. Full article

Thin film lithium niobate (TFLN) has become a promising material platform for large scale photonic integrated circuits (PICs). As an indispensable component in PICs, on-chip electrically tunable narrow-linewidth lasers have attracted widespread attention in recent years due to their significant applications in high-speed optical communication, coherent detection, precision metrology, laser cooling, coherent transmission systems, light detection and ranging (LiDAR). However, research on electrically driven, high-power, and narrow-linewidth laser sources on TFLN platforms is still in its infancy. This review summarizes the recent progress on the narrow-linewidth compact laser sources boosted by hybrid TFLN/III-V semiconductor integration techniques, which will offer an alternative solution for on-chip high performance lasers for the future TFLN PIC industry and cutting-edge sciences. The review begins with a brief introduction of the current status of compact external cavity semiconductor lasers (ECSLs) and recently developed TFLN photonics. The following section presents various ECSLs based on TFLN photonic chips with different photonic structures to construct external cavity for on-chip optical feedback. Some conclusions and future perspectives are provided. Full article

Cu pillars serve as interconnecting structures for 3D chip stacking in heterogeneous integration, whose height uniformity directly impacts chip yield. Compared to typical methods such as white-light interferometry and confocal microscopy for measuring Cu pillars, microscopic fringe projection profilometry (MFPP) offers obvious advantages in throughput, which has great application value in on-line bump height measurement in wafer-level packages. However, Cu pillars with large curvature and smooth surfaces pose challenges for signal detection. To enable the MFPP system to measure both the top region of the Cu pillar and the substrate, which are necessary for bump height measurement, we utilized rigorous surface scattering theory to solve the bidirectional reflective distribution function of the Cu pillar surface. Subsequently, leveraging the scattering distribution properties, we propose a hybrid bright-dark-field MFPP system concept capable of detecting weakly scattered signals from the top of the Cu pillar and reflected signals from the substrate. Experimental results demonstrate that the proposed MFPP system can measure the height of Cu pillars with an effective field of view of 15.2 mm × 8.9 mm and a maximum measurement error of less than 0.65 μm. Full article

After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures. Full article

Recently, considerable work has been directed at the development of an ultracompact X-ray free-electron laser (UCXFEL) based on emerging techniques in high-field cryogenic acceleration, with attendant dramatic improvements in electron beam brightness and state-of-the-art concepts in beam dynamics, magnetic undulators, and X-ray optics. A full conceptual design of a 1 nm (1.24 keV) UCXFEL with a length and cost over an order of magnitude below current X-ray free-electron lasers (XFELs) has resulted from this effort. This instrument has been developed with an emphasis on permitting exploratory scientific research in a wide variety of fields in a university setting. Concurrently, compact FELs are being vigorously developed for use as instruments to enable next-generation chip manufacturing through use as a high-flux, few nm lithography source. This new role suggests consideration of XFELs to urgently address emerging demands in the semiconductor device sector, as identified by recent national need studies, for new radiation sources aimed at chip manufacturing. Indeed, it has been shown that one may use coherent X-rays to perform 10–20 nm class resolution surveys of macroscopic, cm scale structures such as chips, using ptychographic laminography techniques. As the XFEL is a very promising candidate for realizing such methods, we present here an analysis of the issues and likely solutions associated with extending the UCXFEL to harder X-rays (above 7 keV), much higher fluxes, and increased levels of coherence, as well as methods of applying such a source for ptychographic laminography to microelectronic device measurements. We discuss the development path to move the concept to rapid realization of a transformative XFEL-based application, outlining both FEL and metrology system challenges. Full article

Optical imaging and photolithography hold the promise of extensive applications in the branch of nano-electronics, metrology, and the intricate domain of single-molecule biology. Nonetheless, the phenomenon of light diffraction imposes a foundational constraint upon optical resolution, thus presenting a significant barrier to the downscaling aspirations of nanoscale fabrication. The strategic utilization of surface plasmons has emerged as an avenue to overcome this diffraction-limit problem, leveraging their inherent wavelengths. In this study, we designed a pioneering and two-staged resolution, by adeptly compressing optical energy at profound sub-wavelength dimensions, achieved through the combination of propagating surface plasmons (PSPs) and localized surface plasmons (LSPs). By synergistically combining this plasmonic lens with parallel patterning technology, this economic framework not only improves the throughput capabilities of prevalent photolithography but also serves as an innovative pathway towards the next generation of semiconductor fabrication. Full article

The semiconductor industry is one of the most technology-evolving and capital-intensive market sectors. Effective inspection and metrology are necessary to improve product yield, increase product quality and reduce costs. In recent years, many types of semiconductor manufacturing equipments have been equipped with sensors to facilitate real-time monitoring of the production processes. These production-state and equipment-state sensor data provide an opportunity to practice machine-learning technologies in various domains, such as anomaly/fault detection, maintenance scheduling, quality prediction, etc. In this work, we focus on the soft-sensing regression problem in metrology systems, which uses sensor data collected during wafer processing steps to predict impending inspection measurements that used to be measured in wafer inspection and metrology systems. We proposed a regressor based on Long Short-term Memory network and devised two distinct loss functions for the purpose of the training model. Although the assessment of our prediction errors by engineers is subjective, a novel piece-wise evaluation metric was introduced to evaluate model accuracy in a mathematical way. Our experimental results showcased that the proposed model is capable of achieving both accurate and early prediction across various types of inspections in complicated manufacturing processes. Full article

Recent advancements in 3D deep learning have led to significant progress in improving accuracy and reducing processing time, with applications spanning various domains such as medical imaging, robotics, and autonomous vehicle navigation for identifying and segmenting different structures. In this study, we employ the latest developments in 3D semi-supervised learning to create cutting-edge models for the 3D object detection and segmentation of buried structures in high-resolution X-ray semiconductors scans. We illustrate our approach to locating the region of interest of the structures, their individual components, and their void defects. We showcase how semi-supervised learning is utilized to capitalize on the vast amounts of available unlabeled data to enhance both detection and segmentation performance. Additionally, we explore the benefit of contrastive learning in the data pre-selection step for our detection model and multi-scale Mean Teacher training paradigm in 3D semantic segmentation to achieve better performance compared with the state of the art. Our extensive experiments have shown that our method achieves competitive performance and is able to outperform by up to 16% on object detection and 7.8% on semantic segmentation. Additionally, our automated metrology package shows a mean error of less than 2 $\mathsf{\mu }$m for key features such as Bond Line Thickness and pad misalignment. Full article

Narrow linewidth external cavity semiconductor lasers (NLECSLs) have many important applications, such as spectroscopy, metrology, biomedicine, holography, space laser communication, laser lidar and coherent detection, etc. Due to their high coherence, low phase-frequency noise, high monochromaticity and wide wavelength tuning potential, NLECSLs have attracted much attention for their merits. In this paper, three main device structures for achieving NLECSLs are reviewed and compared in detail, such as free space bulk diffraction grating external cavity structure, waveguide external cavity structure and confocal Fabry–Perot cavity structure of NLECSLs. The Littrow structure and Littman structure of NLECSLs are introduced from the free space bulk diffraction grating external cavity structure of NLECSLs. The fiber Bragg grating external cavity structure and silicon based waveguide external cavity structure of NLECSLs are introduced from the waveguide external cavity structure of NLECSLs. The results show that the confocal Fabry–Perot cavity structure of NLECSLs is a potential way to realize a lower than tens Hz narrow linewidth laser output. Full article

It is crucial to develop novel metrology techniques in the semiconductor fabrication process to accurately measure a film’s thickness in a few nanometers, as well as the material profile of the film. Highly uniform trichlorosilane (1H,1H,2H,2H-perfluorodecyltrichlorosilane, FDTS) derived SAM film patterns were fabricated by several conventional semiconductor fabrication methods combined, including photolithography, SAM vapor deposition, and the lift-off technique. Substantial information can be collected for FDTS SAM film patterns when Auger electron spectroscopy (AES) and X-ray photoelectron spectroscopy (XPS) techniques are incorporated to investigate this material. Precise two-dimensional (2D) FDTS SAM film patterns were reconstructed through mapping analysis of corresponding elements and chemical state peaks by AES and XPS. Additionally, three-dimensional (3D) FDTS SAM film patterns were also reconstructed layer by layer through gas cluster ion beam (GCIB) etching and XPS analysis. These characterization results demonstrate that FDTS SAM film patterns based on the vapor deposition method are highly uniform because the vacuum and precise gas-delivery system exclude ambient environmental interference efficiently and ensure reaction process repeatability. AES and XPS techniques could be used for metrology applications in the semiconductor process with high-quality SAM microstructures and nanostructures. Full article