Search Results (323)

Generator-side transient overvoltage may occur in DC 600 V AC–DC–AC railway power supply systems because switching-induced common-mode voltage generated by the front-end rectifier can propagate in reverse through cable distributed parameters, grounding impedance, and generator parasitic capacitance. Although AZSVPWM has been widely studied as a common-mode voltage reduction technique, its application to the suppression of generator-side reverse transient overvoltage in railway DC 600 V power supply systems has not been sufficiently investigated. In this paper, AZSVPWM is applied to the front-end active rectifier as a source-side suppression strategy. A high-frequency electromagnetic transient model is developed by considering the generator equivalent impedance, cable distributed parameters, grounding path, and generator winding-to-ground parasitic capacitance. The model is validated by comparing simulated and measured generator terminal voltages under AZSVPWM operation. Based on this model, the common-mode voltage excitation mechanism, reverse propagation path, and overvoltage suppression effect of AZSVPWM are analyzed. The results show that, compared with conventional SVPWM under identical active-rectifier conditions, AZSVPWM reduces the representative peak transient voltage at the generator terminals from 751.37 V to 557.71 V under the 8 m cable condition, corresponding to a reduction of approximately 25.77%. In addition, AZSVPWM-based active rectification improves the low-frequency voltage quality compared with conventional thyristor rectification, and the THD is estimated to decrease from approximately 14.8% to 0.8% based on the FFT spectrum. Parametric analysis further shows that AZSVPWM maintains stable suppression performance for cable lengths of 2–15 m and generator parasitic capacitances of 5–20 nF, with the maximum peak-voltage deviation caused by parasitic capacitance variation being approximately 1.15%. These results indicate that AZSVPWM provides a practical and robust source-side suppression strategy for generator-side transient overvoltage in railway DC 600 V power supply systems. Full article

The main purpose of this study is to overcome the difficulty of maintaining high-quality zero-voltage switching (ZVS) in resonant converters over wide operating ranges. Conservative designs ensuring light-load ZVS inevitably generate excessive reactive current, causing severe circulating losses and body diode conduction under heavy loads. To resolve this intrinsic trade-off, this paper proposes an active closed-loop optimal ZVS control strategy utilizing a DC-biased variable resonant inductor. The core mechanism actively shifts the tank impedance to dynamically reshape the primary current. By integrating the primary current during each dead time, the real-time integrated charge is actively regulated to track an optimal reference limit defined by the switch parasitic capacitance and dc-bus voltage. Consequently, the variable inductor continuously regulates the tank current toward the optimal ZVS boundary, ensuring the parasitic capacitance is completely discharged just before the turn-on instant. Validations via simulation and a 192 W hardware prototype confirm the method’s efficacy. The strategy completely eliminates light-load hard switching and significantly suppresses heavy-load body diode conduction without compromising output voltage regulation. Compared to conventional active schemes, this approach achieves full-range optimal ZVS without requiring additional high-frequency switching devices, establishing a highly efficient shift from passive parameter design to active boundary tracking. Full article

Accurate estimation of insulation resistance, denoted as R_iso, in high-voltage direct current energy storage systems plays a pivotal role in leakage protection and thermal runaway suppression. Conventional physical measurement techniques are inherently susceptible to distortions under dynamic operating conditions due to interference from parasitic capacitance. Meanwhile, emerging data-driven approaches are often bottlenecked by cross-domain distribution shifts and the scarcity of annotated full-lifecycle data. This study proposes a hybrid framework that integrates transfer learning and residual correction within a CNN-LSTM architecture, referred to as TL-CNN-LSTM + Corr. Utilizing seven-dimensional operational features as inputs, the framework employs a one-dimensional convolutional neural network to extract high-frequency transient response patterns. Simultaneously, a long short-term memory network models the long-term, non-stationary temporal evolution of insulation degradation. To circumvent systemic biases across varying scenarios, a three-stage domain adaptation strategy consisting of pre-training, freezing, and fine-tuning was developed, which is complemented by a lightweight linear residual compensator designed to rectify amplitude drifts during abrupt operational transitions. Independent evaluations using 500 sets of real-world operational data demonstrate that the proposed model achieves high-precision predictions, yielding a root mean square error of 40.595, a mean absolute error of 32.919, and an R² value of 0.941. Furthermore, the model exhibits remarkable robustness against sensor noise and data loss. By ensuring cross-domain predictive consistency with minimal computational overhead, this framework provides a highly reliable and deployable solution for online insulation state monitoring in edge-side battery management systems. Full article

An optimal CMOS up-conversion mixer is designed using a novel combination of genetic algorithms and particle swarm optimization (Com_GAPSO) and improved-Kolmogorov–Arnold networks (Im_GKAN) for 5G communication. The proposed Im_GKAN, trained with Com_GAPSO, enhances optimization through social interactions and private cognition through social interactions. The proposed hybrid approach enables accurate parameter determination due to the effective modeling and compensation of nonlinearities in the up-conversion mixer. The proposed optimized mixer incorporates an enhanced linearity boosting technique (LBT) along with a tunable capacitive feedback common-source (TCF-CS) structure. This combination effectively suppresses third-order nonlinear distortion while compensating for parasitic capacitances to improve gain performance and enhance circuit stability. The proposed design achieves a peak conversion gain (CG) of approximately 4.2 dB near 24 GHz. In terms of isolation characteristics, the LO-IF isolation reaches about −44 dB. Additionally, the RF-IF isolation is around −30 dB, ensuring minimal undesired coupling between the input and output paths, while the LO-RF isolation is maintained near −39 dB. The optimized mixer exhibits an output 1 dB compression point (OP₁dB) of 5.1 dBm and an input 1 dB compression point (IP₁dB) of −1.1 dBm. The RF port shows a return loss of approximately −24 dB near 24 GHz. The LO port exhibits a return loss in the range of −3 to −5 dB, with improved matching observed over the operating band. Meanwhile, the IF port demonstrates strong matching at lower frequencies, with return loss values dropping below −20 dB. Furthermore, the measured optimized design achieves a minimum noise figure (NF) of approximately 3.8 dB at 24 GHz. Full article

Wireless power transfer (WPT) systems for electric vehicles (EVs) are increasingly being studied in the MHz range to increase power density and reduce the size of passive components. However, operation at higher frequencies significantly changes electromagnetic interference (EMI) behaavior. Fast switching in SiC- and GaN-based inverters, high-Q resonant operation, and frequency-dependent parasitic capacitances create conductive, capacitive, and magnetic interference mechanisms that are less significant in conventional kHz-range systems. Although many existing studies focus on power-transfer efficiency and converter optimization, EMI mechanisms in MHz-range EV WPT systems remain insufficiently systematized from a system-level electromagnetic perspective. This paper presents a state-of-the-art review of EMI generation mechanisms and system-level effects in high-frequency WPT systems for electric vehicles. The review considers the main interference sources and coupling paths, including switching-induced common-mode currents, resonant amplification of current and voltage stress, capacitive coupling between the coupler and nearby conductive structures, and magnetic-field redistribution caused by coil misalignment. Special attention is given to the transition from lumped-element assumptions to more distributed electromagnetic behavior at higher frequencies. The review also discusses the possible impact of these mechanisms on vehicle electronic subsystems and highlights the need for frequency-aware electromagnetic design, integrated modeling, and more rigorous EMC assessment for reliable MHz-range wireless EV charging systems. Full article

This paper presents a 0.5–67 GHz static 1:2 frequency divider implemented in a commercial 0.7 μm InGaAs/InP DHBT technology. Instead of migrating to a more advanced process or introducing complex speed-enhancement circuits, a selective transistor scaling strategy is adopted, where only the critical switching and latching differential pairs in the CML master–slave core are implemented using 0.5 μm high-f_T DHBTs, while the input/output buffers, bias circuits, and non-critical devices remain based on standard 0.7 μm transistors. This approach reduces the parasitic capacitances at speed-limiting nodes and improves the high-frequency operation of the divider with minimal circuit and process overhead. The fabricated divider achieves a continuous operating bandwidth from 0.5 to 67 GHz, a full-band input power range from −5 to +10 dBm, a single-ended output power higher than −10 dBm, and an SSB phase noise of −141.03 dBc/Hz at 100 kHz offset with a 30 GHz input. These results demonstrate that selective core transistor scaling provides an effective and practical route for upgrading wideband static frequency dividers on mature InP DHBT platforms. Full article

A high quality factor, denoted as the Q-factor, is crucial for micromachined disk resonator gyroscopes, commonly referred to as DRGs, to suppress thermomechanical noise and improve bias stability. However, the coupled energy dissipation mechanisms under low-pressure conditions impose significant limitations on further Q-factor enhancement. This paper establishes a rigorous multiphysics damping analysis framework for DRGs and quantitatively investigates the contributions of air damping, thermoelastic damping, and anchor loss. A free-molecular squeeze-film damping model is derived based on kinetic gas theory and molecular energy transfer mechanisms, avoiding the continuous fluid assumption of the classical Reynolds equation, which fails in low-pressure regimes. Due to the highly symmetric ring structure and central anchor design, finite element method simulations reveal an extremely high anchor-loss-limited quality factor, Q_anchor, of approximately 1.85 × 10¹², indicating negligible anchor-induced dissipation. Under an operating pressure of 0.1 Pa, air damping is validated as the absolute dominant energy dissipation mechanism with a gas quality factor, Q_air, of approximately 1.105 × 10⁵, which is significantly lower than the thermoelastic damping quality factor, Q_TED, evaluated at 8.98 × 10⁵. To break the classical trade-off between squeeze-film damping suppression and capacitive drive efficiency, a decoupled gap optimization strategy is proposed. By maintaining the drive electrode gap, gap_e, at 7.2 µm while increasing only the parasitic ring-to-suspended-mass gap, gap_m, to 12 µm, the squeeze-film-damping-limited Q-factor is improved by approximately 25% to 1.381 × 10⁵ without degrading electromechanical coupling efficiency. In addition, the optimal anchor radius is determined to be approximately 160 µm. The proposed framework provides practical design guidance for high-Q DRGs and other MEMS resonant inertial sensors. Full article

This paper presents the design and implementation of an X-band voltage-controlled oscillator (VCO) fabricated in a standard 180-nm CMOS process. To sustain stable oscillation under a constrained power budget, a gm-boosted topology is employed, integrating vertically stacked cross-coupled transistors with a center-tapped transformer to enhance the equivalent negative conductance. The boosting is achieved through two complementary mechanisms: the center-tapped transformer performs an impedance transformation that repurposes the layout parasitic capacitances into transconductance-enhancing elements, while the stacked cross-coupled pair reuses the DC current and suppresses the source-degeneration of a conventional pair, jointly sustaining a robust start-up margin at a low 0.75 V supply. On-wafer measurement results demonstrate a frequency tuning range from 8.78 GHz to 9.13 GHz as the control voltage is swept from 0 V to 1.8 V, with an average VCO gain K_VCO of 447.5 MHz/V. Under a total DC power consumption of 6.9 mW, the oscillator delivers an output power of 4.54 dBm and exhibits a measured phase noise of −103 dBc/Hz at a 1-MHz offset. Full article

The increasing computational demands of deep neural network inference drive the need for energy-efficient hardware accelerators that minimize data movement between memory and processing units. Compute-in-memory (CIM) architectures address this bottleneck by embedding computation directly within memory arrays, reducing the overhead of repeated weight transfers in conventional von Neumann systems. Conventional 6T SRAM-based digital CIM bitcells incur significant transistor overhead as arrays scale, motivating exploration of reduced-transistor bitcell alternatives. We propose a compact 4T+2T SRAM-based digital CIM bitcell implemented in 45 nm CMOS, combining a 4T SRAM storage cell with a 2T multiplier for bitwise multiply-and-accumulate (MAC) operations. The proposed design reduces transistor count from 8 to 6 compared to the 6T+2T reference, lowering parasitic capacitance and hardware overhead without compromising memory or computation functionality. Transient simulations confirm correct write, read, and CIM operations. The bitcell achieves a read delay of 26.91 ps, read power of 1.351 nW, and read energy of 0.005403 fJ—reductions of 98.7%, 86.5%, and 73.1% over the 6T+2T reference, respectively. For CIM operation, bitwise multiplication power decreases from 1.772 µW to 0.8014 µW and energy from 10.63 fJ to 4.808 fJ, representing a 54.8% reduction in both metrics, with only a marginal CIM delay increase of 3.13 ps. Monte Carlo analysis across 100 samples confirms robust write behavior under process variation, with write delay ranging from 55.02 to 69.59 ps and write energy from 0.05870 to 0.06557 fJ. Static noise margin analysis yields an SNM of 83.7 mV under nominal conditions, confirming stable data retention. These results demonstrate that the proposed 4T+2T bitcell offers strong transistor efficiency, energy savings, and computational correctness, making it a promising candidate for area-efficient digital CIM architectures targeting edge AI inference. Full article

Nowadays, numerical simulation methods are advanced and widely used in industry, enabling the modeling of complex systems from printed circuit boards (PCBs) to full power converters. Among many isolated topologies, the phase-shift full-bridge (PSFB) topology is a well-established solution for isolated DC–DC conversion in electric vehicles. Therefore, this paper proposes a broadband electromagnetic compatibility (EMC) modeling methodology for a custom-designed 1 kW gallium nitride (GaN)-based PSFB converter intended for an electric vehicle (EV) DC powertrain. Moreover, the approach combines full-wave electromagnetic simulation with circuit-level simulation, including parasitic effects from PCB layout, power harnesses, and discrete components. Thus, the virtual prototype is assessed within a complete virtual test bench compliant with the standard Comité International Spécial des Perturbations Radioélectriques (CISPR) 25 over the 150 kHz–108 MHz range to capture common-mode (CM) and differential-mode (DM) conducted electromagnetic interference (EMI). Results show that the converter achieves efficiencies of 97.26% in standalone mode and 97.03% when integrated into the full DC powertrain. However, the conducted EMI assessment reveals that both CM and DM emissions exceed CISPR 25 Class 2 limits across the entire spectrum, with excess levels reaching up to 72 dBµV. Therefore, power harnesses significantly increase EMI levels at low frequencies due to the distributed inductance and stray capacitance. Finally, this study demonstrates the value of virtual prototyping for simulation-based EMI prediction in early-stage power converter design. Full article

A quasi-continuous-wave (QCW) laser module based on a half-bridge structure is proposed for the low-voltage silicon photonics application, which forms a continuous-wave (CW) laser output when it equally distributes the heat dissipation into all lasers. Such a QCW laser module is modulated into a CW laser source for the chip-to-chip or board-to-board communication. The source current is alternatively diverted to the high-side and the low-side lasers by turning the corresponding gallium nitride high-electron-mobility transistor (GaN HEMT) on and off. The current redirection modulates multiple QCW laser outputs into a CW laser output; however, an undesirable laser downtime is produced during the transition time of the current redirection. Although for the 10 Gbps data rate transmission, a short laser downtime period may be scheduled for the time to perform either the laser steering task of the free-space optics (FSO) operation or the data pause for the fan-out delay, which is still preferred to be minimized for higher data rate transmission. The power efficiency and the laser downtime are functions of the parameters of the laser diodes, switch parasitic capacitances, input voltage, and the inductor. According to the mathematical derivation of the circuit response, the circuit design rules and the switching control strategy are provided to achieve high efficiency and low laser downtime. In the experiment, we implemented a laser module to achieve an FSO specification with a laser downtime of less than 3 ns, total harmonic distortion (THD) less than 10%, power efficiency greater than 60% and laser power higher than 1 W. Full article

This paper investigates the accuracy of conventional inductive current transformers (iCTs) and Rogowski coils (RCs) in measuring distorted currents, evaluating compliance with the WB0 (up to the 13th harmonic) and WB1 (up to the 60th harmonic) accuracy classes according to the IEC 61869-1 standard. A custom reference iCT, calibrated via the ampere-turns method to achieve a superior baseline accuracy (0.02%), served as the primary benchmark. A zero-flux electronic transducer was utilized strictly to verify this reference. Despite inherent core nonlinearity, tested conventional iCTs with reduced to minimum secondary burdens successfully met the class 0.5-WB1 requirements. In the case of tested Rogowski coils, the study reveals that their wideband performance depends on physical design of the particular type. High-sensitivity coils suffer from increased parasitic capacitance and self-inductance, causing significant additional phase shift at higher frequencies, whereas low-sensitivity, small-diameter coils offer superior linearity. Overall, the tested RCs generally ensured compliance with the 0.5-WB1 class across the evaluated frequency range, with certain units successfully achieving the more restrictive 0.2-WB1 class. Ultimately, conventional iCTs remain a highly reliable solution for metering purposes in low-voltage networks, while properly selected Rogowski coils provide a valuable alternative for power quality analysis and harmonic distortion measurements. Full article

This work presents the realization of a compact and embedded impedance-based sensor system for the characterization of lithium-ion batteries by means of electrical impedance spectroscopy (EIS). The analog magnitude-ratio and phase-difference detection (MRPDD) method is implemented and extended through a generalized formulation that models the shunt element as a frequency-dependent impedance and compensates the parasitic contributions of the printed circuit board. This reformulation corrects magnitude and phase errors introduced by the measurement hardware without increasing the overall complexity. The prototype comprises two main functional blocks: current-mode excitation and voltage-mode measurement. The excitation stage uses an operational transconductance amplifier and a power MOSFET to generate a voltage-controlled current source, whereas the sinusoidal voltage signal is generated by means of a direct digital synthesizer. The measurement chain relies on differential acquisition using instrumentation amplifiers and analog magnitude/phase detection based on the AD8302 vector detector under microcontroller control. The proposed method has been first validated by simulations using both a linear RC equivalent model and an extended Randles-type battery-equivalent model, and then experimentally characterized using a linear RC equivalent model of the device under test. Measurements show that the generalized formulation recovers the ideal impedance response in the presence of parasitic effects, both in the shunt device and in the printed circuit board. In the experimental validation with the RC model, a magnitude error of 1.65% is obtained at 1 kHz, which is adopted as the upper frequency limit for battery characterization, even though operation up to 10 kHz is possible. Phase measurements revealed that the input capacitive coupling of the vector detector, conceived for operation in the RF range, requires an adaptation for appropriate operation in the intended frequency range. The prototype has been also applied to the characterization of a commercial lithium-ion 18650 cell, enabling the measurement of battery impedance and the analysis of its dependence on the state-of-charge and on the discharge current. Full article

Capacitance-based methods are widely used to evaluate lubricant film thickness in machine elements where direct optical access is unavailable, especially in rolling bearings and other multi-contact components. This review examines the physical basis, historical development, and modern methodological routes of capacitance-based film thickness determination, with emphasis on four coupled interpretive layers: film geometry, dielectric response, electrical topology, and parasitic/background effects. The literature shows that the field has evolved from simple dielectric-gap conversion toward more strongly constrained interpretation using elastohydrodynamic lubrication priors, dielectric identification, network-aware reduction, and frequency-domain information, particularly under grease lubrication, starvation, and transient conditions. Across these studies, capacitance-derived film thickness is not a methodologically uniform quantity but an inferred result whose meaning depends on what is prescribed, what is estimated, and what ambiguity remains unresolved. The main unresolved challenges are geometry–dielectric non-uniqueness, parasitic and topology uncertainty, and limited validation under realistic operating conditions. Overall, capacitance-based film thickness determination in practical machine elements is best understood as a constrained electromechanical inference problem, and future progress will depend on stronger identifiability, more informative broadband measurements, and clearer reporting of assumptions, inference targets, and validation basis. Full article

This paper presents a rule-based LVS-driven methodology for parasitic RC extraction from CMOS layouts for post-layout SPICE simulation. The proposed approach operates directly within foundry-qualified rule environments, ensuring consistency with Process Design Kits (PDKs) and enabling seamless integration with existing design and verification flows without requiring field-solver execution during the production extraction flow. The methodology provides a generalized framework for deriving electrical parameters from layout geometries and is applicable to interconnects, contacts, vias, and gate structures in multilayer CMOS technologies. By decomposing conductive regions into directional components and applying geometric and Boolean operations, the method captures the impact of layout topology and process-dependent features on circuit-level behavior. In addition, a model-order reduction technique based on π-equivalent representations is introduced to simplify the resulting networks while preserving timing accuracy. This enables the scalable simulation of complex layouts with reduced computational overhead. The proposed framework supports layout optimization, variability-aware design, and process-technology co-design, particularly for mature and advanced planar nodes. The methodology is evaluated using register-file layout test cases and post-layout SPICE simulations. The results show that the proposed rule-based extraction and RC-merging flow preserve timing behavior while reducing netlist complexity. Full article