Search Results (150)

In the pursuit of advanced non-volatile memory technologies, ferroelectric memristors have attracted great attention. However, traditional perovskite ferroelectric materials are hampered by environmental pollution, limited applicability, and the complexity and high cost of conventional vacuum deposition methods. This has spurred the exploration of alternative materials and fabrication strategies. Herein, a flexible Pt/Zr: HfO₂ (HZO)/graphene oxide (GO)/mica memristor is successfully fabricated using the total solution-processed method. The interfacial oxygen competition mechanism between the HZO layer and the GO bottom electrode facilitates the formation of the HZO ferroelectric phase. The as-prepared device exhibits a switching ratio of approximately 150 and can maintain eight distinct resistance levels, and it can also effectively simulate neural responses. By integrating the ferroelectric polarization principle and the piezoelectric effect of HZO, along with the influence of GO, the performance variations of the as-prepared device under mechanical and thermal influences are further explored. Notably, Morse code recognition is achieved by utilizing the device’s pressure properties and setting specific press rules. The as-prepared device can accurately convert and store information, opening new avenues for non-volatile memory applications in silent communication and promoting the development of wearable electronics. Full article

As an emerging type of non-volatile memory, magneto-resistive random access memory (MRAM) stands out for its exceptional reliability and rapid read–write speeds, thereby garnering considerable attention within the industry. The memory cell architecture of MRAM is centered around the magnetic tunnel junction (MTJ), which, however, is prone to interference from external magnetic fields—a limitation that restricts its application in demanding environments. To address this challenge, we propose an innovative open magnetic shielding structure. This design demonstrates remarkable shielding efficacy against both in-plane and perpendicular magnetic fields, effectively catering to the magnetic shielding demands of both spin-transfer torque (STT) and spin–orbit torque (SOT) MRAM. Finite element magnetic simulations reveal that when subjected to an in-plane magnetic field of 40 mT, the magnetic field intensity at the chip level is reduced to nearly 1‰ of its original value. Similarly, under a perpendicular magnetic field of 40 mT, the magnetic field at the chip is reduced to 2‰ of its initial strength. Such reductions significantly enhance the anti-magnetic capabilities of MRAM. Moreover, the magnetic shielding performance remains unaffected by the height of the packaging structure, ensuring compatibility with various chip stack packaging requirements across different layers. The research presented in this paper holds immense significance for the realization of highly reliable magnetic shielding packaging solutions for MRAM. Full article

As the CMOS technology approaches its physical and economic limits, further advancement of Moore’s Law for enhanced computing performance can no longer rely solely on smaller transistors and higher integration density. Instead, the computing landscape is poised for a fundamental transformation that transcends hardware scaling to embrace innovations in architecture, software, application-specific algorithms, and cross-disciplinary integration. Among the most promising enablers of this transition is non-volatile memory (NVM), which provides new technological pathways for restructuring the future of computing systems. Recent advancements in non-volatile memory (NVM) technologies, such as flash memory, Resistive Random-Access Memory (RRAM), and magneto-resistive RAM (MRAM), have significantly narrowed longstanding performance gaps while introducing transformative capabilities, including instant-on functionality, ultra-low standby power, and persistent data retention. These characteristics pave the way for developing more energy-efficient computing systems, heterogeneous memory hierarchies, and novel computational paradigms, such as in-memory and neuromorphic computing. Beyond isolated hardware improvements, integrating NVM at both the architectural and algorithmic levels would foster the emergence of intelligent computing platforms that transcend the limitations of traditional von Neumann architectures and device scaling. Driven by these advances, next-generation computing platforms powered by NVM are expected to deliver substantial gains in computational performance, energy efficiency, and scalability of the emerging data-centric architectures. These improvements align with the broader vision of both “More Moore” and “More than Moore”—extending beyond MOS device miniaturization to encompass architectural and functional innovation that redefines how performance is achieved at the end of CMOS device downsizing. Full article

Understanding the resistive switching (RS) mechanisms in memristive devices is crucial for developing non-volatile memory technologies. Here, we investigate the memristor effect in hydrothermally grown Au-nanoseeded CuO films. Based on I-V measurements, conductive-AFM, S/TEM, and EDS analyses, we examine the changes within the switching layer associated with RS. Our results reveal a filamentary mechanism of RS. Notably, EDS mapping shows directional Au redistribution between the bottom nanoseeds and the top electrode, while Cu and O remain uniformly distributed. These findings support an electrochemical metallization (ECM)-like filamentary mechanism driven by Au species migration. The use of Au-nanoseeds, required by the solution-based growth method, critically affects filament formation and RS behavior. Our results emphasize the importance of microstructure and electrode–oxide interfaces in determining the switching mechanism in oxide-based memristors. Full article

Integrating two-dimensional transition-metal dichalcogenides with graphene is attractive for low-power memory and neuromorphic hardware, yet sequential wet transfer leaves polymer residues and high contact resistance. We demonstrate a complementary metal–oxide–semiconductor (CMOS)-compatible, transfer-free route in which an atomically thin amorphous MoS₂ precursor is RF-sputtered directly onto chemical vapor-deposited few-layer graphene and crystallized by confined-space sulfurization at 800 °C. Grazing-incidence X-ray reflectivity, Raman spectroscopy, and X-ray photoelectron spectroscopy confirm the formation of residue-free, three-to-four-layer 2H-MoS₂ (roughness: 0.8–0.9 nm) over 1.5 cm × 2 cm coupons. Lateral MoS₂/graphene devices exhibit reproducible non-volatile resistive switching with a set transition (SET) near +6 V and an analogue ON/OFF ≈2.1, attributable to vacancy-induced Schottky-barrier modulation. The single-furnace magnetron sputtering + sulfurization sequence avoids toxic H₂S, polymer transfer steps, and high-resistance contacts, offering a cost-effective pathway toward wafer-scale 2D memristors compatible with back-end CMOS temperatures. Full article

Computing-in-memory (CIM) with emerging non-volatile resistive memory devices has demonstrated remarkable performance in data-intensive applications, such as neural networks and machine learning. A crosspoint memory array enables naturally parallel computation of matrix–vector multiplication (MVM) in the analog domain, offering significant advantages in terms of speed, energy efficiency, and computational density. However, the intrinsic device non-ideality residing in analog conductance state distorts the MVM precision and limits the application to high-precision scenarios, e.g., scientific computing. Yet, a theoretical framework for guiding reliable computing-in-memory designs has been lacking. In this work, we develop an analytical model describing the constraints on bit precision and row parallelism for reliable MVM operations. By leveraging the concept of capacity from information theory, the impact of non-ideality on computational precision is quantitively analyzed. This work offers a theoretical guidance for optimizing the quantized margins, providing valuable insights for future research and practical implementation of reliable CIM. Full article

By combining density functional theory with the non-equilibrium Green’s function method, we conducted a first-principles investigation of spin-dependent transport properties in a molecular device featuring a dynamic covalent chemical bridge connected to zigzag graphene nanoribbon electrodes. The effects of spin-filtering and spin-rectifying on the I–V characteristics are revealed and explained for the proposed molecular device. Interestingly, our results demonstrate that all three devices exhibit significant single-spin-filtering behavior in parallel (P) magnetization and dual-spin-filtering effects in antiparallel (AP) configurations, achieving nearly 100% spin-filtering efficiency. At the same time, from the I–V curves, we find that there is a weak negative differential resistance effect. Moreover, a high rectifying ratio is found for spin-up electron transport in AP magnetization, which is explained by the transmission spectrum and local density of state. The fundamental mechanisms governing these phenomena have been elucidated through a systematic analysis of spin-resolved transmission spectra and spin-polarized electron transport pathways. These results extend the design principles of spin-controlled molecular electronics beyond graphene-based systems, offering a universal strategy for manipulating spin-polarized currents through dynamic covalent interfaces. The nearly ideal spin-filtering efficiency and tunable rectification suggest potential applications in energy-efficient spintronic logic gates and non-volatile memory devices, while the methodology provides a framework for optimizing spin-dependent transport in hybrid organic–inorganic nanoarchitectures. Our findings suggest that such systems are promising candidates for future spintronic applications. Full article

In this manuscript, strontium barium titanate (BST) ferroelectric memory film materials for applications in the feasibility of applying to non-volatile RAM devices were obtained and compared. Solutions were synthesized with a proportional ratio and through the deposition of BST films on titanium nitride/silicon substrates using the sol–gel method, using rapid thermal annealing for defect repair and re-crystallization processing. The crystallization structure and surface morphology of annealed and as-deposited BST films were obtained by XPS, XRD, and SEM measurements. Additionally, the ferroelectric and resistive switching properties for the memory window, the maximum capacitance, and the leakage current were examined for Al/BST/TiN and Cu/BST/TiN structure memory devices. In addition, the first-order reaction equation of the decay reaction behavior for the BST film RRAM devices in the reset state revealed that $r=0.19{[O^{2-}]}^1$. Finally, the Cu/BST/TiN and Al/BST/TiN structures of the ferroelectric BST films RRAM devices exhibited good memory window properties, bipolar switching properties, and non-volatile properties for applications in non-volatile memory devices. Full article

In this study, the bipolar resistance switching behavior and electrical conduction transport properties of a neodymium oxide film’s resistive random access memory (RRAM) devices for using different top electrode materials were observed and discussed. Different related electrical properties and transport mechanisms are important factors in applications in a film’s RRAM devices. For aluminum top electrode materials, the electrical conduction mechanism of the neodymium oxide film’s RRAM devices all exhibited hopping conduction behavior, with 1 mA and 10 mA compliance currents in the set state for low/high voltages applied. For TiN and ITO (Indium tin oxide) top electrode materials, the conduction mechanisms all exhibited ohmic conduction for the low voltage applied, and all exhibited hopping conduction behavior for the high voltage applied. In addition, the electrical field strength simulation resulted in an increase in the reset voltage, indicating that oxygen ions have diffused into the vicinity of the ITO electrode during the set operation. This was particularly the case in the three physical models proposed, and based on the relationship between different ITO electrode thicknesses and the oxygen ion concentration distribution effect of the neodymium oxide film’s RRAM devices, they were investigated and discussed. To prove the oxygen concentration distribution expands over the area of the ITO electrode, the simulation software was used to analyze and simulate the distribution of the electric field for the Poisson equation. Finally, the neodymium oxide film’s RRAM devices for using different top electrode materials all exhibited high memory window properties, bipolar resistance switching characteristics, and non-volatile properties for incorporation into next-generation non-volatile memory device applications in this study. Full article

Memristors are promising candidates for next-generation non-volatile memory devices, offering low power consumption and high-speed switching capabilities. However, conventional metal oxide-based memristors are constrained by fabrication complexity and high costs, limiting their commercial viability. Organic–inorganic hybrid perovskites (OIHPs), known for their facile solution processability and unique ionic–electronic conductivity, provide an attractive alternative. This study presents a conjugated polyelectrolyte (CPE), PhNa-1T, as an interlayer for OIHP memristors to enhance the high-resistance state (HRS) performance. A post-treatment process using n-octylammonium bromide (OABr) was further applied to optimize the interlayer properties. Devices treated with PhNa-1T/OABr achieved a significantly improved ON/OFF ratio of 2150, compared to 197 for untreated devices. Systematic characterization revealed that OABr treatment improved film morphology, reduced crystallite strain, and optimized energy level alignment, thereby reinforcing the Schottky barrier and minimizing current leakage. These findings highlight the potential of tailored interlayer engineering to improve OIHP-based memristor performance, offering promising prospects for applications in non-volatile memory technologies. Full article

Among the transition metal oxides, hematite (α-Fe₂O₃) has been widely used in the preparation of memristors because of its excellent physical and chemical properties. In this paper, α-Fe₂O₃ nanowire arrays with a preferred orientation along the [110] direction were prepared by a facile hydrothermal method and annealing treatment on the FTO substrate, and then α-Fe₂O₃ nanowire array-based Au/α-Fe₂O₃/FTO memristors were obtained by plating the Au electrodes on the as-prepared α-Fe₂O₃ nanowire arrays. The as-prepared α-Fe₂O₃ nanowire array-based Au/α-Fe₂O₃/FTO memristors have demonstrated stable nonvolatile bipolar resistive switching behaviors with a high resistive switching ratio of about two orders of magnitude, good resistance retention (up to 10³ s), and ultralow set voltage (V_set = +2.63 V) and reset voltage (V_reset = −2 V). In addition, the space charge-limited conduction (SCLC) mechanism has been proposed to be in the high resistance state, and the formation and destruction of the conductive channels modulated by oxygen vacancies have been suggested to be responsible for the nonvolatile resistive switching behaviors of the Au/α-Fe₂O₃/FTO memristors. Our results show the potential of the Au/α-Fe₂O₃/FTO memristors in nonvolatile memory applications. Full article

Biodegradable electronic devices play a crucial role in addressing the escalating issue of electronic waste accumulation, which poses significant environmental threats. In this study, we explore the utilization of a methanol-based extract of the Elaeodendron buchananii plant blended with a carboxymethyl cellulose biopolymer to produce a biodegradable and environmentally friendly functional material for a resistive switching memory system using silver and tungsten electrodes. Our analyses revealed that these two materials chemically interact to generate a perfect composite with near semiconducting optical bandgap (4.01 eV). The resultant device exhibits O-type memory behavior, with a low ON/OFF ratio, strong endurance (≥${10}^3$ write/erase cycles), and satisfactory (≥${10}^3$) data retention. Furthermore, through a comprehensive transport mechanism analysis, we observed the formation of traps in the composite that significantly improved conduction in the device. In addition, we established that altering the voltage amplitude modifies the concentration of traps, leading to voltage amplitude-driven multiple resistance states. Overall, our findings underscore the potential of functionalizing polymers that can be functionalized by incorporating plant extracts, resulting in biodegradable and nonvolatile memory devices with promising performance metrics. Full article

The development of two-dimensional (2D) materials has gained significant attention due to their unique properties and potential applications in advanced electronics. This study investigates the fabrication and characterization of Fe-doped SnSe semiconductors using an optimized chemical vapor deposition (CVD) method. Fe doping was achieved by dissolving FeCl₃ in deionized water, applying it to SnSe powder, and conducting vacuum drying followed by high-temperature CVD at 820 °C. Structural and morphological properties were characterized using optical microscopy, scanning electron microscopy (SEM), and energy dispersive X-ray spectroscopy (EDX). Results revealed differently shaped flakes, including rectangles, discs and wires, influenced by Fe content. Micro-Raman spectroscopy showed significant vibrational mode shifts, indicating structural changes. X-ray photoelectron spectroscopy (XPS) confirmed the presence of Sn-Se and Fe-Se bonds. Electrical characterization of the memristive devices showed stable switching between high- and low-resistance states, with a threshold voltage of 1.6 V. These findings suggest that Fe-doped SnSe is a promising material for non-volatile memory and neuromorphic computing applications. Full article

Herein we report on a facile sol-gel spin-coating technique to fabricate ZnO thin films that grow preferentially along the (002) plane on FTO substrates. By employing the magnetron sputtering technique to deposit a tungsten (W) top metal electrode onto these ZnO thin films, we successfully realize a W/ZnO/FTO memory device that exhibits self-rectifying and forming-free resistive switching characteristics. Notably, the as-prepared device demonstrates impressive nonvolatile and bipolar resistive switching behavior, with a high resistance ratio (R_HRS/R_LRS) exceeding two orders of magnitude at a reading voltage of 0.1 V. Moreover, it exhibits ultralow set and reset voltages of approximately +0.5 V and −1 V, respectively, along with exceptional durability. In terms of carrier transport properties, the low resistance state of the device is dominated by ohmic conduction, whereas the high resistance state is characterized by trap-controlled space-charge-limited current conduction. This work highlights the potential of the ZnO-based W/ZnO/FTO memory device as a promising candidate for future high-density nonvolatile memory applications. Full article

Research on novel memory storage devices that occupy less physical area and are compatible with CMOS processes, such as resistive RAM, has led to the interesting study of non-volatile compute memories and devices. The advent of these low-compromise non-volatile cells invites the opportunity for fully non-volatile microprocessors that are capable of rapid shutdown and startup. This class of microprocessors would be beneficial to intermittent computing systems applications that wait until an energy-harvesting device has sufficient energy available before they do some useful work due to requiring less energy to power down safely. Prior work has demonstrated the emulation of these non-volatile memories that enable the rapid testing of non-volatile memory systems. In this work, we expand on these ideas by introducing a framework that is capable of emulating fully functional non-volatile microprocessors based on individual non-volatile flip-flops, rather than larger addressable non-volatile memory blocks. Our proposed system enables the conversion and emulation of conventional systems into non-volatile equivalents. The proposed architecture is integrated into the open-source RISC-V microprocessor implementation ‘Potato’ and synthesized on a Xilinx Ultrascale+ XCZU5EV FPGA. The area overhead for the proposed emulator is 22 slice registers and 17 LUTs per emulated non-volatile flip-flop. As a case study, an AES block cipher is executed throughout power-down and power-up sequences. The system is shown to properly emulate the complex overhead operations resulting from sensitive power-down and power-up sequences in power-intermittent systems, providing a vital metric for the non-volatile microprocessor’s fidelity. Full article