Search Results (11)

The time-dependent dielectric breakdown (TDDB) degradation mechanism, governed by the synergistic interaction of multiphysics fields, plays a pivotal role in the performance degradation and eventual failure of semiconductor devices and advanced packaging back-end-of-line (BEOL) structures. This work specifically focuses on the dielectric breakdown mechanism driven by metal ion migration within inter-metal dielectric layers, a primary contributor to TDDB degradation. A SPICE-compatible modeling approach is developed to accurately capture the dynamics of this ion migration-induced degradation. The proposed model is rooted in the fundamental physics of metal ion migration and the evolution of conductive filaments (CFs) within the dielectric layer under operational stress conditions. By precisely characterizing the degradation behavior induced by TDDB, a SPICE-compatible degradation model is developed. This model facilitates accurate predictions of resistance changes across a range of operational conditions and lifetime, encompassing variations in stress voltages, temperatures, and structural parameters. The predictive capability and accuracy of the model are validated by comparing its calculated results with numerical ones, thereby confirming its applicability. Furthermore, building upon the established degradation model, the impact of line-edge roughness (LER) is incorporated through a process variation model based on the power spectral density (PSD) function. This PSD-derived model provides a quantitative characterization of LER-induced fluctuations in critical device dimensions, enabling a more realistic representation of process-related variability. By integrating this stochastic variability model into the degradation framework, the resulting lifetime prediction model effectively captures reliability variations arising from real-world fabrication non-uniformities. Validation against simulation data demonstrates that the inclusion of LER effects significantly improves the accuracy of predicted lifetime curves, yielding closer alignment with observed device behavior under accelerated stress conditions. Full article

Enabling extreme ultraviolet lithography (EUVL) as a viable and efficient sub-10 nm patterning tool requires addressing the critical issue of reducing line edge roughness (LER). Stochastic effects from random and local variability in photon distribution and photochemical reactions have been considered the primary cause of LER. However, polymer chain conformation has recently attracted attention as an additional factor influencing LER, necessitating detailed computational studies with explicit chain representation and photon distribution to overcome the existing approach based on continuum models and random variables. We developed a coarse-grained molecular simulation model for an EUV patterning process to investigate the effect of chain conformation variation and stochastic effects via photon shot noise and acid diffusion on the roughness of the pattern. Our molecular simulation demonstrated that final LER is most sensitive to the variation in photon distributions, while material distributions and acid diffusion rate also impact LER; thus, the intrinsic limit of LER is expected even at extremely suppressed stochastic effects. Furthermore, we proposed and tested a novel approach to improve the roughness by controlling the initial polymer chain orientation. Full article

State of the art three-dimensional atomic force microscopes (3D-AFM) cannot measure three spatial dimensions separately from each other. A 3D-AFM-head with true 3D-probing capabilities is presented in this paper. It detects the so-called 3D-Nanoprobes CD-tip displacement with a differential interferometer and an optical lever. The 3D-Nanoprobe was specifically developed for tactile 3D-probing and is applied for critical dimension (CD) measurements. A calibrated 3D-Nanoprobe shows a selectivity ratio of 50:1 on average for each of the spatial directions x, y, and z. Typical stiffness values are $k_x = 1.722 \pm 0.083$ N/m, $k_y = 1.511 \pm 0.034$ N/m, and $k_z = 1.64 \pm 0.16$ N/m resulting in a quasi-isotropic ratio of the stiffness of 1.1:0.9:1.0 in x:y:z, respectively. The probing repeatability of the developed true 3D-AFM shows a standard deviation of 0.18 nm, 0.31 nm, and 0.83 nm for x, y, and z, respectively. Two CD-line samples type IVPS100-PTB, which were perpendicularly mounted to each other, were used to test the performance of the developed true 3D-AFM: repeatability, long-term stability, pitch, and line edge roughness and linewidth roughness (LER/LWR), showing promising results. Full article

Although extreme ultraviolet lithography (EUVL) has potential to enable 5-nm half-pitch resolution in semiconductor manufacturing, it faces a number of persistent challenges. Line-edge roughness (LER) is one of critical issues that significantly affect critical dimension (CD) and device performance because LER does not scale along with feature size. For LER creation and impacts, better understanding of EUVL process mechanism and LER impacts on fin-field-effect-transistors (FinFETs) performance is important for the development of new resist materials and transistor structure. In this paper, for causes of LER, a modeling of EUVL processes with 5-nm pattern performance was introduced using Monte Carlo method by describing the stochastic fluctuation of exposure due to photon-shot noise and resist blur. LER impacts on FinFET performance were investigated using a compact device method. Electric potential and drain current with fin-width roughness (FWR) based on LER and line-width roughness (LWR) were fluctuated regularly and quantized as performance degradation of FinFETs. Full article

In this study, the impact of the negative capacitance (NC) effect on process-induced variations, such as work function variation (WFV), random dopant fluctuation (RDF), and line edge roughness (LER), was investigated and compared to those of the baseline junctionless nanowire FET (JL-NWFET) in both linear (V_ds = 0.05 V) and saturation (V_ds = 0.5 V) modes. Sentaurus TCAD and MATLAB were used for the simulation of the baseline JL-NWFET and negative capacitance JL-NWFET (NC-JL-NWFET). Owing to the NC effect, the NC-JL-NWFET showed less variation in terms of device performance, such as σ[V_t], σ[SS], σ[I_on/I_off], σ[V_t]/µ[V_t], σ[SS]/µ[SS], and σ[I_on/I_off]/µ[I_on/I_off], and enhanced device performance, which implies that the NC effect can successfully control the variation-induced degradation. Full article

As the physical size of MOSFET has been aggressively scaled-down, the impact of process-induced random variation (RV) should be considered as one of the device design considerations of MOSFET. In this work, an artificial neural network (ANN) model is developed to investigate the effect of line-edge roughness (LER)-induced random variation on the input/output transfer characteristics (e.g., off-state leakage current (Ioff), subthreshold slope (SS), saturation drain current (Id,sat), linear drain current (Id,lin), saturation threshold voltage (Vth,sat), and linear threshold voltage (Vth,lin)) of 5 nm FinFET. Hence, the prediction model was divided into two phases, i.e., “Predict Vth” and “Model Vth”. In the former, LER profiles were only used as training input features, and two threshold voltages (i.e., Vth,sat and Vth,lin) were target variables. In the latter, however, LER profiles and the two threshold voltages were used as training input features. The final prediction was then made by feeding the output of the first model to the input of the second model. The developed models were quantitatively evaluated by the Earth Mover Distance (EMD) between the target variables from the TCAD simulation tool and the predicted variables of the ANN model, and we confirm both the prediction accuracy and time-efficiency of our model. Full article

This work reports a novel, simple, and resist-free chemo-epitaxy process permitting the directed self-assembly (DSA) of lamella polystyrene-block-polymethylmethacrylate (PS-b-PMMA) block copolymers (BCPs) on a 300 mm wafer. 193i lithography is used to manufacture topographical guiding silicon oxide line/space patterns. The critical dimension (CD) of the silicon oxide line obtained can be easily trimmed by means of wet or dry etching: it allows a good control of the CD that permits finely tuning the guideline and the background dimensions. The chemical pattern that permits the DSA of the BCP is formed by a polystyrene (PS) guide and brush layers obtained with the grafting of the neutral layer polystyrene-random-polymethylmethacrylate (PS-r-PMMA). Moreover, data regarding the line edge roughness (LER) and line width roughness (LWR) are discussed with reference to the literature and to the stringent requirements of semiconductor technology. Full article

Block copolymer (BCP) self-assembly is a promising tool for next generation lithography as microphase separated polymer domains in thin films can act as templates for surface nanopatterning with sub-20 nm features. The replicated patterns can, however, only be as precise as their templates. Thus, the investigation of the morphology of polymer domains is of great importance. Commonly used analytical techniques (neutron scattering, scanning force microscopy) either lack spatial information or nanoscale resolution. Using advanced analytical (scanning) transmission electron microscopy ((S)TEM), we provide real space information on polymer domain morphology and interfaces between polystyrene (PS) and polymethylmethacrylate (PMMA) in cylinder- and lamellae-forming BCPs at highest resolution. This allows us to correlate the internal structure of polymer domains with line edge roughnesses, interface widths and domain sizes. STEM is employed for high-resolution imaging, electron energy loss spectroscopy and energy filtered TEM (EFTEM) spectroscopic imaging for material identification and EFTEM thickness mapping for visualisation of material densities at defects. The volume fraction of non-phase separated polymer species can be analysed by EFTEM. These methods give new insights into the morphology of polymer domains the exact knowledge of which will allow to improve pattern quality for nanolithography. Full article

We investigate the effects of Line Edge Roughness (LER) of electrode lines on the uniformity of Resistive Random Access Memory (ReRAM) device areas in cross-point architectures. To this end, a modeling approach is implemented based on the generation of 2D cross-point patterns with predefined and controlled LER and pattern parameters. The aim is to evaluate the significance of LER in the variability of device areas and their performances and to pinpoint the most critical parameters and conditions. It is found that conventional LER parameters may induce >10% area variability depending on pattern dimensions and cross edge/line correlations. Increased edge correlations in lines such as those that appeared in Double Patterning and Directed Self-assembly Lithography techniques lead to reduced area variability. Finally, a theoretical formula is derived to explain the numerical dependencies of the modeling method. Full article

Extreme ultraviolet lithography (EUVL) is a leading-edge technology for pattern miniaturization and the production of advanced electronic devices. One of the current critical challenges for further scaling down the technology is reducing the line-edge roughness (LER) of the final patterns while simultaneously maintaining high resolution and sensitivity. As the target sizes of features and LER become closer to the polymer size, polymer chain conformations and their distribution should be considered to understand the primary sources of LER. Here, we proposed a new approach of EUV photoresist modeling with an explicit description of polymer chains using a coarse-grained model. Our new simulation model demonstrated that interface variation represented by width and fluctuation at the edge of the pattern could be caused by characteristic changes of the resist material during the lithography processes. We determined the effect of polymer chain conformation on LER formation and how it finally contributed to LER formation with various resist material parameters (e.g., Flory–Huggins parameter, molecular weight, protected site ratio, and T_g). Full article

In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in near-threshold region. The impacts of the most severe intrinsic device variations including work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device I_on, I_off, C_g, 32-bit CLA delay and power-delay product (PDP) are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations and HSPICE simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The results indicate that WFV and fin LER have different impacts on device I_on and I_off. Besides, at low operating voltage (<0.3 V), the CLA circuit delay and power-delay product (PDP) of TFET are significantly better than FinFET due to its better I_on and C_g,ave and their smaller variability. However, the leakage power of TFET CLA is larger than FinFET CLA due to the worse I_off variability of TFET devices. Full article