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Keywords = inductor path

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14 pages, 2327 KiB  
Article
A 17–38 GHz Cascode Low-Noise Amplifier in 150-nm GaAs Adopting Simultaneous Noise- and Input-Matched Gain Stage with Shunt-Only Input Matching
by Dongwan Kang, Yeonggeon Lee and Dae-Woong Park
Electronics 2025, 14(14), 2771; https://doi.org/10.3390/electronics14142771 - 10 Jul 2025
Viewed by 235
Abstract
This paper presents a 17–38 GHz wideband low-noise amplifier (LNA) designed in a 150-nm GaAs pHEMT process. The proposed amplifier adopts a cascode topology with an interstage inductor between the common-source (CS) and common-gate (CG) stages, and a series inductor at the source [...] Read more.
This paper presents a 17–38 GHz wideband low-noise amplifier (LNA) designed in a 150-nm GaAs pHEMT process. The proposed amplifier adopts a cascode topology with an interstage inductor between the common-source (CS) and common-gate (CG) stages, and a series inductor at the source node of the CS stage for source degeneration. By incorporating these inductors in the amplification stage, simultaneous noise and input matching is facilitated, while achieving flat gain characteristics over a broad frequency range and ensuring stability. In addition, the amplification stage with inductors achieves input matching using only a shunt component in the DC bias path, without any series matching elements. This approach allows the amplifier to achieve simultaneous noise and input matching (SNIM), ensuring low-noise performance over a wide bandwidth. The simulation results show a flat gain of 20–23 dB and a low noise figure of 1.1–2.1 dB over the 17–38 GHz band. Full article
(This article belongs to the Special Issue Radio Frequency/Microwave Integrated Circuits and Design Automation)
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16 pages, 4237 KiB  
Article
Solid-State Circuit Breaker Topology Design Methodology for Smart DC Distribution Grids with Millisecond-Level Self-Healing Capability
by Baoquan Wei, Haoxiang Xiao, Hong Liu, Dongyu Li, Fangming Deng, Benren Pan and Zewen Li
Energies 2025, 18(14), 3613; https://doi.org/10.3390/en18143613 - 9 Jul 2025
Viewed by 253
Abstract
To address the challenges of prolonged current isolation times and high dependency on varistors in traditional flexible short-circuit fault isolation schemes for DC systems, this paper proposes a rapid fault isolation circuit design based on an adaptive solid-state circuit breaker (SSCB). By introducing [...] Read more.
To address the challenges of prolonged current isolation times and high dependency on varistors in traditional flexible short-circuit fault isolation schemes for DC systems, this paper proposes a rapid fault isolation circuit design based on an adaptive solid-state circuit breaker (SSCB). By introducing an adaptive current-limiting branch topology, the proposed solution reduces the risk of system oscillations induced by current-limiting inductors during normal operation and minimizes steady-state losses in the breaker. Upon fault occurrence, the current-limiting inductor is automatically activated to effectively suppress the transient current rise rate. An energy dissipation circuit (EDC) featuring a resistor as the primary energy absorber and an auxiliary varistor (MOV) for voltage clamping, alongside a snubber circuit, provides an independent path for inductor energy release after faults. This design significantly alleviates the impact of MOV capacity constraints on the fault isolation process compared to traditional schemes where the MOV is the primary energy sink. The proposed topology employs a symmetrical bridge structure compatible with both pole-to-pole and pole-to-ground fault scenarios. Parameter optimization ensures the IGBT voltage withstand capability and energy dissipation efficiency. Simulation and experimental results demonstrate that this scheme achieves fault isolation within 0.1 ms, reduces the maximum fault current-to-rated current ratio to 5.8, and exhibits significantly shorter isolation times compared to conventional approaches. This provides an effective solution for segment switches and tie switches in millisecond-level self-healing systems for both low-voltage (LVDC, e.g., 750 V/1500 V DC) and medium-voltage (MVDC, e.g., 10–35 kV DC) smart DC distribution grids, particularly in applications demanding ultra-fast fault isolation such as data centers, electric vehicle (EV) fast-charging parks, and shipboard power systems. Full article
(This article belongs to the Special Issue AI Solutions for Energy Management: Smart Grids and EV Charging)
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15 pages, 2620 KiB  
Article
Proposal and Validation of a Pyro Conductor Switch-Based FCL for DC Distribution System Protection
by Il Kwon, Yu-Jin Kwak, Jeong-Cheol Lee and Bang-Wook Lee
Energies 2025, 18(13), 3441; https://doi.org/10.3390/en18133441 - 30 Jun 2025
Viewed by 190
Abstract
With the increasing deployment of DC power systems, particularly in DC distribution systems, there is a growing demand for rapid and effective fault current limiting solutions. Conventional fault current limiters (FCLs) often suffer from limitations in terms of response time, size, and operational [...] Read more.
With the increasing deployment of DC power systems, particularly in DC distribution systems, there is a growing demand for rapid and effective fault current limiting solutions. Conventional fault current limiters (FCLs) often suffer from limitations in terms of response time, size, and operational complexity. As a solution to these challenges, this paper proposes a hybrid FCL based on a pyro conductor switch (PCS), which combines passive limiting elements with an active switching mechanism. The proposed PCS FCL consists of a pyro fuse, an IGBT switch, a limiting inductor, and a damping resistor. Upon fault detection, the IGBT switch is first turned off to initiate current transfer into the limiting branch. Subsequently, the pyro fuse operates by explosively severing the embedded conductor using a pyrotechnic charge, thereby providing galvanic isolation and reinforcing current commutation into a high-impedance path. This operational characteristic enables effective fault current suppression without requiring complex control or real-time sensing. A detailed analysis using PSCAD/EMTDC simulations was conducted to evaluate the current limiting characteristics under fault conditions, and a prototype was subsequently developed to validate its performance. The simulation results were verified through experimental testing, indicating the limiter’s ability to reduce peak fault current. Furthermore, the results demonstrated that the degree of current limitation can be effectively designed through the selection of appropriate current limiting parameters. This demonstrates that the proposed PCS-based FCL provides a practical and scalable solution for improving protection in DC power distribution systems. Full article
(This article belongs to the Section F2: Distributed Energy System)
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14 pages, 16692 KiB  
Article
A New Type of DC-DC Buck Converter with Soft Start Function and Reduced Voltage Stress
by Xin Wang, Zishuo Li, Zhen Lin and Fanyi Meng
J. Low Power Electron. Appl. 2025, 15(2), 29; https://doi.org/10.3390/jlpea15020029 - 7 May 2025
Viewed by 766
Abstract
This paper introduces a novel topology called the dual-path step-down converter with auxiliary switches to minimize voltage stress and enable wide voltage conversion ranges. The proposed dual-path step-down converter with auxiliary switches, which uses an inductor and flying capacitor as power conversion components, [...] Read more.
This paper introduces a novel topology called the dual-path step-down converter with auxiliary switches to minimize voltage stress and enable wide voltage conversion ranges. The proposed dual-path step-down converter with auxiliary switches, which uses an inductor and flying capacitor as power conversion components, helps to reduce the voltage stress on the power switches. By adding auxiliary switches, the proposed topology achieves the same voltage conversion ratio range as that of a conventional buck converter. Additionally, soft-start technology is incorporated to reduce the initial inrush current. Furthermore, this paper introduces a system-level design procedure for DC-DC converters. Designed for low-power applications with lithium-ion (Li-ion) batteries, the proposed converter steps down the battery voltage to 1.2 V. With a 380 nH inductor and a 5 µF output capacitor, the converter attains a peak efficiency of 90% under the conditions of 2.7 V to 1.2 V conversion. Full article
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22 pages, 9568 KiB  
Article
A Fixed-Time Zero Sequence Circulating Current Suppression Strategy Based on Extended Kalman Filter
by Xiaopeng Li, Guofeng He, Yuanhao Zhou, Yanfei Dong and Hang Wang
Energies 2025, 18(2), 408; https://doi.org/10.3390/en18020408 - 18 Jan 2025
Viewed by 647
Abstract
The operation of parallel inverters can enhance the reliability of power supply and meet the demand of the grid forming system; however, due to the difference in the Zero Sequence Voltage (ZSV) and the existence of the Zero Sequence Path (ZSP), the problem [...] Read more.
The operation of parallel inverters can enhance the reliability of power supply and meet the demand of the grid forming system; however, due to the difference in the Zero Sequence Voltage (ZSV) and the existence of the Zero Sequence Path (ZSP), the problem of Zero Sequence Circulating Current (ZSCC) inevitably occurs. This paper proposes a fixed-time control strategy based on the Extended Kalman Filter (EKF), used in order to suppress the ZSCC issue in a paralleled inverter system. Firstly, the detailed mathematical model of ZSCC is described, where the inductance perturbations are considered according to the generation mechanism of ZSCC, and a novel ZSCC controller is designed based on the principles of the fixed-time stability theory which can assure the action time of the zero vectors in one switching cycle. Secondly, to reduce the influence of the inductor parameters on the ZSCC control effect, the EKF is used to identify the online inductance parameters of the filter, and the robustness of the algorithm can be improved. Subsequently, based on the Lyapunov stability criterion, it has been proved that the proposed control strategy is fixed-time stable. Finally, the simulation and experiments are employed to demonstrate the effectiveness of the proposed control method. Full article
(This article belongs to the Section F3: Power Electronics)
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15 pages, 7646 KiB  
Article
A Critical Analysis and Comparison of the Effect of Source Inductance on 3- and 4-Lead SuperJunction MOSFETs Turn-Off
by Santi Agatino Rizzo, Nunzio Salerno, Cristina Ventura, Alfio Scuto and Giuseppe Sorrentino
Electronics 2024, 13(20), 4051; https://doi.org/10.3390/electronics13204051 - 15 Oct 2024
Viewed by 1056
Abstract
This paper critically compares the turn-off performance of two package solutions, 3-lead (3L) vs. 4-lead (4L), in SuperJunction MOSFETs. It is commonly assumed that the better performance (lower switching losses) of the 4L MOSFET is obtained thanks to the decoupling of the power [...] Read more.
This paper critically compares the turn-off performance of two package solutions, 3-lead (3L) vs. 4-lead (4L), in SuperJunction MOSFETs. It is commonly assumed that the better performance (lower switching losses) of the 4L MOSFET is obtained thanks to the decoupling of the power and driving loops. On the contrary, in this work, the experimental results, circuit models and Kirchhoff laws show that the turn-off improvement (lower turn-off losses) obtained by adopting the Kelvin source is due to the lower inductance of the driver loop of the 4L MOSFET, instead of the decoupling between the driver and power loops. In detail, an inductor is added to the gate path of the 4L MOSFET to obtain a total inductance in the driver loop equal to the 3L counterpart. The experimental results show that the 4L MOSFET presents the same drain current slew rate under this condition, although the driver and power loops are still decoupled. Full article
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23 pages, 7866 KiB  
Article
Hardware-in-the-Loop Emulation of a SEPIC Multiplier Converter in a Photovoltaic System
by Johnny Posada Contreras and Julio C. Rosas-Caro
Electricity 2024, 5(3), 426-448; https://doi.org/10.3390/electricity5030022 - 5 Jul 2024
Cited by 3 | Viewed by 1642
Abstract
This article presents the development and execution of a Single-Ended Primary-Inductor Converter (SEPIC) multiplier within a Hardware-in-the-Loop (HIL) emulation environment tailored for photovoltaic (PV) applications. Utilizing the advanced capabilities of the dSPACE 1104 platform, this work establishes a dynamic data exchange mechanism between [...] Read more.
This article presents the development and execution of a Single-Ended Primary-Inductor Converter (SEPIC) multiplier within a Hardware-in-the-Loop (HIL) emulation environment tailored for photovoltaic (PV) applications. Utilizing the advanced capabilities of the dSPACE 1104 platform, this work establishes a dynamic data exchange mechanism between a variable voltage power supply and the SEPIC multiplier converter, enhancing the efficiency of solar energy harnessing. The proposed emulation model was crafted to simulate real-world solar energy capture, facilitating the evaluation of control strategies under laboratory conditions. By emulating realistic operational scenarios, this approach significantly accelerates the innovation cycle for PV system technologies, enabling faster validation and refinement of emerging solutions. The SEPIC multiplier converter is a new topology based on the traditional SEPIC with the capability of producing a larger output voltage in a scalable manner. This initiative sets a new benchmark for conducting PV system research, offering a blend of precision and flexibility in testing supervisory strategies, thereby streamlining the path toward technological advancements in solar energy utilization. Full article
(This article belongs to the Topic Advances in Power Science and Technology)
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19 pages, 6482 KiB  
Article
A Three-Port DC-DC Converter with Partial Power Regulation for a Photovoltaic Generator Integrated with Energy Storage
by Donghui Ye and Sergio Martinez
Electronics 2024, 13(12), 2304; https://doi.org/10.3390/electronics13122304 - 12 Jun 2024
Cited by 6 | Viewed by 2092
Abstract
A novel integrated DC-DC converter is proposed for the first stage of two-stage grid connected photovoltaic (PV) systems with energy storage systems. The proposed three-port converter (TPC) consists of a buck–boost converter, interposed between the battery storage system and the DC-AC inverter, in [...] Read more.
A novel integrated DC-DC converter is proposed for the first stage of two-stage grid connected photovoltaic (PV) systems with energy storage systems. The proposed three-port converter (TPC) consists of a buck–boost converter, interposed between the battery storage system and the DC-AC inverter, in series with PV modules. The buck–boost converter in the proposed TPC is utilized for maximum power point tracking by regulating two power switches. The output power of the proposed converter is regulated by controlling the DC-AC converter. During the battery-charging mode, partial power regulation is employed with a direct power flow path (the series-connection of the PV panel, the battery and the output). As resistances in this path are almost negligible, the power conversion efficiency is higher than existing topologies. During battery-discharging mode, the power conversion is processed through a buck–boost converter with only two active power switches and one inductor. With fewer components, higher power conversion efficiency is also achieved. The circuit operation and analysis are presented in detail. To illustrate the simplicity of the converter control, the performance of the converter is tested with a straightforward maximum power point tracking on a PV system with battery cells. Simulation and experimental tests are carried out to demonstrate circuit operation and power conversion efficiency. Full article
(This article belongs to the Special Issue Optimal Integration of Energy Storage and Conversion in Smart Grids)
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15 pages, 5452 KiB  
Article
Suppression of Initial Charging Torque for Electric Drive-Reconfigured On-Board Charger
by Yang Xiao, Kangwei Wang, Zhi Geng, Kai Ni, Mingdi Fan and Yong Yang
World Electr. Veh. J. 2024, 15(5), 207; https://doi.org/10.3390/wevj15050207 - 9 May 2024
Viewed by 2014
Abstract
This paper presents a new electric drive-reconfigured on-board charger and initial electromagnetic torque suppression method. This proposed reconfigured on-board charger does not need many components added to the original electric drive system: only a connector is needed, which is easy to add. Specifically, [...] Read more.
This paper presents a new electric drive-reconfigured on-board charger and initial electromagnetic torque suppression method. This proposed reconfigured on-board charger does not need many components added to the original electric drive system: only a connector is needed, which is easy to add. Specifically, the inverter for propulsion is reconfigured as a buck chopper and a conduction path to match the reconfigured windings. Two of the machine phase windings serve as inductors, while the third phase winding is reutilized as a common-mode inductor. In addition, the initial charging torque is generated at the outset of the charging process, which may cause an instant shock or even rotational movement. In order to prevent vehicle movement, the reason for the charging torque and suppression method were analyzed. Further, predictive control of the model based on mutual inductance analysis was adopted, where the charging torque was directly used as a control object in the cost function. Finally, experimental performances were applied to verify the proposed reconfigured on-board charger under constant current and constant voltage charging. Full article
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33 pages, 2107 KiB  
Article
Geometric Control and Structure-at-Infinity Control for Disturbance Rejection and Fault Compensation Regarding Buck Converter-Based LED Driver
by Jesse Y. Rumbo-Morales, Jair Gómez-Radilla, Gerardo Ortiz-Torres, Felipe D. J. Sorcia-Vázquez, Hector M. Buenabad-Arias, Maria A. López-Osorio, Carlos A. Torres-Cantero, Moises Ramos-Martinez, Mario A. Juárez, Manuela Calixto-Rodriguez, Jorge A. Brizuela-Mendoza and Jesús E. Valdez-Resendiz
Mathematics 2024, 12(9), 1277; https://doi.org/10.3390/math12091277 - 23 Apr 2024
Cited by 4 | Viewed by 1776
Abstract
Currently, various light-emitting diode (LED) lighting systems are being developed because LEDs are one of the most used lighting sources for work environments, buildings, homes, and public roads in terms of some of their applications. Similarly, they have low energy consumption, quick responses, [...] Read more.
Currently, various light-emitting diode (LED) lighting systems are being developed because LEDs are one of the most used lighting sources for work environments, buildings, homes, and public roads in terms of some of their applications. Similarly, they have low energy consumption, quick responses, and excellent optimal performance in their operation. However, these systems still need to precisely regulate lighting, maintain stable voltage and current in the presence of faults and disturbances, and have a wide range of operations in the event of trajectory changes or monitoring tasks regarding the desired voltage and current. This work presents the design and application of two types of robust controllers (structure-at-infinity control and geometric control) applied to an LED driver using a buck converter. The controllers aim to follow the desired trajectories, attenuate disturbances at the power supply input, and compensate for faults in the actuator (MOSFET) to keep the capacitor voltage and inductor current stable. When comparing the results obtained with the two controllers, it was observed that both present excellent performance in the presence of constant disturbances. However, in scenarios in which variable faults and path changes are implemented, the structure-at-infinity control method shows an overimpulse of output voltage and current ranging from 39 to 42 volts and from 0.3 to 0.45 A, with a margin of error of 1%, and it can generate a failure in the LED driver using a buck converter. On the other hand, when using geometric control, the results are satisfactory, achieving attenuating constant disturbances and variable faults, reaching the desired voltage (40 v to 35 v) and current (0.3 to 0.25 A) with a margin of error of 0.05%, guaranteeing a system without overvoltages or the accelerated degradation of the components due to magnetic conductivity. Full article
(This article belongs to the Special Issue System Modeling, Control Theory, and Their Applications)
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15 pages, 2625 KiB  
Article
A Novel Single-Phase Five-Level Current-Source Inverter Topology
by Mayas Fakher Aldin and Kfir Jack Dagan
Electronics 2024, 13(7), 1213; https://doi.org/10.3390/electronics13071213 - 26 Mar 2024
Cited by 1 | Viewed by 2456
Abstract
Recent technological advances have renewed the research interest in current-source inverters (CSIs). Nonetheless, CSI research still falls behind its voltage-source counterpart with regards to topologies, modulation, and control. Acknowledging the above, this paper presents a novel single-phase five-level CSI topology. The proposed circuit [...] Read more.
Recent technological advances have renewed the research interest in current-source inverters (CSIs). Nonetheless, CSI research still falls behind its voltage-source counterpart with regards to topologies, modulation, and control. Acknowledging the above, this paper presents a novel single-phase five-level CSI topology. The proposed circuit utilises eight switches and two inductors for the generation of five distinct output levels while maintaining low output voltage THD and dv/dt. Furthermore, by offsetting the inductor currents from a binary 1:2 to a trinary 1:3 ratio, the proposed inverter can generate seven current levels at its output. The inverter offers built-in short-circuit protection and can boost a low input DC voltage to a higher peak AC output voltage. These merits, alongside an electrolytic-capacitor-free design, simple current balancing mechanism, and fault-tolerant characteristics, make it a promising candidate for PV module-integrated inverter (MII) systems. The current topology utilises two inductors but is fully functional with single-inductor operation. The paper provides a functional analysis of the inverter topology alongside the inverter switching states and corresponding conduction paths. A detailed analysis of the inductor current dynamics as well as a current-balancing algorithm for dual- and single-inductor operations are given. The theoretical analysis of the proposed circuit and its functional operation are verified using simulations and experimental results carried out on a laboratory prototype. Full article
(This article belongs to the Special Issue New Trends in Power Electronics for Microgrids)
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15 pages, 6318 KiB  
Article
Experimental Study of Radiated Emission Due to Secondary Common-Mode Current in Buck Converters
by Shotaro Takahashi
Appl. Sci. 2023, 13(21), 11735; https://doi.org/10.3390/app132111735 - 26 Oct 2023
Viewed by 1595
Abstract
High switching frequency and fast switching speed of wide bandgap power semiconductor device-based power converters may increase radiated emissions more than conventional silicon-power device-based power converters. Based on the background, this article experimentally investigates radiated emission sources in buck converters. The experimental system [...] Read more.
High switching frequency and fast switching speed of wide bandgap power semiconductor device-based power converters may increase radiated emissions more than conventional silicon-power device-based power converters. Based on the background, this article experimentally investigates radiated emission sources in buck converters. The experimental system constructed in this article has two common-mode noise paths, the primary common-mode and the secondary common-mode. First, this article outlines that a secondary common-mode voltage source is caused by a primary common-mode current and an imbalance of power supply side impedances, and the secondary common-mode current path acts as a monopole antenna. The common-mode currents and the radiated emissions are measured in an anechoic chamber when the common-mode inductor for each mode is connected. The measurement results show that the primary common-mode current generates the secondary common-mode noise, and the secondary common-mode noise is the dominant source of radiated emission in the experimental system. Full article
(This article belongs to the Section Electrical, Electronics and Communications Engineering)
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14 pages, 6892 KiB  
Article
A Study on a Fully Integrated Coil Based on the LCCL-S Compensation Topology for Wireless EVs Charging Systems
by Junchen Xie, Guangyao Li, Seungjin Jo and Dong-Hee Kim
Appl. Sci. 2023, 13(17), 9672; https://doi.org/10.3390/app13179672 - 27 Aug 2023
Cited by 4 | Viewed by 2287
Abstract
This study proposes a full integration method for the double capacitances and inductance–series (LCCL-S)-compensated inductive power transfer (IPT) of electric vehicles (EVs). The transmitter and receiver coils adopt the unipolar coil, and the compensation inductor is designed as an extended DD coil. Specifically, [...] Read more.
This study proposes a full integration method for the double capacitances and inductance–series (LCCL-S)-compensated inductive power transfer (IPT) of electric vehicles (EVs). The transmitter and receiver coils adopt the unipolar coil, and the compensation inductor is designed as an extended DD coil. Specifically, the use of an extended DD coil enhances the misalignment tolerance of the EVs. When the IPT system is in the misaligned state, a primary transfer path for magnetic flux is established between the transmitter and receiver coils, and a secondary transfer path is established between the extended DD coil and receiver coil. The distance between the two unipolar coils of the extended DD coil is optimized to maximize the magnetic flux on the secondary transfer path, thereby increasing the total power of the system misaligned state. Simultaneously, the most suitable turns and inner diameter of the extended DD coil are designed by using the finite element method (FEM) simulation tool. In order to verify the performance of the proposed integrated coil method, a 3.3 kW experimental prototype with a 100 mm air gap was constructed and compared with the conventional integration method under the same conditions. The experimental results show that the proposed magnetic coupling structure maintains at least a 63.6% well-aligned value at a door-to-door 150 mm misaligned state, and the output power of the system is 1.05 kW higher than that of the traditional integration method without extra control algorithms. Full article
(This article belongs to the Special Issue Wireless Power Transfer Systems)
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13 pages, 5702 KiB  
Article
Near-Field Coupling Effect Analysis of SMD Inductor Using 3D-EM Model
by Gyeong Ryun Choi, HyongJoo Kim, Yonggi Hong, Joosung Hwang, Euihyuk Kim and Wansoo Nah
Electronics 2023, 12(13), 2845; https://doi.org/10.3390/electronics12132845 - 27 Jun 2023
Viewed by 2472
Abstract
In this paper, we propose a methodology for analyzing the near-field coupling between two surface mount device (SMD) inductors using a 3-dimensional electromagnetic (3D-EM) model. To develop the 3D-EM model, we first constitute the equivalent circuit of the SMD inductor from the measured [...] Read more.
In this paper, we propose a methodology for analyzing the near-field coupling between two surface mount device (SMD) inductors using a 3-dimensional electromagnetic (3D-EM) model. To develop the 3D-EM model, we first constitute the equivalent circuit of the SMD inductor from the measured impedance and derive the loss tangent using circuit parameters. Secondly, the loss tangent using damped harmonic oscillator model is introduced to extract the effective permeability of core magnetic material in the SMD inductor. The optimization algorithm is used to compare the two loss tangents. Then the effective permeability is used in the magnetic material for the 3D-EM modeling of the SMD inductor. The validity of the proposed 3D-EM model is confirmed by comparing the impedance and S-parameters obtained from both measured and EM-simulated values for the two near-field coupled SMD inductors. Finally, the near-field coupling effects between the two adjacent SMD inductors are visualized in terms of coupling path visualization (CPV) using the proposed 3D-EM model, which demonstrates its usefulness for near-field coupling analysis. Full article
(This article belongs to the Topic EMC and Reliability of Power Networks)
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15 pages, 888 KiB  
Article
Wideband Cascaded and Stacked Receiver Front-Ends Employing an Improved Clock-Strategy Technique
by Arash Abbasi and Frederic Nabki
J. Low Power Electron. Appl. 2023, 13(1), 14; https://doi.org/10.3390/jlpea13010014 - 2 Feb 2023
Cited by 1 | Viewed by 2519
Abstract
A wideband cascaded receiver and a stacked receiver using an improved clock strategy are proposed to support the software-defined radio (SDR). The improved clock strategy reduces the number of mixer switches and the number of LO clock paths required to drive the mixer [...] Read more.
A wideband cascaded receiver and a stacked receiver using an improved clock strategy are proposed to support the software-defined radio (SDR). The improved clock strategy reduces the number of mixer switches and the number of LO clock paths required to drive the mixer switches. This reduces the dynamic power consumption. The cascaded receiver includes an inverter-based low-noise transconductance amplifier (LNTA) using a feed-forward technique to enhance the noise performance; a passive mixer; and an inverter-based transimpedance amplifier (TIA). The stacked receiver architecture is used to reduce the power consumption by sharing the current between the LNTA and the TIA from a single supply. It utilizes a wideband LNTA with a capacitor cross-coupled (CCC) common-gate (CG) topology, a passive mixer to convert the RF current to an IF current, an active inductor (AI) and a 1/f noise-cancellation (NC) technique to improve the noise performance, and a TIA to convert the IF current to an IF voltage at the output. Both cascaded and stacked receivers are simulated in 22 nm CMOS technology. The cascaded receiver achieves a conversion-gain from 26 dB to 36 dB, a double-sideband noise-figure (NFDSB) from 1.4 dB to 3.9 dB, S11<10 dB and an IIP3 from 7.5 dBm to 10.5 dBm, over the RF operating band from 0.4 GHz to 12 GHz. The stacked receiver achieves a conversion-gain from 34.5 dB to 36 dB, a NFDSB from 4.6 dB to 6.2 dB, S11<10 dB, and an IIP3 from 21 dBm to 17.5 dBm, over the RF operating band from 2.2 GHz to 3.2 GHz. The cascaded receiver consumes 11 m from a 1 V supply voltage, while the stacked receiver consumes 2.4 m from a 1.2 V supply voltage. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things)
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