A New Type of DC-DC Buck Converter with Soft Start Function and Reduced Voltage Stress

Abstract

This paper introduces a novel topology called the dual-path step-down converter with auxiliary switches to minimize voltage stress and enable wide voltage conversion ranges. The proposed dual-path step-down converter with auxiliary switches, which uses an inductor and flying capacitor as power conversion components, helps to reduce the voltage stress on the power switches. By adding auxiliary switches, the proposed topology achieves the same voltage conversion ratio range as that of a conventional buck converter. Additionally, soft-start technology is incorporated to reduce the initial inrush current. Furthermore, this paper introduces a system-level design procedure for DC-DC converters. Designed for low-power applications with lithium-ion (Li-ion) batteries, the proposed converter steps down the battery voltage to 1.2 V. With a 380 nH inductor and a 5 µF output capacitor, the converter attains a peak efficiency of 90% under the conditions of 2.7 V to 1.2 V conversion.

1. Introduction

In the current era of rapid technological progress, a diverse range of electronic devices show trends of being multifunctional, low-power, miniaturized, portable, and high-performing. From smartphones and wearable devices to laptops, as well as complex industrial control systems and communication base stations, these devices contain many electronic modules with different functions inside. Each module needs a stable and proper power supply to ensure its correct operation and reach the best performance [1]. Power management chips (PMICs), as the key part in the power supply structure of electronic devices, are in charge of converting the input power source (such as the DC voltage from batteries or external power adapters) into power that meets the specific voltage and current needs of each module [2]. The performance of these chips is directly related to important aspects like the reliability, battery life, operational efficiency, and electromagnetic compatibility of the whole electronic device [3], especially for low-power systems.

The current mainstream semiconductor processes are divided into III-V compound semiconductor processes, which includes the Gallium Arsenide (GaAs) process, Gallium Nitride (GaN) process, and Silicon Carbide (SiC) process, and silicon-based processes, like the CMOS process, Bipolar-CMOS process, and Silicon-on-Insulator (SOI) process. The advantages of III-V compound power switches are their large bandgap and suitability for high-temperature and high-power occasions. However, their high price, relatively large size, and more problems with the connection of silicon-based process chips limit the application of III-V compound switches in power management chips [4]. However, with the high-speed development of silicon-based semiconductor process, the feature size of the transistors continues to reduce. Silicon-based semiconductor power switches stimulate the development of power management chips under the advantages of low price, ease of integration, and relatively small size [5].

As low-power systems continue to evolve and CMOS fabrication processes shrink, the operating voltage required by these systems—typically less than or equal to 1.2 V—becomes much lower than the voltage supplied by lithium-ion (Li-ion) batteries. Consequently, there is a critical need for power management integrated circuits (PMICs) that offer wide voltage conversion ratios (VCRs) and high efficiency [6].

The conventional buck converter (CBC), a traditional step-down DC-DC topological structure, is often used in practical applications to reduce a relatively high DC input voltage to the desired lower output voltage level [7]. In 2011, M. Du designed a new DC-DC converter based on the CBC [8]. However, the switches in a CBC withstand relatively high voltage stresses during operation [9]. When one switch is turned on, the other switch of the CBC will bear a voltage stress equal to the input voltage, which means it requires a relatively high voltage withstand rating. Switches with a high voltage withstand rating usually have larger on-resistance and parasitic capacitance, causing an increase in switching losses and hindering the further development of the buck circuit in high-frequency and high-efficiency application situations [10]. Also, high voltage stress can lead to reliability problems in the switching transistor, like breakdown failures, thus reducing the stability and service life of the whole power supply system [3,11].

In 2020, Katsuhiro Hata proposed the type 3 DPSD topology, in which the maximum voltage stress on the switches is limited to V_IN–V_OUT. This effectively reduces the voltage stress. However, its step-down conversion ratio range is limited to 0 to 0.5 [12]. In 2021, Professor Shaowei Zhen from the University of Electronic Science and Technology of China proposed a DC-DC converter based on the type 4 DPSD topology [13]. Although the maximum voltage stress of the switch was reduced to V_IN–V_OUT, the range of the step-down voltage conversion ratios (VCRs) was only 0–0.5. In 2022, Guigang Cai from the University of Macau proposed the parallel inductor buck, called SC-parallel-inductor hybrid buck (CPL-Buck) [14]. Although this structure reduces the voltage stress on the switch tube, it employs six switches, has a relatively complex structure, and cannot achieve a step-down conversion ratio range from 0 to 1. To overcome the above limitations, we propose a new topological structure, called dual-path step-down topology with auxiliary switches. The proposed topological structure aims to effectively reduce the voltage stress of the switch while maintaining the same step-down conversion range as the Buck circuit, thereby improving the overall performance of the power management chip. Due to the effect of the flying capacitor and auxiliary switches, this topology enables a rational distribution of the voltage stress across the switching devices during operation, thereby preventing the occurrence of excessive voltage stress.

In the context of DC-DC converters, the soft-start function plays a crucial role in ensuring the smooth and reliable operation of the system. When the system is powered on, the input capacitor charges quickly, leading to a large inrush current that can cause several issues [15]. This inrush current, if not properly controlled, may damage the internal components of the power management chip and generate significant electromagnetic interference (EMI). This interference could disrupt the performance of both the input power source and other connected peripheral components, potentially compromising the stability of the entire system.

To mitigate these risks, the soft-start function is designed to gradually increase the output voltage and current from zero to the rated values during the startup phase. This controlled ramp-up helps to limit the inrush current, preventing voltage overshoot and current spikes, which in turn enhances system reliability and reduces the thermal and electrical stresses on the components. For the power management chip based on the proposed topology, where the interaction between components is complex, the soft-start mechanism becomes even more critical [16]. A well-implemented soft-start function ensures that the system starts up smoothly, thus improving the overall stability and longevity of both the chip and the entire low-power electronic device [17,18].

This work proposes a dual-path step-down converter with auxiliary switches and soft start function. The proposed topology relieves voltage stress on switches that are lower than the input voltage, and its VCRs range from 0 to 1. The proposed converter is designed with a 65 nm CMOS process. This paper is organized as follows. Section 2 shows the structural and functional features of the proposed topology. The loop structure of the proposed converter and soft-start circuit is given in Section 3. Section 4 shows the simulation results. Finally, the conclusion is given in Section 5.

2. The Proposed Topology

2.1. Topology Transformation

The CBC, composed of power transistors S₁ and S₂, inductor L, and output capacitor C_O as shown in Figure 1a, features a simple topological structure which is the most widely used. Its output range can cover from input voltage to GND. However, the maximum voltage stress on the switching transistor reaches the input voltage. Figure 1b presents the topological structure of the T4 DPSD. It is composed of power transistors S_1–3, inductor L, and two capacitor C_F and C_O. Although the T4 DPSD reduces the switching voltage stress, its VCRs range is only 0 to 0.5.

By combining the advantages of both the CBC and T4 DPSD, the dual-path step-down converter with auxiliary switches achieves both wide-range voltage conversion ratios and reduced switching voltage stress. It is shown in Figure 2.

2.2. Operation of the Proposed Topology

Figure 3 illustrates the structural design of the proposed topology in detail, where D represents the duty cycle, and T_SW denotes the unit period during normal operation of the topology. In Figure 3, the gray switches indicate that the switches are open, while the black switches represent that the switches are closed. It can be seen that the topology mainly consists of an inductor L, a flying capacitor C_F, an output capacitor C_O, and five switches S_1–5.

Figure 3 provides a comprehensive illustration of the operating principle of the proposed topology. Specifically, during the Φ1 phase, S₂ and S₅ are switched on while S₁, S_3, and S₄ are in the off state. As a result, a series connection is established between C_F and L. At this point, C_F charges the inductor. The situation changes when the operation reaches Φ₂, where S₁, S_3, and S₄ are on and S₂ and S₅ are off. At this point, C_F is charged to the V_IN–V_OUT voltage level. At the same time, L discharges to the load.

2.3. Step-Down Conversion Ratios

Figure 3 demonstrates that the V_Y node voltage alternates between 2V_OUT–V_IN and V_OUT, driven by C_F and the V_X node voltage switching between V_OUT and V_IN. Based on this, the voltage conversion ratios of the proposed topology are calculated using the voltage-second balance method on inductor L:

$$(V_{IN}-V_{OUT})D{T}_{SW}-V_{OUT}(1-D)T_{SW}=0$$

(1)

$${\displaystyle \frac{V_{OUT}}{V_{IN}}}=D$$

(2)

where D is the duty ratio, V_IN/V_OUT is the voltage conversion ratio, and T_SW represents a switching period of the topology, which means one operating cycle of the topology. Like the CBC, the proposed converter achieves a full range of VCRs.

2.4. Switch Voltage Stress Reduction

In addition, during phase Φ1, switches S₁ and S₃ experience a voltage stress of V_IN − V_OUT, while S₄ is subjected to V_OUT. In phase Φ2, the voltage stress on S₂ is V_IN − V_OUT, and S₅ bears V_OUT. Thanks to the presence of C_F, the proposed topology achieves reduced voltage stresses across its switches compared to the CBC topology [7].

3. Circuit Implementation

This section provides a detailed depiction of the circuit implementation of the proposed converter. The overall structure of the converter is shown in Figure 4, which comprises switches S₁ to S₅ and the voltage-negative feedback controller.

3.1. Control Circuit

The proposed converters’ system can be roughly divided into the control domain and power domain, as shown in Figure 4.

The power domain includes power transistors and gate drivers, and the control domain includes an error amplifier (EA), soft start circuit, bandgap, oscillator (OSC), and timing controller.

In the power stage, the power switches S₂ and S₅ are turned ON, while S₁, S₃, and S₄ are turned OFF during Φ1; during Φ2, S₁, S₃, and S₄ are turned ON, while S₂ and S₅ are turned OFF. The voltage at V_Y can fall below the ground level during Φ1 due to the discharge of C_F. During Φ2, V_X reaches V_IN because S₁ closes. To minimize the number of off-chip components and simplify the circuit, S₃ and S₁ are implemented using PMOS transistors. The remaining switches are implemented with NMOS transistors.

In our design, the output voltage of the converter will be fed back into the negative voltage feedback loop. The error signal, resulting from the comparison between V_OUT and V_refss which is generated by the soft start circuit, undergoes comparison with the ramp signal from the oscillator. This generates a square wave signal that controls the duty cycle. To ensure proper operation of the power stage, level shifters are included in the design [7].

Therefore, to meet the performance requirements and ensure the functioning of the converter, Figure 5 presents the design flowchart of the proposed converter. The converter design begins with defining key specifications before proceeding to implement the control loop modules including bandgap reference, LDO regulator, error amplifier (EA), and oscillator (OSC). Subsequently, the power stage circuitry is constructed with optimized passive components and properly sized power switches, followed by critical loop compensation tuning. The design is finalized only after rigorous verification confirms all input/output characteristics and efficiency metrics meet target requirements, completing the comprehensive power converter development process.

3.2. Soft-Start Circuit

During the start-up phase of a DC-DC converter, a significant voltage overshooting or large inrush current often occurs due to the substantial difference between the reference voltage and the output feedback voltage applied to the error amplifier [18]. For instance, a pulse-skipping soft-start circuit has been proposed to control the reference voltage of the error amplifier, effectively restraining the inrush current during start-up [19]. Additionally, an on-chip soft-start technique utilizing a staircase waveform signal generator to control the error amplifier’s output has demonstrated effectiveness in preventing inrush current and output voltage overshoot [20]. These approaches highlight the importance of managing the error amplifier’s input during start-up to ensure a smooth transition and stable operation of DC-DC converters. This article also describes a soft start circuit as depicted in Figure 6 [21,22].

During the start-up phase of a DC-DC converter, a significant voltage overshooting or large inrush current often occurs due to the substantial difference between the reference voltage and the output feedback voltage applied to the error amplifier. For instance, a pulse-skipping soft-start circuit has been proposed to control the reference voltage of the error amplifier, effectively restraining the inrush current during start-up [19]. Additionally, an on-chip soft-start technique utilizing a staircase waveform signal generator to control the error amplifier’s output has demonstrated effectiveness in preventing inrush current and output voltage overshoot [20]. These approaches highlight the importance of managing the error amplifier’s input during start-up to ensure a smooth transition and stable operation of DC-DC converters. This article also describes a soft start circuit as depicted in Figure 6 [21,22].

In Figure 6, the soft start circuit is formed by comparators CMP1–CMP2, inverters INV1–INV2, transistors M₁–M₁₁, and capacitors C₁–C₂.

At first, the output voltage (V_refss) is set at zero because there is no charge on the C₂. V_refss is lower than the reference voltage (V_ref), making M₁ on so that the current mirrors M_3–6, and M₁₀ start to work.

By designing the dimensions of the transistor, the current flowing through M₆ is slightly larger than that of M₅. At this point, C₁ is charged continuously. When the voltage of C₁ is greater than V_ref, M₁₁ is on, the current flowing through M₁₁ charges C₂, and V_refss slowly becomes larger. At the same time, the output of CMP2 is inverted and delayed by INV2, causing M₈ on, grounding C₁. Then, M₈ is off keeping C₁ charged again. Due to the periodic charging and discharging of C₁, a ramp voltage (V_ramp) is formed, causing V_refss to slowly become larger until it is the same as V_ref.

4. Simulation Result and Discussions

Here is the simulation result of the soft-start circuit in Figure 7.

This work, simulated in a 65 nm CMOS process, occupies an active area of 1.58 mm², as shown in Figure 8. The layout consists of power switches, gate drivers, and control circuits.

For C_O, it can be obtained from the capacitor charge formula:

$$\Delta V_{OUT}\le {\displaystyle \frac{1}{C_O}}{\displaystyle {\int }_0^{D{T}_{SW}}{I}_{LOAD}d\mathrm{t}}={\displaystyle \frac{I_{LOAD}D{T}_{SW}}{C_O}}$$

(3)

$$C_O\ge {\displaystyle \frac{I_{LOAD}{V}_{OUT}{T}_{SW}}{V_{IN}\Delta V_{OUT}}}$$

(4)

where ∆V_OUT represents the output ripple voltage, I_LOAD represents the load current. After subsequent simulation verification and comprehensive consideration, the final choice for C_O was 5 µF. To ensure the system always operates in continuous conduction mode (CCM), the peak-to-peak inductor current and the load current must satisfy the following relationship:

$$\Delta I_L={\displaystyle \frac{1}{L}}{\displaystyle {\int }_0^{D{T}_{SW}}{V}_{L}d\mathrm{t}}={\displaystyle \frac{1}{L}}{\displaystyle {\int }_0^{D{T}_{SW}}\left(V_{IN}-V_{OUT}\right)d\mathrm{t}}$$

(5)

$${\displaystyle \frac{\Delta I_L}{2}}\le I_{LOAD}$$

(6)

$$L\ge {\displaystyle \frac{V_{OUT}{T}_{SW}\left(V_{IN}-V_{OUT}\right)}{2V_{IN}{I}_{LOAD}}}$$

(7)

where ∆I_L represents the peak-to-peak inductor ripple current. After simulation verification, the value of L is selected as 380 nH. As for the capacitor C_F, currently, there is relatively little research on its value. We have set its value at 80 nF to facilitate the compensation of the system.

This experiment used a 380 nH external inductor, an 80 nF external capacitor for C_F, and a 5 µF external capacitor for C_O, shown in

Table 1. Main design parameters of the proposed converter.

Parameter	Value
Output capacitor, Co	5 µF
Inductor, L	380 nH
Flying capacitor, CF	80 nF
NMOS power switch	35 × 600 µm/0.5 um
PMOS power switch	70 × 600 µm/0.5 um
Output voltage, VOUT	1.2 V
Expected load current	200 mA

. The function of this converter is to convert 3.3 V into an output voltage of 1.2 V. Currently, much of the research on DC-DC converters is being conducted at a switching frequency of 10 MHz, which has become a hot topic in the field [23,24,25]. The higher frequencies increase switching losses but reduce the size of inductors and filters, enabling a more compact design and improving system response speed. While lower frequencies reduce switching losses, they increase component size and affect dynamic response. So, in this design, a working frequency of 10 MHz was selected for the DC-DC converter, based on a comprehensive consideration of switching losses, component size, system efficiency, fast response, and small volume.

For the size selection of power MOSFETs, it is essential to ensure a low on-resistance to maintain the load capability of the switching transistor circuit and avoid performance degradation due to current limitations. At the same time, the transistor’s switching performance and process adaptability must be ensured. A shorter transistor gate length improves switching speed and reduces switching losses, making it suitable for high-frequency applications [26,27]. Therefore, after comprehensive consideration, the sizes of the NMOS and PMOS power switching transistors were determined to be 35 × 600 µm/0.5 µm and 70 × 600 µm/0.5 µm.

Figure 9 shows the output voltage waveforms of the proposed converter with and without the soft-start circuit under the conditions of a 3.3 V input voltage and a 100 mA load current. It can be observed that without the soft-start circuit, a significant voltage deviation occurs between the output voltage and the expected value during the initial start-up phase. This causes the error amplifier to exit its linear operating region, while the comparator generates a PWM signal with a large duty cycle, forcing the output voltage to rapidly approach the reference voltage. However, due to the demagnetization delay of the inductor current and the low loop gain and bandwidth during start-up period, the converter’s feedback loop exhibits a certain lag. During the inductor demagnetization phase, the released energy superimposes onto the output voltage, resulting in voltage overshoot, which may damage the circuit. With the soft-start circuit, the output voltage increases gradually and stabilizes near the reference voltage, significantly mitigating the overshoot issue.

Figure 10a shows the simulation results of the time control signal when V_IN = 3.3 V and I_LOAD = 100 mA. Figure 10b represents the simulation results of the relationship between the duty cycle D of the converter and I_LOAD under the condition V_IN = 3.3 V. According to Figure 10b, when I_LOAD is small, the actual value of the D is approximately the same as the theoretically calculated value of V_OUT/V_IN (36.4%). However, as I_LOAD increases, the D of the converter will gradually be larger than its theoretically calculated value. As the load current increases, the inductor requires more energy to maintain the output. Therefore, in order to ensure that the output remains constant, the time for C_F to charge the inductor needs to be extended, that is, D needs to increase. The voltage across C_F will gradually decrease during the inductor charging phase. This situation is not obvious when the load is light, but when the load is heavy, this phenomenon will be magnified, thus further increasing the charging gain time of the inductor current. Therefore, D will increase as I_LOAD increases. According to Figure 10b, when the load current is less than 0.1 A, the duty cycle can be approximately regarded as being unaffected by the load current.

To detect the robustness of the converter, the waveform of the converter’s output voltage when the input voltage undergoes an instantaneous change is shown in Figure 11. At Time = 90 µs, V_IN changes from 2.7 V to 3.3 V. At this time, the V_OUT will experience a brief spike fluctuation, with the peak voltage reaching 1.215 V. After this short-term fluctuation, the output voltage continues to be stably output.

Figure 12 presents the simulated efficiency versus load current characteristics of the converter under different input voltages. The converter achieves a peak efficiency of 90.6% at V_IN = 2.7 V and I_LOAD = 70 mA. Under higher step-down ratios with V_IN = 3 V and V_IN = 3.3 V, the peak efficiency remains above 88%.

Table 2. Performance summary and comparison.

	This Work *	[8] JSSC 2011 #	[12] APEC 2020 #	[13] ISCAS 2021 *	[14] JSSC 2022 #
Process	65 nm CMOS	0.35 µm CMOS	PCB	0.18 µm BCD	65 nm CMOS
Topology	DPSD with Auxiliary Switches	Buck	DPSD	DPSD	CPL-Buck
Frequency	10 MHz	5 MHz	100 kHz	1 MHz	2 MHz
Peak Efficiency	90.6%	91%	97.1%	95.6%	92.9%
Input Voltage [V]	2.7–4	2.7–4.2	48	2.7–5	3.0–4.2
Output Voltage [V]	1.2	N/A	12	1.2	0.6–1.0
Number of Power Switches	5	2	3	3	6
Main Switch Voltage Stress [V]	VIN–VOUT, VOUT	VIN	VIN–VOUT	VIN–VOUT	VIN–VOUT, VOUT
Topology VCRs	D	D	D/(1 + D)	D/(1 + D)	D/(1 + 2D) or D/(1 + D)

* Based on simulation results; # Based on measurement results.

presents the summary and comparison with the state-of-the-art. The proposed converter uses five CMOS power switches but still achieves a conversion efficiency of over 90%. As shown in Table 2, the proposed converter maintains comparable peak efficiency while achieving lower voltage stress on power switches compared to reference [8]. Furthermore, the adopted topology demonstrates wider step-down conversion ratios than those in references [12,13,14], enabling broader application scenarios.

5. Conclusions

This article has presented a dual-path step-down converter with auxiliary switches and soft-start circuit. The proposed converter, designed for low-power systems, uses a 65 nm CMOS process with a layout area of only 1.58 mm². The converter can realize lithium-ion battery voltage to 1.2 V voltage conversion and output more than 600 mA current load capacity, reaching a peak efficiency of 90%. The proposed topology can not only feature a full range of buck conversion ratios but also reduce switching voltage stress in the power stage circuit. Due to the soft-start circuit design, large inrush is suppressed. These design points improve the reliability and lifetime of the DC-DC converter, making it a new power-supply choice for low-power systems.