Search Results (277)

The rapid development of smart energy infrastructures and renewable energy systems requires advanced sensing solutions that provide high accuracy, expandability, and stability under real operating conditions. However, conventional gas monitoring systems are predominantly based on resistive or voltage-output sensors, which require complex analog front-end circuits and analog-to-digital conversion, leading to increased system complexity, cost, and susceptibility to electromagnetic interference. This paper tackles this limitation by proposing a frequency-domain sensing approach for multichannel monitoring of biogas plant parameters. The objective of this study is to develop and experimentally validate an extendable sensing architecture based on autogenerator microelectronic gas transducers with direct gas concentration–frequency conversion and FPGA-based digital acquisition. The proposed method is grounded in a physical–mathematical model of the space-charge capacitance of gas-sensitive semiconductor structures derived from Poisson’s equation, facilitating analytical formulation of conversion and sensitivity functions. A multichannel FPGA-based measurement system is implemented to process frequency signals without analog conditioning or ADC stages. Experimental validation was performed for CH₄ (0–85%), CO₂ (0–60%), H₂, NH₃, and H₂S (1–20,000 ppm). The results demonstrate measurement uncertainty within 0.25–0.5%, with sensitivity reaching 350–748 Hz/ppm for H₂, 455–750 Hz/ppm for NH₃, and 253–375 Hz/ppm for H₂S, while methane and carbon dioxide sensitivities reach up to 112 kHz/% and 98.7 kHz/%, respectively. Spectral analysis in the LTE-1800 band confirms improved noise immunity (up to 4.5×) and extended transmission capabilities. A 12-channel FPGA-based monitoring system (RDM-BP-1) with a 1 s sampling interval, IP67 protection, and wireless connectivity is developed and validated. The proposed architecture eliminates analog signal conditioning, reduces hardware complexity, and provides an easily expandable and reliable sensing solution for smart buildings, renewable energy systems, and cloud-integrated energy infrastructures. Full article

As the number of elderly individuals living alone increases, the risk of fall-related accidents correspondingly rises, underscoring the need for rapid fall detection systems. Because falls are difficult to predict in terms of location, detection systems must be deployed in a distributed manner, which in turn requires compact and low-power implementations. Unlike camera sensors, radar sensors do not raise privacy concerns and are not limited by line-of-sight constraints. Moreover, compared with wearable sensors, radar enables continuous monitoring without user intervention. However, prior radar-based approaches incur high computational complexity, leading to increased power consumption and larger hardware area, thereby necessitating efficient hardware design. This paper proposes a lightweight fall detection system based on continuous-wave (CW) radar and a binarized convolutional neural network (BCNN). Radar signals are preprocessed using short-time Fourier transform (STFT) to generate binary spectrograms, which are then fed into a BCNN-based classification network. The proposed system performs binary classification of five fall activities and seven non-fall activities with an accuracy of 96.1%. The preprocessing module and classification network were implemented as hardware accelerators and integrated with a microprocessor in a system-on-chip (SoC) architecture on a field-programmable gate array (FPGA). Compared with the software implementation, the proposed hardware achieved speedups of 387.5× and 86.7× for the preprocessing and classification modules, respectively. Furthermore, the overall system processing time was 2.58 ms, corresponding to an 89.5× speedup over the software baseline. Full article

High-precision time and frequency references are essential for satellite navigation, deep-space exploration, and space science missions. To address the large size, high power consumption, and limited integration of conventional Passive Hydrogen Maser (PHM) servo electronics based on discrete analog chains, this paper proposes a miniaturized digital servo architecture for PHMs based on software-defined radio (SDR) and a field-programmable gate array (FPGA). The AD9364 is used as an integrated RF front end for microwave interrogation signal generation, receiver down-conversion, and analog-to-digital conversion (ADC), while digital demodulation, discriminator construction, and closed-loop control are implemented in the FPGA. A dual-frequency interrogation and time-division multiplexing scheme is introduced to separate the atomic and cavity responses, and an oversampling-based processing method combining outlier rejection and averaging decimation is adopted to improve the observation accuracy and noise immunity of weak error signals. Experimental results demonstrate stable closed-loop locking of the atomic transition spectrum, achieving a frequency stability of 1.46 × 10⁻¹² at 1 s, while significantly improving the compactness and integration level of the servo electronics. Full article

Selectively modulating specific brain-rhythm bands with physical stimuli helps both to reveal neural mechanisms and to provide non-pharmacological treatment avenues for brain disorders. This study proposes and implements a multi-channel transcranial magneto-acoustic stimulation driving system based on amplitude-modulated (AM) sine waves (AM-TMAS) intended to supply a reliable hardware platform for noninvasive, focal low-frequency rhythmic electrical stimulation of deep-brain structures. The driving system implements a 64-channel AM module based on an FPGA plus high-speed DACs. Multi-channel precision is achieved via a unified high-speed clock and a global UPDATE trigger. To overcome the large separation between envelope and carrier frequencies, we developed a high-fidelity AM waveform generation method based on DDS + LUT + envelope multiplication. The algorithm first centers the carrier samples to preserve waveform symmetry, then applies LUT-based envelope coefficients and fixed-point envelope multiplication, enabling high-precision AM outputs with carrier frequencies from 100 kHz to 2 MHz and envelope frequencies from 0.1 Hz to 100 kHz. We tested the system’s rhythmic multi-channel AM output performance across frequencies and also measured magneto-acoustic-coupled rhythmic electrical signals produced by the AM-TMAS driving setup. Any single channel reliably produced high-fidelity AM waveforms with a 500 kHz carrier and 8 Hz/40 Hz envelopes; the measured carrier was 499.998 kHz with excellent frequency stability. Both envelope and carrier frequencies are flexibly tunable. At the nominal 500 kHz carrier, envelope fidelity was further quantified: the extracted envelopes achieved NRMSEs of 1.0795% (8 Hz) and 1.9212% (40 Hz), confirming high-fidelity AM synthesis. Under a 0.3 T static magnetic field, the AM-TMAS driving system generated rhythmic electrical responses in physiological saline that carried the expected 40 Hz envelope. The proposed AM-TMAS driver achieves high accuracy in AM waveform generation and robust multi-channel performance, and—when combined with an external static magnetic field—can produce rhythmically modulated magneto-acoustic electrical stimulation. This platform provides a practical technical tool for brain-function research and the development of rhythm-targeted neuromodulation therapies. Full article

Optical coherence tomography (OCT) is a non-invasive, high-resolution imaging technique widely used in medical diagnosis, biomedical research and other fields. It plays an important role in the early detection and accurate diagnosis of diseases. The superluminescent light-emitting diode (SLED) is the ideal light source for OCT systems, where the stability of its drive current and operating temperature directly determines the imaging quality of OCT. Existing driving and temperature control schemes for similar light sources predominantly rely on microcontrollers or field programmable gate arrays (FPGAs), a reliance which often results in complex system architectures and difficulties in balancing simplicity with control precision. To address these issues, a stable and compact SLED source driver module designed for OCT was developed in this study, integrating both a constant-current drive circuit and a temperature control circuit. The negative feedback control and improved current-limiting protection are employed in the constant-current drive circuit to maintain stable SLED operation and reduce the circuit footprint. A miniature dedicated temperature control chip is adopted in the temperature control circuit. The operating temperature of the SLED is acquired by linearizing the negative temperature coefficient (NTC) thermistor value and regulated through a proportional-integral-derivative (PID) compensation circuit. The size of the fabricated module (including casing) is less than 10 × 8 × 3 cm³. Experimental results show that the driver module achieves a drive current control accuracy of 0.1% and a temperature control accuracy of 0.01 °C. The output optical power fluctuation is less than 0.005 mW and the average axial resolution for OCT is 6.5992 μm with a standard deviation of 0.0107 μm. This light source driver module successfully balances control precision with structural simplicity, demonstrating excellent applicability in OCT systems. Full article

Vision-only driving perception systems are highly sensitive to illumination variations, particularly under low-light conditions where reduced contrast and structural degradation impair detection and segmentation accuracy. Rather than treating enhancement as a post-processing step, this work investigates the system-level impact of relocating low-light enhancement to the FPGA-based front end within a heterogeneous FPGA–ARM architecture. A hardware-accelerated visual pipeline is designed to perform color space conversion, fixed-point convolutional enhancement, and multi-channel fusion prior to high-level perception on the ARM processor. Experimental results demonstrate that the proposed FPGA-based front-end enhancement introduces only 13 ms of additional processing latency, which executes in parallel with the preceding frame’s neural network inference and therefore imposes zero net overhead on the end-to-end pipeline. In contrast, an equivalent software-based back-end enhancement approach would add its full processing time serially to the inference stage, increasing total system latency proportionally. The system achieves a sustained throughput of 58 fps while supporting real-time multi-task perception including lane detection (YOLOPv2, 539 ms per frame), object detection and emergency braking (YOLOv5, 432 ms per frame), and hardware-level multi-camera synchronization. Full article

Energy efficiency has become a primary bottleneck in hardware platforms supporting machine learning workloads, particularly as modern inference and training tasks demand sustained high-throughput computation. This challenge is further amplified in energy-harvesting and intermittently powered systems, where the available energy budget varies over time. This work introduces a run-time configurable multiply–accumulate (MAC) architecture that dynamically adjusts arithmetic precision to match instantaneous energy availability. The proposed design relies on an internally adaptive multiplier based on bit-level logic compression, enabling controlled modulation of power consumption while preserving numerical robustness. Crucially, the MAC maintains a fixed external operand interface, allowing for seamless precision adaptation without operand reformulation or datapath disruption. The architecture is implemented in System Verilog and evaluated using both ASIC synthesis in a 90 nm CMOS technology and FPGA deployment. Experimental results demonstrate approximately a fourfold improvement in power–delay product (PDP) relative to full-precision operation, with only limited degradation in inference accuracy. Full article

Random number generation is essential in many application domains, including high-energy physics simulations. Implementing Monte Carlo methods that generate samples following a desired probability distribution is particularly challenging on hardware platforms such as FPGAs. Direct implementations of analytical distribution functions are often resource-intensive, making them impractical for real-time systems. An efficient alternative is the use of the inverse cumulative distribution function (CDF), which can be implemented using look-up tables (LUTs). In this approach, a uniformly distributed random number—generated by Linear Feedback Shift Registers (LFSRs)—is used as an address to access LUTs containing discretized x-axis values of the CDF, thereby yielding the target random variable. However, this method presents limited accuracy in low-probability regions of the distribution. To address this issue, this paper proposes a segmented CDF implementation based on multiple LUTs, improving resolution in poorly sampled regions. A cascade of decision logic selects the appropriate memory output, increasing resolution only where necessary while optimizing memory usage. The proposed method was validated through Monte Carlo simulations in particle physics applications, achieving close agreement with theoretical distributions while requiring limited FPGA resources and no DSP blocks. Full article

Accurate measurement of robotic pose is indispensable for large-scale precision manufacturing and robotic calibration, particularly because traditional robotic kinematic models often fall short owing to environmental disturbances and structural uncertainties. Laser tracker systems offer high-precision, large-volume measurement capabilities and are therefore appealing as external references for robot pose estimation; however, their practical efficacy is heavily reliant on optical tracking stability, sensor noise levels, and system robustness. This paper introduces a laser tracker-based framework for measuring robot pose, which integrates PSD-based optical spot sensing, multi-sensor fusion, and simulation-based system analysis. A prototype PSD sensing subsystem has been developed utilizing analog signal conditioning, high-speed A/D sampling, and FPGA-based centroid computation. Bench experiments validate the linearity, geometric sensitivity, and robustness of the PSD sensing chain under controlled spot translations and various ambient illumination conditions. Results demonstrate that the PSD response is nearly linear within a ±0.9 mm spot displacement and that the implementation of an interference optical filter significantly enhances measurement repeatability under background light. At the system level, a comprehensive simulation framework is established wherein PSD measurements are fused with inertial and encoder data via an extended Kalman filter. The simulations explore the effects of process noise tuning, time synchronization, systematic error sources, and control strategies on pose estimation accuracy. Ranging-related effects and error-compensation mechanisms are analyzed within the context of modeling and simulation, providing insights into the interferometric ranging principle underlying the complete laser tracker system. The validation of the prototype alongside simulation results demonstrates that PSD-based optical tracking, combined with multi-sensor fusion and layered error compensation, can effectively improve robustness and positional accuracy. The proposed framework offers valuable guidance for the development and phased validation of laser tracker-oriented robot pose measurement systems in complex industrial environments. Full article

To address the issue of low accuracy and stability in the gyroscope components of the micro-inertial-measurement-unit (MIMU) core units, which limits their application in high-precision scenarios, this paper designs a real-time data acquisition system for array MIMU based on FPGA and ARM. This system establishes a complete data chain encompassing raw data acquisition, real-time processing, multi-source information fusion, data storage, and communication with a host computer. It has been successfully applied to a 100-m pipeline position coordinate measurement scenario. The paper begins by discussing the overall system design, including both hardware circuit and software code development. Attitude update algorithms and measurement accuracy evaluation metrics are also introduced. System functionality is validated through static tests and practical pipeline measurements. Experimental results demonstrate that the system improves the accuracy of a single micro-electro-mechanical system (MEMS) gyroscope by a factor of 7.4 to 7.7. It also enables precise calculation of the pipeline position coordinates over the 100 m distance, achieving a horizontal positioning error of less than 0.0774 m and an elevation positioning error of less than 0.0351 m. These results fully confirm the significant effectiveness of the array design in mitigating gyroscope random errors, providing a reliable technical solution for pipeline measurement. Full article

This paper presents the FPGA implementation and verification of a lightweight one-dimensional convolutional neural network (1D-CNN) pipeline for real-time battery state-of-charge (SoC) estimation in automotive battery management systems. The proposed model employs separable 1D convolution and global average pooling, and applies aggressive structured pruning to reduce the number of parameters from 3121 to 358, representing an 88.5% reduction, without significant accuracy loss. Using quantization-aware training (QAT), the network is trained and executed in INT8, which reduces weight storage to one-quarter of the 32-bit baseline while maintaining high estimation accuracy with a Mean Absolute Error (MAE) of 0.0172. The hardware adopts a time-multiplexed single MAC architecture with FSM control, occupying 98,410 gates under a 28 nm process. Evaluations on an FPGA testbed with representative drive-cycle inputs show that the proposed INT8 pipeline achieves performance comparable to the floating-point reference with negligible precision drop, demonstrating its suitability for in-vehicle BMS deployment. Full article

High-precision phase difference measurement based on field-programmable gate arrays (FPGA) has important application requirements in fields such as high-stability time-frequency transmission, signal synchronization, and precision testing. Addressing the limitations of traditional methods in terms of temperature stability and measurement accuracy, this paper proposes two high-precision phase difference measurement schemes based on the FPGA platform. An eight-parallel-multi-carry chain time-to-digital converter (TDC) and digital dual-mixer time difference (DDMTD) measurement modules are constructed to perform high-precision phase difference measurements on the phase-shifted output signal of the MMCM dynamic phase-shifted module. Results show that at room temperature (25 °C), the single-carry chain TDC exhibits better measurement accuracy than the DDMTD, and the single-carry chain TDC’s measurement error range of 4.7–6.0 ps is superior to the DDMTD’s 20–75 ps error range. Under different temperature conditions, the eight-parallel-multi-carry chain TDC consistently demonstrates superior measurement accuracy, resolution, and temperature stability compared to the single-carry chain TDC. In terms of measurement accuracy, under room temperature conditions, in three sets of phase difference tests (178.5714 ps, 357.1428 ps, and 535.7142 ps), the measurement error of the eight-parallel-multi-carry chain TDC was controlled within 4.6 ps, which is better than the 4.7–6.0 ps error range of the single-carry chain TDC. Average resolution: The average resolution of the single-carry chain TDC was 6.329 ps, while the average resolution of the eight-parallel-multi-carry chain TDC improved to 0.833 ps. Temperature stability: Within the temperature range of 10 °C to 100 °C, the temperature coefficient of the single-carry chain TDC was 0.002127 ps/°C, while the temperature coefficient of the eight-parallel-multi-carry chain TDC decreased to 0.000564 ps/°C. This paper also summarizes the advantages and limitations of the above methods in terms of implementation complexity and robustness, providing a reference for the optimized design of high-precision phase difference measurement technology for FPGA platforms. Full article

In order to achieve better accuracy, modern models have become increasingly large, leading to an exponential increase in computational load, making it challenging to apply them to edge computing. Binary neural networks (BNNs) are models that quantize the filter weights and activations to 1-bit. These models are highly suitable for small chips like advanced RISC machines (ARMs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), system-on-chips (SoCs) and other edge computing devices. To design a model that is more friendly to edge computing devices, it is crucial to reduce the floating-point operations (FLOPs). Batch normalization (BN) is an essential tool for binary neural networks; however, when convolution layers are quantized to 1-bit, the floating-point computation cost of BN layers becomes significantly high. This paper aims to reduce the floating-point operations by removing the BN layers from the model and introducing the scaled weight standardization convolution (WS-Conv) method to avoid the significant accuracy drop caused by the absence of BN layers, and to enhance the model performance through a series of optimizations, adaptive gradient clipping (AGC) and knowledge distillation (KD). Specifically, our model maintains a competitive computational cost and accuracy, even without BN layers. Furthermore, by incorporating a series of training methods, the model’s accuracy on CIFAR-100 is 0.6% higher than the baseline model, fractional activation BNN (FracBNN), while the total computational load is only 46% of the baseline model. With unchanged binary operations (BOPs), the FLOPs are reduced to nearly zero, making it more suitable for embedded platforms like FPGAs or other edge computers. Full article

The ever-increasing need for energy-efficient implementation of AI algorithms has driven the research community towards the development of many hardware architectures and frameworks for AI. A lot of work has been presented around FPGAs, while more sophisticated architectures like CGRAs have also been at the center. However, AI ecosystems are isolated and fragmented, with no standardized way to compare different frameworks with detailed Power–Performance–Area (PPA) analysis. This paper bridges the gap by presenting a unified, fully open-source hardware-aware AI acceleration pipeline that enables seamless deployment of neural networks on both FPGA and CGRA architectures. Built around the Brevitas quantization framework, it supports two distinct backend flows: FINN for high-performance dataflow accelerators and CGRA4ML for low-power coarse-grained reconfigurable designs. To facilitate this, a model translation layer from QONNX to QKeras is also introduced. To demonstrate its effectiveness, we use an autoencoder model for anomaly detection in wind turbines. We deploy our accelerated models on the AMD’s ZCU104 and benchmark it against a Raspberry Pi. Evaluation on a realistic cyber–physical testbed shows that the hardware-accelerated solutions achieve substantial performance and energy-efficiency gains—up to 10× and 37× faster inference per flow and over 11× higher efficiency—while maintaining acceptable reconstruction accuracy. Full article

To address the dual demands of accuracy and real-time performance in power quality disturbance (PQD) recognition for new power system, this paper proposes a lightweight model named the Cross-Channel Attention Three-Layer Convolutional Model (1D-CCANet-3), specifically designed for edge deployment. Based on the one-dimensional convolutional neural network (1D-CNN), the model features an ultra-compact architecture with only three convolutional layers and one fully connected layer. By incorporating a set of cross-channel attention (CCA) mechanisms in the final convolutional layer, the model further enhances disturbance recognition accuracy. Compared to other deep learning models, 1D-CCANet-3 significantly reduces computational and storage requirements for edge devices while achieving accurate and efficient PQD recognition. The model demonstrates robust performance in recognizing 10 types of PQD under varying signal-to-noise ratio (SNR) conditions. Furthermore, the model has been successfully deployed on the FPGA platform and exhibits high recognition accuracy and efficiency in real-world data validation. This work provides a feasible and effective solution for accurate and real-time PQD monitoring on edge devices in new power systems. Full article